edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012-2013 - Mauro Carvalho Chehab
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. unsigned long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = kstrtoul(val, 0, &l);
  52. if (ret)
  53. return ret;
  54. if (l < 1000)
  55. return -EINVAL;
  56. *((unsigned long *)kp->arg) = l;
  57. /* notify edac_mc engine to reset the poll period */
  58. edac_mc_reset_delay_period(l);
  59. return 0;
  60. }
  61. /* Parameter declarations for above */
  62. module_param(edac_mc_panic_on_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  64. module_param(edac_mc_log_ue, int, 0644);
  65. MODULE_PARM_DESC(edac_mc_log_ue,
  66. "Log uncorrectable error to console: 0=off 1=on");
  67. module_param(edac_mc_log_ce, int, 0644);
  68. MODULE_PARM_DESC(edac_mc_log_ce,
  69. "Log correctable error to console: 0=off 1=on");
  70. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  71. &edac_mc_poll_msec, 0644);
  72. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  73. static struct device *mci_pdev;
  74. /*
  75. * various constants for Memory Controllers
  76. */
  77. static const char * const mem_types[] = {
  78. [MEM_EMPTY] = "Empty",
  79. [MEM_RESERVED] = "Reserved",
  80. [MEM_UNKNOWN] = "Unknown",
  81. [MEM_FPM] = "FPM",
  82. [MEM_EDO] = "EDO",
  83. [MEM_BEDO] = "BEDO",
  84. [MEM_SDR] = "Unbuffered-SDR",
  85. [MEM_RDR] = "Registered-SDR",
  86. [MEM_DDR] = "Unbuffered-DDR",
  87. [MEM_RDDR] = "Registered-DDR",
  88. [MEM_RMBS] = "RMBS",
  89. [MEM_DDR2] = "Unbuffered-DDR2",
  90. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  91. [MEM_RDDR2] = "Registered-DDR2",
  92. [MEM_XDR] = "XDR",
  93. [MEM_DDR3] = "Unbuffered-DDR3",
  94. [MEM_RDDR3] = "Registered-DDR3",
  95. [MEM_DDR4] = "Unbuffered-DDR4",
  96. [MEM_RDDR4] = "Registered-DDR4"
  97. };
  98. static const char * const dev_types[] = {
  99. [DEV_UNKNOWN] = "Unknown",
  100. [DEV_X1] = "x1",
  101. [DEV_X2] = "x2",
  102. [DEV_X4] = "x4",
  103. [DEV_X8] = "x8",
  104. [DEV_X16] = "x16",
  105. [DEV_X32] = "x32",
  106. [DEV_X64] = "x64"
  107. };
  108. static const char * const edac_caps[] = {
  109. [EDAC_UNKNOWN] = "Unknown",
  110. [EDAC_NONE] = "None",
  111. [EDAC_RESERVED] = "Reserved",
  112. [EDAC_PARITY] = "PARITY",
  113. [EDAC_EC] = "EC",
  114. [EDAC_SECDED] = "SECDED",
  115. [EDAC_S2ECD2ED] = "S2ECD2ED",
  116. [EDAC_S4ECD4ED] = "S4ECD4ED",
  117. [EDAC_S8ECD8ED] = "S8ECD8ED",
  118. [EDAC_S16ECD16ED] = "S16ECD16ED"
  119. };
  120. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  121. /*
  122. * EDAC sysfs CSROW data structures and methods
  123. */
  124. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  125. /*
  126. * We need it to avoid namespace conflicts between the legacy API
  127. * and the per-dimm/per-rank one
  128. */
  129. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  130. static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  131. struct dev_ch_attribute {
  132. struct device_attribute attr;
  133. int channel;
  134. };
  135. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  136. static struct dev_ch_attribute dev_attr_legacy_##_name = \
  137. { __ATTR(_name, _mode, _show, _store), (_var) }
  138. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  139. /* Set of more default csrow<id> attribute show/store functions */
  140. static ssize_t csrow_ue_count_show(struct device *dev,
  141. struct device_attribute *mattr, char *data)
  142. {
  143. struct csrow_info *csrow = to_csrow(dev);
  144. return sprintf(data, "%u\n", csrow->ue_count);
  145. }
  146. static ssize_t csrow_ce_count_show(struct device *dev,
  147. struct device_attribute *mattr, char *data)
  148. {
  149. struct csrow_info *csrow = to_csrow(dev);
  150. return sprintf(data, "%u\n", csrow->ce_count);
  151. }
  152. static ssize_t csrow_size_show(struct device *dev,
  153. struct device_attribute *mattr, char *data)
  154. {
  155. struct csrow_info *csrow = to_csrow(dev);
  156. int i;
  157. u32 nr_pages = 0;
  158. for (i = 0; i < csrow->nr_channels; i++)
  159. nr_pages += csrow->channels[i]->dimm->nr_pages;
  160. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  161. }
  162. static ssize_t csrow_mem_type_show(struct device *dev,
  163. struct device_attribute *mattr, char *data)
  164. {
  165. struct csrow_info *csrow = to_csrow(dev);
  166. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  167. }
  168. static ssize_t csrow_dev_type_show(struct device *dev,
  169. struct device_attribute *mattr, char *data)
  170. {
  171. struct csrow_info *csrow = to_csrow(dev);
  172. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  173. }
  174. static ssize_t csrow_edac_mode_show(struct device *dev,
  175. struct device_attribute *mattr,
  176. char *data)
  177. {
  178. struct csrow_info *csrow = to_csrow(dev);
  179. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  180. }
  181. /* show/store functions for DIMM Label attributes */
  182. static ssize_t channel_dimm_label_show(struct device *dev,
  183. struct device_attribute *mattr,
  184. char *data)
  185. {
  186. struct csrow_info *csrow = to_csrow(dev);
  187. unsigned chan = to_channel(mattr);
  188. struct rank_info *rank = csrow->channels[chan];
  189. /* if field has not been initialized, there is nothing to send */
  190. if (!rank->dimm->label[0])
  191. return 0;
  192. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  193. rank->dimm->label);
  194. }
  195. static ssize_t channel_dimm_label_store(struct device *dev,
  196. struct device_attribute *mattr,
  197. const char *data, size_t count)
  198. {
  199. struct csrow_info *csrow = to_csrow(dev);
  200. unsigned chan = to_channel(mattr);
  201. struct rank_info *rank = csrow->channels[chan];
  202. ssize_t max_size = 0;
  203. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  204. strncpy(rank->dimm->label, data, max_size);
  205. rank->dimm->label[max_size] = '\0';
  206. return max_size;
  207. }
  208. /* show function for dynamic chX_ce_count attribute */
  209. static ssize_t channel_ce_count_show(struct device *dev,
  210. struct device_attribute *mattr, char *data)
  211. {
  212. struct csrow_info *csrow = to_csrow(dev);
  213. unsigned chan = to_channel(mattr);
  214. struct rank_info *rank = csrow->channels[chan];
  215. return sprintf(data, "%u\n", rank->ce_count);
  216. }
  217. /* cwrow<id>/attribute files */
  218. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  219. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  220. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  221. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  222. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  223. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  224. /* default attributes of the CSROW<id> object */
  225. static struct attribute *csrow_attrs[] = {
  226. &dev_attr_legacy_dev_type.attr,
  227. &dev_attr_legacy_mem_type.attr,
  228. &dev_attr_legacy_edac_mode.attr,
  229. &dev_attr_legacy_size_mb.attr,
  230. &dev_attr_legacy_ue_count.attr,
  231. &dev_attr_legacy_ce_count.attr,
  232. NULL,
  233. };
  234. static struct attribute_group csrow_attr_grp = {
  235. .attrs = csrow_attrs,
  236. };
  237. static const struct attribute_group *csrow_attr_groups[] = {
  238. &csrow_attr_grp,
  239. NULL
  240. };
  241. static void csrow_attr_release(struct device *dev)
  242. {
  243. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  244. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  245. kfree(csrow);
  246. }
  247. static struct device_type csrow_attr_type = {
  248. .groups = csrow_attr_groups,
  249. .release = csrow_attr_release,
  250. };
  251. /*
  252. * possible dynamic channel DIMM Label attribute files
  253. *
  254. */
  255. #define EDAC_NR_CHANNELS 6
  256. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 0);
  258. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 1);
  260. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 2);
  262. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 3);
  264. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  265. channel_dimm_label_show, channel_dimm_label_store, 4);
  266. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  267. channel_dimm_label_show, channel_dimm_label_store, 5);
  268. /* Total possible dynamic DIMM Label attribute file table */
  269. static struct attribute *dynamic_csrow_dimm_attr[] = {
  270. &dev_attr_legacy_ch0_dimm_label.attr.attr,
  271. &dev_attr_legacy_ch1_dimm_label.attr.attr,
  272. &dev_attr_legacy_ch2_dimm_label.attr.attr,
  273. &dev_attr_legacy_ch3_dimm_label.attr.attr,
  274. &dev_attr_legacy_ch4_dimm_label.attr.attr,
  275. &dev_attr_legacy_ch5_dimm_label.attr.attr,
  276. NULL
  277. };
  278. /* possible dynamic channel ce_count attribute files */
  279. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
  280. channel_ce_count_show, NULL, 0);
  281. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
  282. channel_ce_count_show, NULL, 1);
  283. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
  284. channel_ce_count_show, NULL, 2);
  285. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
  286. channel_ce_count_show, NULL, 3);
  287. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
  288. channel_ce_count_show, NULL, 4);
  289. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
  290. channel_ce_count_show, NULL, 5);
  291. /* Total possible dynamic ce_count attribute file table */
  292. static struct attribute *dynamic_csrow_ce_count_attr[] = {
  293. &dev_attr_legacy_ch0_ce_count.attr.attr,
  294. &dev_attr_legacy_ch1_ce_count.attr.attr,
  295. &dev_attr_legacy_ch2_ce_count.attr.attr,
  296. &dev_attr_legacy_ch3_ce_count.attr.attr,
  297. &dev_attr_legacy_ch4_ce_count.attr.attr,
  298. &dev_attr_legacy_ch5_ce_count.attr.attr,
  299. NULL
  300. };
  301. static umode_t csrow_dev_is_visible(struct kobject *kobj,
  302. struct attribute *attr, int idx)
  303. {
  304. struct device *dev = kobj_to_dev(kobj);
  305. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  306. if (idx >= csrow->nr_channels)
  307. return 0;
  308. /* Only expose populated DIMMs */
  309. if (!csrow->channels[idx]->dimm->nr_pages)
  310. return 0;
  311. return attr->mode;
  312. }
  313. static const struct attribute_group csrow_dev_dimm_group = {
  314. .attrs = dynamic_csrow_dimm_attr,
  315. .is_visible = csrow_dev_is_visible,
  316. };
  317. static const struct attribute_group csrow_dev_ce_count_group = {
  318. .attrs = dynamic_csrow_ce_count_attr,
  319. .is_visible = csrow_dev_is_visible,
  320. };
  321. static const struct attribute_group *csrow_dev_groups[] = {
  322. &csrow_dev_dimm_group,
  323. &csrow_dev_ce_count_group,
  324. NULL
  325. };
  326. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  327. {
  328. int chan, nr_pages = 0;
  329. for (chan = 0; chan < csrow->nr_channels; chan++)
  330. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  331. return nr_pages;
  332. }
  333. /* Create a CSROW object under specifed edac_mc_device */
  334. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  335. struct csrow_info *csrow, int index)
  336. {
  337. if (csrow->nr_channels > EDAC_NR_CHANNELS)
  338. return -ENODEV;
  339. csrow->dev.type = &csrow_attr_type;
  340. csrow->dev.bus = mci->bus;
  341. csrow->dev.groups = csrow_dev_groups;
  342. device_initialize(&csrow->dev);
  343. csrow->dev.parent = &mci->dev;
  344. csrow->mci = mci;
  345. dev_set_name(&csrow->dev, "csrow%d", index);
  346. dev_set_drvdata(&csrow->dev, csrow);
  347. edac_dbg(0, "creating (virtual) csrow node %s\n",
  348. dev_name(&csrow->dev));
  349. return device_add(&csrow->dev);
  350. }
  351. /* Create a CSROW object under specifed edac_mc_device */
  352. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  353. {
  354. int err, i;
  355. struct csrow_info *csrow;
  356. for (i = 0; i < mci->nr_csrows; i++) {
  357. csrow = mci->csrows[i];
  358. if (!nr_pages_per_csrow(csrow))
  359. continue;
  360. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  361. if (err < 0) {
  362. edac_dbg(1,
  363. "failure: create csrow objects for csrow %d\n",
  364. i);
  365. goto error;
  366. }
  367. }
  368. return 0;
  369. error:
  370. for (--i; i >= 0; i--) {
  371. csrow = mci->csrows[i];
  372. if (!nr_pages_per_csrow(csrow))
  373. continue;
  374. put_device(&mci->csrows[i]->dev);
  375. }
  376. return err;
  377. }
  378. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  379. {
  380. int i;
  381. struct csrow_info *csrow;
  382. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  383. csrow = mci->csrows[i];
  384. if (!nr_pages_per_csrow(csrow))
  385. continue;
  386. device_unregister(&mci->csrows[i]->dev);
  387. }
  388. }
  389. #endif
  390. /*
  391. * Per-dimm (or per-rank) devices
  392. */
  393. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  394. /* show/store functions for DIMM Label attributes */
  395. static ssize_t dimmdev_location_show(struct device *dev,
  396. struct device_attribute *mattr, char *data)
  397. {
  398. struct dimm_info *dimm = to_dimm(dev);
  399. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  400. }
  401. static ssize_t dimmdev_label_show(struct device *dev,
  402. struct device_attribute *mattr, char *data)
  403. {
  404. struct dimm_info *dimm = to_dimm(dev);
  405. /* if field has not been initialized, there is nothing to send */
  406. if (!dimm->label[0])
  407. return 0;
  408. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  409. }
  410. static ssize_t dimmdev_label_store(struct device *dev,
  411. struct device_attribute *mattr,
  412. const char *data,
  413. size_t count)
  414. {
  415. struct dimm_info *dimm = to_dimm(dev);
  416. ssize_t max_size = 0;
  417. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  418. strncpy(dimm->label, data, max_size);
  419. dimm->label[max_size] = '\0';
  420. return max_size;
  421. }
  422. static ssize_t dimmdev_size_show(struct device *dev,
  423. struct device_attribute *mattr, char *data)
  424. {
  425. struct dimm_info *dimm = to_dimm(dev);
  426. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  427. }
  428. static ssize_t dimmdev_mem_type_show(struct device *dev,
  429. struct device_attribute *mattr, char *data)
  430. {
  431. struct dimm_info *dimm = to_dimm(dev);
  432. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  433. }
  434. static ssize_t dimmdev_dev_type_show(struct device *dev,
  435. struct device_attribute *mattr, char *data)
  436. {
  437. struct dimm_info *dimm = to_dimm(dev);
  438. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  439. }
  440. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  441. struct device_attribute *mattr,
  442. char *data)
  443. {
  444. struct dimm_info *dimm = to_dimm(dev);
  445. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  446. }
  447. /* dimm/rank attribute files */
  448. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  449. dimmdev_label_show, dimmdev_label_store);
  450. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  451. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  452. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  453. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  454. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  455. /* attributes of the dimm<id>/rank<id> object */
  456. static struct attribute *dimm_attrs[] = {
  457. &dev_attr_dimm_label.attr,
  458. &dev_attr_dimm_location.attr,
  459. &dev_attr_size.attr,
  460. &dev_attr_dimm_mem_type.attr,
  461. &dev_attr_dimm_dev_type.attr,
  462. &dev_attr_dimm_edac_mode.attr,
  463. NULL,
  464. };
  465. static struct attribute_group dimm_attr_grp = {
  466. .attrs = dimm_attrs,
  467. };
  468. static const struct attribute_group *dimm_attr_groups[] = {
  469. &dimm_attr_grp,
  470. NULL
  471. };
  472. static void dimm_attr_release(struct device *dev)
  473. {
  474. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  475. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  476. kfree(dimm);
  477. }
  478. static struct device_type dimm_attr_type = {
  479. .groups = dimm_attr_groups,
  480. .release = dimm_attr_release,
  481. };
  482. /* Create a DIMM object under specifed memory controller device */
  483. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  484. struct dimm_info *dimm,
  485. int index)
  486. {
  487. int err;
  488. dimm->mci = mci;
  489. dimm->dev.type = &dimm_attr_type;
  490. dimm->dev.bus = mci->bus;
  491. device_initialize(&dimm->dev);
  492. dimm->dev.parent = &mci->dev;
  493. if (mci->csbased)
  494. dev_set_name(&dimm->dev, "rank%d", index);
  495. else
  496. dev_set_name(&dimm->dev, "dimm%d", index);
  497. dev_set_drvdata(&dimm->dev, dimm);
  498. pm_runtime_forbid(&mci->dev);
  499. err = device_add(&dimm->dev);
  500. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  501. return err;
  502. }
  503. /*
  504. * Memory controller device
  505. */
  506. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  507. static ssize_t mci_reset_counters_store(struct device *dev,
  508. struct device_attribute *mattr,
  509. const char *data, size_t count)
  510. {
  511. struct mem_ctl_info *mci = to_mci(dev);
  512. int cnt, row, chan, i;
  513. mci->ue_mc = 0;
  514. mci->ce_mc = 0;
  515. mci->ue_noinfo_count = 0;
  516. mci->ce_noinfo_count = 0;
  517. for (row = 0; row < mci->nr_csrows; row++) {
  518. struct csrow_info *ri = mci->csrows[row];
  519. ri->ue_count = 0;
  520. ri->ce_count = 0;
  521. for (chan = 0; chan < ri->nr_channels; chan++)
  522. ri->channels[chan]->ce_count = 0;
  523. }
  524. cnt = 1;
  525. for (i = 0; i < mci->n_layers; i++) {
  526. cnt *= mci->layers[i].size;
  527. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  528. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  529. }
  530. mci->start_time = jiffies;
  531. return count;
  532. }
  533. /* Memory scrubbing interface:
  534. *
  535. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  536. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  537. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  538. *
  539. * Negative value still means that an error has occurred while setting
  540. * the scrub rate.
  541. */
  542. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  543. struct device_attribute *mattr,
  544. const char *data, size_t count)
  545. {
  546. struct mem_ctl_info *mci = to_mci(dev);
  547. unsigned long bandwidth = 0;
  548. int new_bw = 0;
  549. if (kstrtoul(data, 10, &bandwidth) < 0)
  550. return -EINVAL;
  551. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  552. if (new_bw < 0) {
  553. edac_printk(KERN_WARNING, EDAC_MC,
  554. "Error setting scrub rate to: %lu\n", bandwidth);
  555. return -EINVAL;
  556. }
  557. return count;
  558. }
  559. /*
  560. * ->get_sdram_scrub_rate() return value semantics same as above.
  561. */
  562. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  563. struct device_attribute *mattr,
  564. char *data)
  565. {
  566. struct mem_ctl_info *mci = to_mci(dev);
  567. int bandwidth = 0;
  568. bandwidth = mci->get_sdram_scrub_rate(mci);
  569. if (bandwidth < 0) {
  570. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  571. return bandwidth;
  572. }
  573. return sprintf(data, "%d\n", bandwidth);
  574. }
  575. /* default attribute files for the MCI object */
  576. static ssize_t mci_ue_count_show(struct device *dev,
  577. struct device_attribute *mattr,
  578. char *data)
  579. {
  580. struct mem_ctl_info *mci = to_mci(dev);
  581. return sprintf(data, "%d\n", mci->ue_mc);
  582. }
  583. static ssize_t mci_ce_count_show(struct device *dev,
  584. struct device_attribute *mattr,
  585. char *data)
  586. {
  587. struct mem_ctl_info *mci = to_mci(dev);
  588. return sprintf(data, "%d\n", mci->ce_mc);
  589. }
  590. static ssize_t mci_ce_noinfo_show(struct device *dev,
  591. struct device_attribute *mattr,
  592. char *data)
  593. {
  594. struct mem_ctl_info *mci = to_mci(dev);
  595. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  596. }
  597. static ssize_t mci_ue_noinfo_show(struct device *dev,
  598. struct device_attribute *mattr,
  599. char *data)
  600. {
  601. struct mem_ctl_info *mci = to_mci(dev);
  602. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  603. }
  604. static ssize_t mci_seconds_show(struct device *dev,
  605. struct device_attribute *mattr,
  606. char *data)
  607. {
  608. struct mem_ctl_info *mci = to_mci(dev);
  609. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  610. }
  611. static ssize_t mci_ctl_name_show(struct device *dev,
  612. struct device_attribute *mattr,
  613. char *data)
  614. {
  615. struct mem_ctl_info *mci = to_mci(dev);
  616. return sprintf(data, "%s\n", mci->ctl_name);
  617. }
  618. static ssize_t mci_size_mb_show(struct device *dev,
  619. struct device_attribute *mattr,
  620. char *data)
  621. {
  622. struct mem_ctl_info *mci = to_mci(dev);
  623. int total_pages = 0, csrow_idx, j;
  624. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  625. struct csrow_info *csrow = mci->csrows[csrow_idx];
  626. for (j = 0; j < csrow->nr_channels; j++) {
  627. struct dimm_info *dimm = csrow->channels[j]->dimm;
  628. total_pages += dimm->nr_pages;
  629. }
  630. }
  631. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  632. }
  633. static ssize_t mci_max_location_show(struct device *dev,
  634. struct device_attribute *mattr,
  635. char *data)
  636. {
  637. struct mem_ctl_info *mci = to_mci(dev);
  638. int i;
  639. char *p = data;
  640. for (i = 0; i < mci->n_layers; i++) {
  641. p += sprintf(p, "%s %d ",
  642. edac_layer_name[mci->layers[i].type],
  643. mci->layers[i].size - 1);
  644. }
  645. return p - data;
  646. }
  647. #ifdef CONFIG_EDAC_DEBUG
  648. static ssize_t edac_fake_inject_write(struct file *file,
  649. const char __user *data,
  650. size_t count, loff_t *ppos)
  651. {
  652. struct device *dev = file->private_data;
  653. struct mem_ctl_info *mci = to_mci(dev);
  654. static enum hw_event_mc_err_type type;
  655. u16 errcount = mci->fake_inject_count;
  656. if (!errcount)
  657. errcount = 1;
  658. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  659. : HW_EVENT_ERR_CORRECTED;
  660. printk(KERN_DEBUG
  661. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  662. errcount,
  663. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  664. errcount > 1 ? "s" : "",
  665. mci->fake_inject_layer[0],
  666. mci->fake_inject_layer[1],
  667. mci->fake_inject_layer[2]
  668. );
  669. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  670. mci->fake_inject_layer[0],
  671. mci->fake_inject_layer[1],
  672. mci->fake_inject_layer[2],
  673. "FAKE ERROR", "for EDAC testing only");
  674. return count;
  675. }
  676. static const struct file_operations debug_fake_inject_fops = {
  677. .open = simple_open,
  678. .write = edac_fake_inject_write,
  679. .llseek = generic_file_llseek,
  680. };
  681. #endif
  682. /* default Control file */
  683. static DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  684. /* default Attribute files */
  685. static DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  686. static DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  687. static DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  688. static DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  689. static DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  690. static DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  691. static DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  692. static DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  693. /* memory scrubber attribute file */
  694. DEVICE_ATTR(sdram_scrub_rate, 0, mci_sdram_scrub_rate_show,
  695. mci_sdram_scrub_rate_store); /* umode set later in is_visible */
  696. static struct attribute *mci_attrs[] = {
  697. &dev_attr_reset_counters.attr,
  698. &dev_attr_mc_name.attr,
  699. &dev_attr_size_mb.attr,
  700. &dev_attr_seconds_since_reset.attr,
  701. &dev_attr_ue_noinfo_count.attr,
  702. &dev_attr_ce_noinfo_count.attr,
  703. &dev_attr_ue_count.attr,
  704. &dev_attr_ce_count.attr,
  705. &dev_attr_max_location.attr,
  706. &dev_attr_sdram_scrub_rate.attr,
  707. NULL
  708. };
  709. static umode_t mci_attr_is_visible(struct kobject *kobj,
  710. struct attribute *attr, int idx)
  711. {
  712. struct device *dev = kobj_to_dev(kobj);
  713. struct mem_ctl_info *mci = to_mci(dev);
  714. umode_t mode = 0;
  715. if (attr != &dev_attr_sdram_scrub_rate.attr)
  716. return attr->mode;
  717. if (mci->get_sdram_scrub_rate)
  718. mode |= S_IRUGO;
  719. if (mci->set_sdram_scrub_rate)
  720. mode |= S_IWUSR;
  721. return mode;
  722. }
  723. static struct attribute_group mci_attr_grp = {
  724. .attrs = mci_attrs,
  725. .is_visible = mci_attr_is_visible,
  726. };
  727. static const struct attribute_group *mci_attr_groups[] = {
  728. &mci_attr_grp,
  729. NULL
  730. };
  731. static void mci_attr_release(struct device *dev)
  732. {
  733. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  734. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  735. kfree(mci);
  736. }
  737. static struct device_type mci_attr_type = {
  738. .groups = mci_attr_groups,
  739. .release = mci_attr_release,
  740. };
  741. #ifdef CONFIG_EDAC_DEBUG
  742. static struct dentry *edac_debugfs;
  743. int __init edac_debugfs_init(void)
  744. {
  745. edac_debugfs = debugfs_create_dir("edac", NULL);
  746. if (IS_ERR(edac_debugfs)) {
  747. edac_debugfs = NULL;
  748. return -ENOMEM;
  749. }
  750. return 0;
  751. }
  752. void edac_debugfs_exit(void)
  753. {
  754. debugfs_remove(edac_debugfs);
  755. }
  756. static int edac_create_debug_nodes(struct mem_ctl_info *mci)
  757. {
  758. struct dentry *d, *parent;
  759. char name[80];
  760. int i;
  761. if (!edac_debugfs)
  762. return -ENODEV;
  763. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  764. if (!d)
  765. return -ENOMEM;
  766. parent = d;
  767. for (i = 0; i < mci->n_layers; i++) {
  768. sprintf(name, "fake_inject_%s",
  769. edac_layer_name[mci->layers[i].type]);
  770. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  771. &mci->fake_inject_layer[i]);
  772. if (!d)
  773. goto nomem;
  774. }
  775. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  776. &mci->fake_inject_ue);
  777. if (!d)
  778. goto nomem;
  779. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  780. &mci->fake_inject_count);
  781. if (!d)
  782. goto nomem;
  783. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  784. &mci->dev,
  785. &debug_fake_inject_fops);
  786. if (!d)
  787. goto nomem;
  788. mci->debugfs = parent;
  789. return 0;
  790. nomem:
  791. debugfs_remove(mci->debugfs);
  792. return -ENOMEM;
  793. }
  794. #endif
  795. /*
  796. * Create a new Memory Controller kobject instance,
  797. * mc<id> under the 'mc' directory
  798. *
  799. * Return:
  800. * 0 Success
  801. * !0 Failure
  802. */
  803. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci,
  804. const struct attribute_group **groups)
  805. {
  806. int i, err;
  807. /*
  808. * The memory controller needs its own bus, in order to avoid
  809. * namespace conflicts at /sys/bus/edac.
  810. */
  811. mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  812. if (!mci->bus->name)
  813. return -ENOMEM;
  814. edac_dbg(0, "creating bus %s\n", mci->bus->name);
  815. err = bus_register(mci->bus);
  816. if (err < 0)
  817. goto fail_free_name;
  818. /* get the /sys/devices/system/edac subsys reference */
  819. mci->dev.type = &mci_attr_type;
  820. device_initialize(&mci->dev);
  821. mci->dev.parent = mci_pdev;
  822. mci->dev.bus = mci->bus;
  823. mci->dev.groups = groups;
  824. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  825. dev_set_drvdata(&mci->dev, mci);
  826. pm_runtime_forbid(&mci->dev);
  827. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  828. err = device_add(&mci->dev);
  829. if (err < 0) {
  830. edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
  831. goto fail_unregister_bus;
  832. }
  833. /*
  834. * Create the dimm/rank devices
  835. */
  836. for (i = 0; i < mci->tot_dimms; i++) {
  837. struct dimm_info *dimm = mci->dimms[i];
  838. /* Only expose populated DIMMs */
  839. if (!dimm->nr_pages)
  840. continue;
  841. #ifdef CONFIG_EDAC_DEBUG
  842. edac_dbg(1, "creating dimm%d, located at ", i);
  843. if (edac_debug_level >= 1) {
  844. int lay;
  845. for (lay = 0; lay < mci->n_layers; lay++)
  846. printk(KERN_CONT "%s %d ",
  847. edac_layer_name[mci->layers[lay].type],
  848. dimm->location[lay]);
  849. printk(KERN_CONT "\n");
  850. }
  851. #endif
  852. err = edac_create_dimm_object(mci, dimm, i);
  853. if (err) {
  854. edac_dbg(1, "failure: create dimm %d obj\n", i);
  855. goto fail_unregister_dimm;
  856. }
  857. }
  858. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  859. err = edac_create_csrow_objects(mci);
  860. if (err < 0)
  861. goto fail_unregister_dimm;
  862. #endif
  863. #ifdef CONFIG_EDAC_DEBUG
  864. edac_create_debug_nodes(mci);
  865. #endif
  866. return 0;
  867. fail_unregister_dimm:
  868. for (i--; i >= 0; i--) {
  869. struct dimm_info *dimm = mci->dimms[i];
  870. if (!dimm->nr_pages)
  871. continue;
  872. device_unregister(&dimm->dev);
  873. }
  874. device_unregister(&mci->dev);
  875. fail_unregister_bus:
  876. bus_unregister(mci->bus);
  877. fail_free_name:
  878. kfree(mci->bus->name);
  879. return err;
  880. }
  881. /*
  882. * remove a Memory Controller instance
  883. */
  884. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  885. {
  886. int i;
  887. edac_dbg(0, "\n");
  888. #ifdef CONFIG_EDAC_DEBUG
  889. debugfs_remove(mci->debugfs);
  890. #endif
  891. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  892. edac_delete_csrow_objects(mci);
  893. #endif
  894. for (i = 0; i < mci->tot_dimms; i++) {
  895. struct dimm_info *dimm = mci->dimms[i];
  896. if (dimm->nr_pages == 0)
  897. continue;
  898. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  899. device_unregister(&dimm->dev);
  900. }
  901. }
  902. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  903. {
  904. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  905. device_unregister(&mci->dev);
  906. bus_unregister(mci->bus);
  907. kfree(mci->bus->name);
  908. }
  909. static void mc_attr_release(struct device *dev)
  910. {
  911. /*
  912. * There's no container structure here, as this is just the mci
  913. * parent device, used to create the /sys/devices/mc sysfs node.
  914. * So, there are no attributes on it.
  915. */
  916. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  917. kfree(dev);
  918. }
  919. static struct device_type mc_attr_type = {
  920. .release = mc_attr_release,
  921. };
  922. /*
  923. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  924. */
  925. int __init edac_mc_sysfs_init(void)
  926. {
  927. struct bus_type *edac_subsys;
  928. int err;
  929. /* get the /sys/devices/system/edac subsys reference */
  930. edac_subsys = edac_get_sysfs_subsys();
  931. if (edac_subsys == NULL) {
  932. edac_dbg(1, "no edac_subsys\n");
  933. err = -EINVAL;
  934. goto out;
  935. }
  936. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  937. if (!mci_pdev) {
  938. err = -ENOMEM;
  939. goto out_put_sysfs;
  940. }
  941. mci_pdev->bus = edac_subsys;
  942. mci_pdev->type = &mc_attr_type;
  943. device_initialize(mci_pdev);
  944. dev_set_name(mci_pdev, "mc");
  945. err = device_add(mci_pdev);
  946. if (err < 0)
  947. goto out_dev_free;
  948. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  949. return 0;
  950. out_dev_free:
  951. kfree(mci_pdev);
  952. out_put_sysfs:
  953. edac_put_sysfs_subsys();
  954. out:
  955. return err;
  956. }
  957. void edac_mc_sysfs_exit(void)
  958. {
  959. device_unregister(mci_pdev);
  960. edac_put_sysfs_subsys();
  961. }