dmaengine.c 30 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called COPYING.
  16. */
  17. /*
  18. * This code implements the DMA subsystem. It provides a HW-neutral interface
  19. * for other kernel code to use asynchronous memory copy capabilities,
  20. * if present, and allows different HW DMA drivers to register as providing
  21. * this capability.
  22. *
  23. * Due to the fact we are accelerating what is already a relatively fast
  24. * operation, the code goes to great lengths to avoid additional overhead,
  25. * such as locking.
  26. *
  27. * LOCKING:
  28. *
  29. * The subsystem keeps a global list of dma_device structs it is protected by a
  30. * mutex, dma_list_mutex.
  31. *
  32. * A subsystem can get access to a channel by calling dmaengine_get() followed
  33. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  34. * dma_request_channel(). Once a channel is allocated a reference is taken
  35. * against its corresponding driver to disable removal.
  36. *
  37. * Each device has a channels list, which runs unlocked but is never modified
  38. * once the device is registered, it's just setup by the driver.
  39. *
  40. * See Documentation/dmaengine.txt for more details
  41. */
  42. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43. #include <linux/dma-mapping.h>
  44. #include <linux/init.h>
  45. #include <linux/module.h>
  46. #include <linux/mm.h>
  47. #include <linux/device.h>
  48. #include <linux/dmaengine.h>
  49. #include <linux/hardirq.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/percpu.h>
  52. #include <linux/rcupdate.h>
  53. #include <linux/mutex.h>
  54. #include <linux/jiffies.h>
  55. #include <linux/rculist.h>
  56. #include <linux/idr.h>
  57. #include <linux/slab.h>
  58. #include <linux/acpi.h>
  59. #include <linux/acpi_dma.h>
  60. #include <linux/of_dma.h>
  61. #include <linux/mempool.h>
  62. static DEFINE_MUTEX(dma_list_mutex);
  63. static DEFINE_IDR(dma_idr);
  64. static LIST_HEAD(dma_device_list);
  65. static long dmaengine_ref_count;
  66. /* --- sysfs implementation --- */
  67. /**
  68. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  69. * @dev - device node
  70. *
  71. * Must be called under dma_list_mutex
  72. */
  73. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  74. {
  75. struct dma_chan_dev *chan_dev;
  76. chan_dev = container_of(dev, typeof(*chan_dev), device);
  77. return chan_dev->chan;
  78. }
  79. static ssize_t memcpy_count_show(struct device *dev,
  80. struct device_attribute *attr, char *buf)
  81. {
  82. struct dma_chan *chan;
  83. unsigned long count = 0;
  84. int i;
  85. int err;
  86. mutex_lock(&dma_list_mutex);
  87. chan = dev_to_dma_chan(dev);
  88. if (chan) {
  89. for_each_possible_cpu(i)
  90. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  91. err = sprintf(buf, "%lu\n", count);
  92. } else
  93. err = -ENODEV;
  94. mutex_unlock(&dma_list_mutex);
  95. return err;
  96. }
  97. static DEVICE_ATTR_RO(memcpy_count);
  98. static ssize_t bytes_transferred_show(struct device *dev,
  99. struct device_attribute *attr, char *buf)
  100. {
  101. struct dma_chan *chan;
  102. unsigned long count = 0;
  103. int i;
  104. int err;
  105. mutex_lock(&dma_list_mutex);
  106. chan = dev_to_dma_chan(dev);
  107. if (chan) {
  108. for_each_possible_cpu(i)
  109. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  110. err = sprintf(buf, "%lu\n", count);
  111. } else
  112. err = -ENODEV;
  113. mutex_unlock(&dma_list_mutex);
  114. return err;
  115. }
  116. static DEVICE_ATTR_RO(bytes_transferred);
  117. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  118. char *buf)
  119. {
  120. struct dma_chan *chan;
  121. int err;
  122. mutex_lock(&dma_list_mutex);
  123. chan = dev_to_dma_chan(dev);
  124. if (chan)
  125. err = sprintf(buf, "%d\n", chan->client_count);
  126. else
  127. err = -ENODEV;
  128. mutex_unlock(&dma_list_mutex);
  129. return err;
  130. }
  131. static DEVICE_ATTR_RO(in_use);
  132. static struct attribute *dma_dev_attrs[] = {
  133. &dev_attr_memcpy_count.attr,
  134. &dev_attr_bytes_transferred.attr,
  135. &dev_attr_in_use.attr,
  136. NULL,
  137. };
  138. ATTRIBUTE_GROUPS(dma_dev);
  139. static void chan_dev_release(struct device *dev)
  140. {
  141. struct dma_chan_dev *chan_dev;
  142. chan_dev = container_of(dev, typeof(*chan_dev), device);
  143. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  144. mutex_lock(&dma_list_mutex);
  145. idr_remove(&dma_idr, chan_dev->dev_id);
  146. mutex_unlock(&dma_list_mutex);
  147. kfree(chan_dev->idr_ref);
  148. }
  149. kfree(chan_dev);
  150. }
  151. static struct class dma_devclass = {
  152. .name = "dma",
  153. .dev_groups = dma_dev_groups,
  154. .dev_release = chan_dev_release,
  155. };
  156. /* --- client and device registration --- */
  157. #define dma_device_satisfies_mask(device, mask) \
  158. __dma_device_satisfies_mask((device), &(mask))
  159. static int
  160. __dma_device_satisfies_mask(struct dma_device *device,
  161. const dma_cap_mask_t *want)
  162. {
  163. dma_cap_mask_t has;
  164. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  165. DMA_TX_TYPE_END);
  166. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  167. }
  168. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  169. {
  170. return chan->device->dev->driver->owner;
  171. }
  172. /**
  173. * balance_ref_count - catch up the channel reference count
  174. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  175. *
  176. * balance_ref_count must be called under dma_list_mutex
  177. */
  178. static void balance_ref_count(struct dma_chan *chan)
  179. {
  180. struct module *owner = dma_chan_to_owner(chan);
  181. while (chan->client_count < dmaengine_ref_count) {
  182. __module_get(owner);
  183. chan->client_count++;
  184. }
  185. }
  186. /**
  187. * dma_chan_get - try to grab a dma channel's parent driver module
  188. * @chan - channel to grab
  189. *
  190. * Must be called under dma_list_mutex
  191. */
  192. static int dma_chan_get(struct dma_chan *chan)
  193. {
  194. struct module *owner = dma_chan_to_owner(chan);
  195. int ret;
  196. /* The channel is already in use, update client count */
  197. if (chan->client_count) {
  198. __module_get(owner);
  199. goto out;
  200. }
  201. if (!try_module_get(owner))
  202. return -ENODEV;
  203. /* allocate upon first client reference */
  204. if (chan->device->device_alloc_chan_resources) {
  205. ret = chan->device->device_alloc_chan_resources(chan);
  206. if (ret < 0)
  207. goto err_out;
  208. }
  209. if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  210. balance_ref_count(chan);
  211. out:
  212. chan->client_count++;
  213. return 0;
  214. err_out:
  215. module_put(owner);
  216. return ret;
  217. }
  218. /**
  219. * dma_chan_put - drop a reference to a dma channel's parent driver module
  220. * @chan - channel to release
  221. *
  222. * Must be called under dma_list_mutex
  223. */
  224. static void dma_chan_put(struct dma_chan *chan)
  225. {
  226. /* This channel is not in use, bail out */
  227. if (!chan->client_count)
  228. return;
  229. chan->client_count--;
  230. module_put(dma_chan_to_owner(chan));
  231. /* This channel is not in use anymore, free it */
  232. if (!chan->client_count && chan->device->device_free_chan_resources)
  233. chan->device->device_free_chan_resources(chan);
  234. }
  235. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  236. {
  237. enum dma_status status;
  238. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  239. dma_async_issue_pending(chan);
  240. do {
  241. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  242. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  243. pr_err("%s: timeout!\n", __func__);
  244. return DMA_ERROR;
  245. }
  246. if (status != DMA_IN_PROGRESS)
  247. break;
  248. cpu_relax();
  249. } while (1);
  250. return status;
  251. }
  252. EXPORT_SYMBOL(dma_sync_wait);
  253. /**
  254. * dma_cap_mask_all - enable iteration over all operation types
  255. */
  256. static dma_cap_mask_t dma_cap_mask_all;
  257. /**
  258. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  259. * @chan - associated channel for this entry
  260. */
  261. struct dma_chan_tbl_ent {
  262. struct dma_chan *chan;
  263. };
  264. /**
  265. * channel_table - percpu lookup table for memory-to-memory offload providers
  266. */
  267. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  268. static int __init dma_channel_table_init(void)
  269. {
  270. enum dma_transaction_type cap;
  271. int err = 0;
  272. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  273. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  274. * but are not associated with an operation so they do not need
  275. * an entry in the channel_table
  276. */
  277. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  278. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  279. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  280. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  281. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  282. if (!channel_table[cap]) {
  283. err = -ENOMEM;
  284. break;
  285. }
  286. }
  287. if (err) {
  288. pr_err("initialization failure\n");
  289. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  290. free_percpu(channel_table[cap]);
  291. }
  292. return err;
  293. }
  294. arch_initcall(dma_channel_table_init);
  295. /**
  296. * dma_find_channel - find a channel to carry out the operation
  297. * @tx_type: transaction type
  298. */
  299. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  300. {
  301. return this_cpu_read(channel_table[tx_type]->chan);
  302. }
  303. EXPORT_SYMBOL(dma_find_channel);
  304. /**
  305. * dma_issue_pending_all - flush all pending operations across all channels
  306. */
  307. void dma_issue_pending_all(void)
  308. {
  309. struct dma_device *device;
  310. struct dma_chan *chan;
  311. rcu_read_lock();
  312. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  313. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  314. continue;
  315. list_for_each_entry(chan, &device->channels, device_node)
  316. if (chan->client_count)
  317. device->device_issue_pending(chan);
  318. }
  319. rcu_read_unlock();
  320. }
  321. EXPORT_SYMBOL(dma_issue_pending_all);
  322. /**
  323. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  324. */
  325. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  326. {
  327. int node = dev_to_node(chan->device->dev);
  328. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  329. }
  330. /**
  331. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  332. * @cap: capability to match
  333. * @cpu: cpu index which the channel should be close to
  334. *
  335. * If some channels are close to the given cpu, the one with the lowest
  336. * reference count is returned. Otherwise, cpu is ignored and only the
  337. * reference count is taken into account.
  338. * Must be called under dma_list_mutex.
  339. */
  340. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  341. {
  342. struct dma_device *device;
  343. struct dma_chan *chan;
  344. struct dma_chan *min = NULL;
  345. struct dma_chan *localmin = NULL;
  346. list_for_each_entry(device, &dma_device_list, global_node) {
  347. if (!dma_has_cap(cap, device->cap_mask) ||
  348. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  349. continue;
  350. list_for_each_entry(chan, &device->channels, device_node) {
  351. if (!chan->client_count)
  352. continue;
  353. if (!min || chan->table_count < min->table_count)
  354. min = chan;
  355. if (dma_chan_is_local(chan, cpu))
  356. if (!localmin ||
  357. chan->table_count < localmin->table_count)
  358. localmin = chan;
  359. }
  360. }
  361. chan = localmin ? localmin : min;
  362. if (chan)
  363. chan->table_count++;
  364. return chan;
  365. }
  366. /**
  367. * dma_channel_rebalance - redistribute the available channels
  368. *
  369. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  370. * operation type) in the SMP case, and operation isolation (avoid
  371. * multi-tasking channels) in the non-SMP case. Must be called under
  372. * dma_list_mutex.
  373. */
  374. static void dma_channel_rebalance(void)
  375. {
  376. struct dma_chan *chan;
  377. struct dma_device *device;
  378. int cpu;
  379. int cap;
  380. /* undo the last distribution */
  381. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  382. for_each_possible_cpu(cpu)
  383. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  384. list_for_each_entry(device, &dma_device_list, global_node) {
  385. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  386. continue;
  387. list_for_each_entry(chan, &device->channels, device_node)
  388. chan->table_count = 0;
  389. }
  390. /* don't populate the channel_table if no clients are available */
  391. if (!dmaengine_ref_count)
  392. return;
  393. /* redistribute available channels */
  394. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  395. for_each_online_cpu(cpu) {
  396. chan = min_chan(cap, cpu);
  397. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  398. }
  399. }
  400. int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
  401. {
  402. struct dma_device *device;
  403. if (!chan || !caps)
  404. return -EINVAL;
  405. device = chan->device;
  406. /* check if the channel supports slave transactions */
  407. if (!test_bit(DMA_SLAVE, device->cap_mask.bits))
  408. return -ENXIO;
  409. /*
  410. * Check whether it reports it uses the generic slave
  411. * capabilities, if not, that means it doesn't support any
  412. * kind of slave capabilities reporting.
  413. */
  414. if (!device->directions)
  415. return -ENXIO;
  416. caps->src_addr_widths = device->src_addr_widths;
  417. caps->dst_addr_widths = device->dst_addr_widths;
  418. caps->directions = device->directions;
  419. caps->residue_granularity = device->residue_granularity;
  420. /*
  421. * Some devices implement only pause (e.g. to get residuum) but no
  422. * resume. However cmd_pause is advertised as pause AND resume.
  423. */
  424. caps->cmd_pause = !!(device->device_pause && device->device_resume);
  425. caps->cmd_terminate = !!device->device_terminate_all;
  426. return 0;
  427. }
  428. EXPORT_SYMBOL_GPL(dma_get_slave_caps);
  429. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  430. struct dma_device *dev,
  431. dma_filter_fn fn, void *fn_param)
  432. {
  433. struct dma_chan *chan;
  434. if (!__dma_device_satisfies_mask(dev, mask)) {
  435. pr_debug("%s: wrong capabilities\n", __func__);
  436. return NULL;
  437. }
  438. /* devices with multiple channels need special handling as we need to
  439. * ensure that all channels are either private or public.
  440. */
  441. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  442. list_for_each_entry(chan, &dev->channels, device_node) {
  443. /* some channels are already publicly allocated */
  444. if (chan->client_count)
  445. return NULL;
  446. }
  447. list_for_each_entry(chan, &dev->channels, device_node) {
  448. if (chan->client_count) {
  449. pr_debug("%s: %s busy\n",
  450. __func__, dma_chan_name(chan));
  451. continue;
  452. }
  453. if (fn && !fn(chan, fn_param)) {
  454. pr_debug("%s: %s filter said false\n",
  455. __func__, dma_chan_name(chan));
  456. continue;
  457. }
  458. return chan;
  459. }
  460. return NULL;
  461. }
  462. /**
  463. * dma_request_slave_channel - try to get specific channel exclusively
  464. * @chan: target channel
  465. */
  466. struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  467. {
  468. int err = -EBUSY;
  469. /* lock against __dma_request_channel */
  470. mutex_lock(&dma_list_mutex);
  471. if (chan->client_count == 0) {
  472. err = dma_chan_get(chan);
  473. if (err)
  474. pr_debug("%s: failed to get %s: (%d)\n",
  475. __func__, dma_chan_name(chan), err);
  476. } else
  477. chan = NULL;
  478. mutex_unlock(&dma_list_mutex);
  479. return chan;
  480. }
  481. EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  482. struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
  483. {
  484. dma_cap_mask_t mask;
  485. struct dma_chan *chan;
  486. int err;
  487. dma_cap_zero(mask);
  488. dma_cap_set(DMA_SLAVE, mask);
  489. /* lock against __dma_request_channel */
  490. mutex_lock(&dma_list_mutex);
  491. chan = private_candidate(&mask, device, NULL, NULL);
  492. if (chan) {
  493. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  494. device->privatecnt++;
  495. err = dma_chan_get(chan);
  496. if (err) {
  497. pr_debug("%s: failed to get %s: (%d)\n",
  498. __func__, dma_chan_name(chan), err);
  499. chan = NULL;
  500. if (--device->privatecnt == 0)
  501. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  502. }
  503. }
  504. mutex_unlock(&dma_list_mutex);
  505. return chan;
  506. }
  507. EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
  508. /**
  509. * __dma_request_channel - try to allocate an exclusive channel
  510. * @mask: capabilities that the channel must satisfy
  511. * @fn: optional callback to disposition available channels
  512. * @fn_param: opaque parameter to pass to dma_filter_fn
  513. *
  514. * Returns pointer to appropriate DMA channel on success or NULL.
  515. */
  516. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  517. dma_filter_fn fn, void *fn_param)
  518. {
  519. struct dma_device *device, *_d;
  520. struct dma_chan *chan = NULL;
  521. int err;
  522. /* Find a channel */
  523. mutex_lock(&dma_list_mutex);
  524. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  525. chan = private_candidate(mask, device, fn, fn_param);
  526. if (chan) {
  527. /* Found a suitable channel, try to grab, prep, and
  528. * return it. We first set DMA_PRIVATE to disable
  529. * balance_ref_count as this channel will not be
  530. * published in the general-purpose allocator
  531. */
  532. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  533. device->privatecnt++;
  534. err = dma_chan_get(chan);
  535. if (err == -ENODEV) {
  536. pr_debug("%s: %s module removed\n",
  537. __func__, dma_chan_name(chan));
  538. list_del_rcu(&device->global_node);
  539. } else if (err)
  540. pr_debug("%s: failed to get %s: (%d)\n",
  541. __func__, dma_chan_name(chan), err);
  542. else
  543. break;
  544. if (--device->privatecnt == 0)
  545. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  546. chan = NULL;
  547. }
  548. }
  549. mutex_unlock(&dma_list_mutex);
  550. pr_debug("%s: %s (%s)\n",
  551. __func__,
  552. chan ? "success" : "fail",
  553. chan ? dma_chan_name(chan) : NULL);
  554. return chan;
  555. }
  556. EXPORT_SYMBOL_GPL(__dma_request_channel);
  557. /**
  558. * dma_request_slave_channel - try to allocate an exclusive slave channel
  559. * @dev: pointer to client device structure
  560. * @name: slave channel name
  561. *
  562. * Returns pointer to appropriate DMA channel on success or an error pointer.
  563. */
  564. struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
  565. const char *name)
  566. {
  567. /* If device-tree is present get slave info from here */
  568. if (dev->of_node)
  569. return of_dma_request_slave_channel(dev->of_node, name);
  570. /* If device was enumerated by ACPI get slave info from here */
  571. if (ACPI_HANDLE(dev))
  572. return acpi_dma_request_slave_chan_by_name(dev, name);
  573. return ERR_PTR(-ENODEV);
  574. }
  575. EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
  576. /**
  577. * dma_request_slave_channel - try to allocate an exclusive slave channel
  578. * @dev: pointer to client device structure
  579. * @name: slave channel name
  580. *
  581. * Returns pointer to appropriate DMA channel on success or NULL.
  582. */
  583. struct dma_chan *dma_request_slave_channel(struct device *dev,
  584. const char *name)
  585. {
  586. struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
  587. if (IS_ERR(ch))
  588. return NULL;
  589. return ch;
  590. }
  591. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  592. void dma_release_channel(struct dma_chan *chan)
  593. {
  594. mutex_lock(&dma_list_mutex);
  595. WARN_ONCE(chan->client_count != 1,
  596. "chan reference count %d != 1\n", chan->client_count);
  597. dma_chan_put(chan);
  598. /* drop PRIVATE cap enabled by __dma_request_channel() */
  599. if (--chan->device->privatecnt == 0)
  600. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  601. mutex_unlock(&dma_list_mutex);
  602. }
  603. EXPORT_SYMBOL_GPL(dma_release_channel);
  604. /**
  605. * dmaengine_get - register interest in dma_channels
  606. */
  607. void dmaengine_get(void)
  608. {
  609. struct dma_device *device, *_d;
  610. struct dma_chan *chan;
  611. int err;
  612. mutex_lock(&dma_list_mutex);
  613. dmaengine_ref_count++;
  614. /* try to grab channels */
  615. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  616. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  617. continue;
  618. list_for_each_entry(chan, &device->channels, device_node) {
  619. err = dma_chan_get(chan);
  620. if (err == -ENODEV) {
  621. /* module removed before we could use it */
  622. list_del_rcu(&device->global_node);
  623. break;
  624. } else if (err)
  625. pr_debug("%s: failed to get %s: (%d)\n",
  626. __func__, dma_chan_name(chan), err);
  627. }
  628. }
  629. /* if this is the first reference and there were channels
  630. * waiting we need to rebalance to get those channels
  631. * incorporated into the channel table
  632. */
  633. if (dmaengine_ref_count == 1)
  634. dma_channel_rebalance();
  635. mutex_unlock(&dma_list_mutex);
  636. }
  637. EXPORT_SYMBOL(dmaengine_get);
  638. /**
  639. * dmaengine_put - let dma drivers be removed when ref_count == 0
  640. */
  641. void dmaengine_put(void)
  642. {
  643. struct dma_device *device;
  644. struct dma_chan *chan;
  645. mutex_lock(&dma_list_mutex);
  646. dmaengine_ref_count--;
  647. BUG_ON(dmaengine_ref_count < 0);
  648. /* drop channel references */
  649. list_for_each_entry(device, &dma_device_list, global_node) {
  650. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  651. continue;
  652. list_for_each_entry(chan, &device->channels, device_node)
  653. dma_chan_put(chan);
  654. }
  655. mutex_unlock(&dma_list_mutex);
  656. }
  657. EXPORT_SYMBOL(dmaengine_put);
  658. static bool device_has_all_tx_types(struct dma_device *device)
  659. {
  660. /* A device that satisfies this test has channels that will never cause
  661. * an async_tx channel switch event as all possible operation types can
  662. * be handled.
  663. */
  664. #ifdef CONFIG_ASYNC_TX_DMA
  665. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  666. return false;
  667. #endif
  668. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  669. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  670. return false;
  671. #endif
  672. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  673. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  674. return false;
  675. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  676. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  677. return false;
  678. #endif
  679. #endif
  680. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  681. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  682. return false;
  683. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  684. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  685. return false;
  686. #endif
  687. #endif
  688. return true;
  689. }
  690. static int get_dma_id(struct dma_device *device)
  691. {
  692. int rc;
  693. mutex_lock(&dma_list_mutex);
  694. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  695. if (rc >= 0)
  696. device->dev_id = rc;
  697. mutex_unlock(&dma_list_mutex);
  698. return rc < 0 ? rc : 0;
  699. }
  700. /**
  701. * dma_async_device_register - registers DMA devices found
  702. * @device: &dma_device
  703. */
  704. int dma_async_device_register(struct dma_device *device)
  705. {
  706. int chancnt = 0, rc;
  707. struct dma_chan* chan;
  708. atomic_t *idr_ref;
  709. if (!device)
  710. return -ENODEV;
  711. /* validate device routines */
  712. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  713. !device->device_prep_dma_memcpy);
  714. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  715. !device->device_prep_dma_xor);
  716. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  717. !device->device_prep_dma_xor_val);
  718. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  719. !device->device_prep_dma_pq);
  720. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  721. !device->device_prep_dma_pq_val);
  722. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  723. !device->device_prep_dma_interrupt);
  724. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  725. !device->device_prep_dma_sg);
  726. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  727. !device->device_prep_dma_cyclic);
  728. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  729. !device->device_prep_interleaved_dma);
  730. BUG_ON(!device->device_tx_status);
  731. BUG_ON(!device->device_issue_pending);
  732. BUG_ON(!device->dev);
  733. /* note: this only matters in the
  734. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  735. */
  736. if (device_has_all_tx_types(device))
  737. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  738. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  739. if (!idr_ref)
  740. return -ENOMEM;
  741. rc = get_dma_id(device);
  742. if (rc != 0) {
  743. kfree(idr_ref);
  744. return rc;
  745. }
  746. atomic_set(idr_ref, 0);
  747. /* represent channels in sysfs. Probably want devs too */
  748. list_for_each_entry(chan, &device->channels, device_node) {
  749. rc = -ENOMEM;
  750. chan->local = alloc_percpu(typeof(*chan->local));
  751. if (chan->local == NULL)
  752. goto err_out;
  753. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  754. if (chan->dev == NULL) {
  755. free_percpu(chan->local);
  756. chan->local = NULL;
  757. goto err_out;
  758. }
  759. chan->chan_id = chancnt++;
  760. chan->dev->device.class = &dma_devclass;
  761. chan->dev->device.parent = device->dev;
  762. chan->dev->chan = chan;
  763. chan->dev->idr_ref = idr_ref;
  764. chan->dev->dev_id = device->dev_id;
  765. atomic_inc(idr_ref);
  766. dev_set_name(&chan->dev->device, "dma%dchan%d",
  767. device->dev_id, chan->chan_id);
  768. rc = device_register(&chan->dev->device);
  769. if (rc) {
  770. free_percpu(chan->local);
  771. chan->local = NULL;
  772. kfree(chan->dev);
  773. atomic_dec(idr_ref);
  774. goto err_out;
  775. }
  776. chan->client_count = 0;
  777. }
  778. device->chancnt = chancnt;
  779. mutex_lock(&dma_list_mutex);
  780. /* take references on public channels */
  781. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  782. list_for_each_entry(chan, &device->channels, device_node) {
  783. /* if clients are already waiting for channels we need
  784. * to take references on their behalf
  785. */
  786. if (dma_chan_get(chan) == -ENODEV) {
  787. /* note we can only get here for the first
  788. * channel as the remaining channels are
  789. * guaranteed to get a reference
  790. */
  791. rc = -ENODEV;
  792. mutex_unlock(&dma_list_mutex);
  793. goto err_out;
  794. }
  795. }
  796. list_add_tail_rcu(&device->global_node, &dma_device_list);
  797. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  798. device->privatecnt++; /* Always private */
  799. dma_channel_rebalance();
  800. mutex_unlock(&dma_list_mutex);
  801. return 0;
  802. err_out:
  803. /* if we never registered a channel just release the idr */
  804. if (atomic_read(idr_ref) == 0) {
  805. mutex_lock(&dma_list_mutex);
  806. idr_remove(&dma_idr, device->dev_id);
  807. mutex_unlock(&dma_list_mutex);
  808. kfree(idr_ref);
  809. return rc;
  810. }
  811. list_for_each_entry(chan, &device->channels, device_node) {
  812. if (chan->local == NULL)
  813. continue;
  814. mutex_lock(&dma_list_mutex);
  815. chan->dev->chan = NULL;
  816. mutex_unlock(&dma_list_mutex);
  817. device_unregister(&chan->dev->device);
  818. free_percpu(chan->local);
  819. }
  820. return rc;
  821. }
  822. EXPORT_SYMBOL(dma_async_device_register);
  823. /**
  824. * dma_async_device_unregister - unregister a DMA device
  825. * @device: &dma_device
  826. *
  827. * This routine is called by dma driver exit routines, dmaengine holds module
  828. * references to prevent it being called while channels are in use.
  829. */
  830. void dma_async_device_unregister(struct dma_device *device)
  831. {
  832. struct dma_chan *chan;
  833. mutex_lock(&dma_list_mutex);
  834. list_del_rcu(&device->global_node);
  835. dma_channel_rebalance();
  836. mutex_unlock(&dma_list_mutex);
  837. list_for_each_entry(chan, &device->channels, device_node) {
  838. WARN_ONCE(chan->client_count,
  839. "%s called while %d clients hold a reference\n",
  840. __func__, chan->client_count);
  841. mutex_lock(&dma_list_mutex);
  842. chan->dev->chan = NULL;
  843. mutex_unlock(&dma_list_mutex);
  844. device_unregister(&chan->dev->device);
  845. free_percpu(chan->local);
  846. }
  847. }
  848. EXPORT_SYMBOL(dma_async_device_unregister);
  849. struct dmaengine_unmap_pool {
  850. struct kmem_cache *cache;
  851. const char *name;
  852. mempool_t *pool;
  853. size_t size;
  854. };
  855. #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
  856. static struct dmaengine_unmap_pool unmap_pool[] = {
  857. __UNMAP_POOL(2),
  858. #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
  859. __UNMAP_POOL(16),
  860. __UNMAP_POOL(128),
  861. __UNMAP_POOL(256),
  862. #endif
  863. };
  864. static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
  865. {
  866. int order = get_count_order(nr);
  867. switch (order) {
  868. case 0 ... 1:
  869. return &unmap_pool[0];
  870. case 2 ... 4:
  871. return &unmap_pool[1];
  872. case 5 ... 7:
  873. return &unmap_pool[2];
  874. case 8:
  875. return &unmap_pool[3];
  876. default:
  877. BUG();
  878. return NULL;
  879. }
  880. }
  881. static void dmaengine_unmap(struct kref *kref)
  882. {
  883. struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
  884. struct device *dev = unmap->dev;
  885. int cnt, i;
  886. cnt = unmap->to_cnt;
  887. for (i = 0; i < cnt; i++)
  888. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  889. DMA_TO_DEVICE);
  890. cnt += unmap->from_cnt;
  891. for (; i < cnt; i++)
  892. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  893. DMA_FROM_DEVICE);
  894. cnt += unmap->bidi_cnt;
  895. for (; i < cnt; i++) {
  896. if (unmap->addr[i] == 0)
  897. continue;
  898. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  899. DMA_BIDIRECTIONAL);
  900. }
  901. cnt = unmap->map_cnt;
  902. mempool_free(unmap, __get_unmap_pool(cnt)->pool);
  903. }
  904. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
  905. {
  906. if (unmap)
  907. kref_put(&unmap->kref, dmaengine_unmap);
  908. }
  909. EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
  910. static void dmaengine_destroy_unmap_pool(void)
  911. {
  912. int i;
  913. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  914. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  915. if (p->pool)
  916. mempool_destroy(p->pool);
  917. p->pool = NULL;
  918. if (p->cache)
  919. kmem_cache_destroy(p->cache);
  920. p->cache = NULL;
  921. }
  922. }
  923. static int __init dmaengine_init_unmap_pool(void)
  924. {
  925. int i;
  926. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  927. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  928. size_t size;
  929. size = sizeof(struct dmaengine_unmap_data) +
  930. sizeof(dma_addr_t) * p->size;
  931. p->cache = kmem_cache_create(p->name, size, 0,
  932. SLAB_HWCACHE_ALIGN, NULL);
  933. if (!p->cache)
  934. break;
  935. p->pool = mempool_create_slab_pool(1, p->cache);
  936. if (!p->pool)
  937. break;
  938. }
  939. if (i == ARRAY_SIZE(unmap_pool))
  940. return 0;
  941. dmaengine_destroy_unmap_pool();
  942. return -ENOMEM;
  943. }
  944. struct dmaengine_unmap_data *
  945. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
  946. {
  947. struct dmaengine_unmap_data *unmap;
  948. unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
  949. if (!unmap)
  950. return NULL;
  951. memset(unmap, 0, sizeof(*unmap));
  952. kref_init(&unmap->kref);
  953. unmap->dev = dev;
  954. unmap->map_cnt = nr;
  955. return unmap;
  956. }
  957. EXPORT_SYMBOL(dmaengine_get_unmap_data);
  958. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  959. struct dma_chan *chan)
  960. {
  961. tx->chan = chan;
  962. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  963. spin_lock_init(&tx->lock);
  964. #endif
  965. }
  966. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  967. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  968. * @tx: in-flight transaction to wait on
  969. */
  970. enum dma_status
  971. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  972. {
  973. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  974. if (!tx)
  975. return DMA_COMPLETE;
  976. while (tx->cookie == -EBUSY) {
  977. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  978. pr_err("%s timeout waiting for descriptor submission\n",
  979. __func__);
  980. return DMA_ERROR;
  981. }
  982. cpu_relax();
  983. }
  984. return dma_sync_wait(tx->chan, tx->cookie);
  985. }
  986. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  987. /* dma_run_dependencies - helper routine for dma drivers to process
  988. * (start) dependent operations on their target channel
  989. * @tx: transaction with dependencies
  990. */
  991. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  992. {
  993. struct dma_async_tx_descriptor *dep = txd_next(tx);
  994. struct dma_async_tx_descriptor *dep_next;
  995. struct dma_chan *chan;
  996. if (!dep)
  997. return;
  998. /* we'll submit tx->next now, so clear the link */
  999. txd_clear_next(tx);
  1000. chan = dep->chan;
  1001. /* keep submitting up until a channel switch is detected
  1002. * in that case we will be called again as a result of
  1003. * processing the interrupt from async_tx_channel_switch
  1004. */
  1005. for (; dep; dep = dep_next) {
  1006. txd_lock(dep);
  1007. txd_clear_parent(dep);
  1008. dep_next = txd_next(dep);
  1009. if (dep_next && dep_next->chan == chan)
  1010. txd_clear_next(dep); /* ->next will be submitted */
  1011. else
  1012. dep_next = NULL; /* submit current dep and terminate */
  1013. txd_unlock(dep);
  1014. dep->tx_submit(dep);
  1015. }
  1016. chan->device->device_issue_pending(chan);
  1017. }
  1018. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  1019. static int __init dma_bus_init(void)
  1020. {
  1021. int err = dmaengine_init_unmap_pool();
  1022. if (err)
  1023. return err;
  1024. return class_register(&dma_devclass);
  1025. }
  1026. arch_initcall(dma_bus_init);