mips-gic-timer.c 4.2 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/clockchips.h>
  10. #include <linux/cpu.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/irqchip/mips-gic.h>
  14. #include <linux/notifier.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/percpu.h>
  17. #include <linux/smp.h>
  18. #include <linux/time.h>
  19. static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
  20. static int gic_timer_irq;
  21. static unsigned int gic_frequency;
  22. static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
  23. {
  24. u64 cnt;
  25. int res;
  26. cnt = gic_read_count();
  27. cnt += (u64)delta;
  28. gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
  29. res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
  30. return res;
  31. }
  32. static void gic_set_clock_mode(enum clock_event_mode mode,
  33. struct clock_event_device *evt)
  34. {
  35. /* Nothing to do ... */
  36. }
  37. static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
  38. {
  39. struct clock_event_device *cd = dev_id;
  40. gic_write_compare(gic_read_compare());
  41. cd->event_handler(cd);
  42. return IRQ_HANDLED;
  43. }
  44. struct irqaction gic_compare_irqaction = {
  45. .handler = gic_compare_interrupt,
  46. .percpu_dev_id = &gic_clockevent_device,
  47. .flags = IRQF_PERCPU | IRQF_TIMER,
  48. .name = "timer",
  49. };
  50. static void gic_clockevent_cpu_init(struct clock_event_device *cd)
  51. {
  52. unsigned int cpu = smp_processor_id();
  53. cd->name = "MIPS GIC";
  54. cd->features = CLOCK_EVT_FEAT_ONESHOT |
  55. CLOCK_EVT_FEAT_C3STOP;
  56. cd->rating = 350;
  57. cd->irq = gic_timer_irq;
  58. cd->cpumask = cpumask_of(cpu);
  59. cd->set_next_event = gic_next_event;
  60. cd->set_mode = gic_set_clock_mode;
  61. clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
  62. enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
  63. }
  64. static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
  65. {
  66. disable_percpu_irq(gic_timer_irq);
  67. }
  68. static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
  69. void *data)
  70. {
  71. switch (action & ~CPU_TASKS_FROZEN) {
  72. case CPU_STARTING:
  73. gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
  74. break;
  75. case CPU_DYING:
  76. gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
  77. break;
  78. }
  79. return NOTIFY_OK;
  80. }
  81. static struct notifier_block gic_cpu_nb = {
  82. .notifier_call = gic_cpu_notifier,
  83. };
  84. static int gic_clockevent_init(void)
  85. {
  86. if (!cpu_has_counter || !gic_frequency)
  87. return -ENXIO;
  88. setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
  89. register_cpu_notifier(&gic_cpu_nb);
  90. gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
  91. return 0;
  92. }
  93. static cycle_t gic_hpt_read(struct clocksource *cs)
  94. {
  95. return gic_read_count();
  96. }
  97. static struct clocksource gic_clocksource = {
  98. .name = "GIC",
  99. .read = gic_hpt_read,
  100. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  101. };
  102. static void __init __gic_clocksource_init(void)
  103. {
  104. /* Set clocksource mask. */
  105. gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
  106. /* Calculate a somewhat reasonable rating value. */
  107. gic_clocksource.rating = 200 + gic_frequency / 10000000;
  108. clocksource_register_hz(&gic_clocksource, gic_frequency);
  109. gic_clockevent_init();
  110. /* And finally start the counter */
  111. gic_start_count();
  112. }
  113. void __init gic_clocksource_init(unsigned int frequency)
  114. {
  115. gic_frequency = frequency;
  116. gic_timer_irq = MIPS_GIC_IRQ_BASE +
  117. GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
  118. __gic_clocksource_init();
  119. }
  120. static void __init gic_clocksource_of_init(struct device_node *node)
  121. {
  122. struct clk *clk;
  123. if (WARN_ON(!gic_present || !node->parent ||
  124. !of_device_is_compatible(node->parent, "mti,gic")))
  125. return;
  126. clk = of_clk_get(node, 0);
  127. if (!IS_ERR(clk)) {
  128. gic_frequency = clk_get_rate(clk);
  129. clk_put(clk);
  130. } else if (of_property_read_u32(node, "clock-frequency",
  131. &gic_frequency)) {
  132. pr_err("GIC frequency not specified.\n");
  133. return;
  134. }
  135. gic_timer_irq = irq_of_parse_and_map(node, 0);
  136. if (!gic_timer_irq) {
  137. pr_err("GIC timer IRQ not specified.\n");
  138. return;
  139. }
  140. __gic_clocksource_init();
  141. }
  142. CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
  143. gic_clocksource_of_init);