clk-tegra-fixed.c 2.8 KB

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  1. /*
  2. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <linux/clk-provider.h>
  19. #include <linux/of.h>
  20. #include <linux/of_address.h>
  21. #include <linux/delay.h>
  22. #include <linux/export.h>
  23. #include <linux/clk/tegra.h>
  24. #include "clk.h"
  25. #include "clk-id.h"
  26. #define OSC_CTRL 0x50
  27. #define OSC_CTRL_OSC_FREQ_SHIFT 28
  28. #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
  29. int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
  30. unsigned long *input_freqs, unsigned int num,
  31. unsigned int clk_m_div, unsigned long *osc_freq,
  32. unsigned long *pll_ref_freq)
  33. {
  34. struct clk *clk, *osc;
  35. struct clk **dt_clk;
  36. u32 val, pll_ref_div;
  37. unsigned osc_idx;
  38. val = readl_relaxed(clk_base + OSC_CTRL);
  39. osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
  40. if (osc_idx < num)
  41. *osc_freq = input_freqs[osc_idx];
  42. else
  43. *osc_freq = 0;
  44. if (!*osc_freq) {
  45. WARN_ON(1);
  46. return -EINVAL;
  47. }
  48. osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,
  49. *osc_freq);
  50. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
  51. if (!dt_clk)
  52. return 0;
  53. clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
  54. 0, 1, clk_m_div);
  55. *dt_clk = clk;
  56. /* pll_ref */
  57. val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
  58. pll_ref_div = 1 << val;
  59. dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
  60. if (!dt_clk)
  61. return 0;
  62. clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
  63. 0, 1, pll_ref_div);
  64. *dt_clk = clk;
  65. if (pll_ref_freq)
  66. *pll_ref_freq = *osc_freq / pll_ref_div;
  67. return 0;
  68. }
  69. void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
  70. {
  71. struct clk *clk;
  72. struct clk **dt_clk;
  73. /* clk_32k */
  74. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
  75. if (dt_clk) {
  76. clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
  77. CLK_IS_ROOT, 32768);
  78. *dt_clk = clk;
  79. }
  80. /* clk_m_div2 */
  81. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
  82. if (dt_clk) {
  83. clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
  84. CLK_SET_RATE_PARENT, 1, 2);
  85. *dt_clk = clk;
  86. }
  87. /* clk_m_div4 */
  88. dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
  89. if (dt_clk) {
  90. clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
  91. CLK_SET_RATE_PARENT, 1, 4);
  92. *dt_clk = clk;
  93. }
  94. }