intel_pt.h 3.1 KB

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  1. /*
  2. * Intel(R) Processor Trace PMU driver for perf
  3. * Copyright (c) 2013-2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * Intel PT is specified in the Intel Architecture Instruction Set Extensions
  15. * Programming Reference:
  16. * http://software.intel.com/en-us/intel-isa-extensions
  17. */
  18. #ifndef __INTEL_PT_H__
  19. #define __INTEL_PT_H__
  20. /*
  21. * Single-entry ToPA: when this close to region boundary, switch
  22. * buffers to avoid losing data.
  23. */
  24. #define TOPA_PMI_MARGIN 512
  25. /*
  26. * Table of Physical Addresses bits
  27. */
  28. enum topa_sz {
  29. TOPA_4K = 0,
  30. TOPA_8K,
  31. TOPA_16K,
  32. TOPA_32K,
  33. TOPA_64K,
  34. TOPA_128K,
  35. TOPA_256K,
  36. TOPA_512K,
  37. TOPA_1MB,
  38. TOPA_2MB,
  39. TOPA_4MB,
  40. TOPA_8MB,
  41. TOPA_16MB,
  42. TOPA_32MB,
  43. TOPA_64MB,
  44. TOPA_128MB,
  45. TOPA_SZ_END,
  46. };
  47. static inline unsigned int sizes(enum topa_sz tsz)
  48. {
  49. return 1 << (tsz + 12);
  50. };
  51. struct topa_entry {
  52. u64 end : 1;
  53. u64 rsvd0 : 1;
  54. u64 intr : 1;
  55. u64 rsvd1 : 1;
  56. u64 stop : 1;
  57. u64 rsvd2 : 1;
  58. u64 size : 4;
  59. u64 rsvd3 : 2;
  60. u64 base : 36;
  61. u64 rsvd4 : 16;
  62. };
  63. #define TOPA_SHIFT 12
  64. #define PT_CPUID_LEAVES 2
  65. enum pt_capabilities {
  66. PT_CAP_max_subleaf = 0,
  67. PT_CAP_cr3_filtering,
  68. PT_CAP_topa_output,
  69. PT_CAP_topa_multiple_entries,
  70. PT_CAP_payloads_lip,
  71. };
  72. struct pt_pmu {
  73. struct pmu pmu;
  74. u32 caps[4 * PT_CPUID_LEAVES];
  75. };
  76. /**
  77. * struct pt_buffer - buffer configuration; one buffer per task_struct or
  78. * cpu, depending on perf event configuration
  79. * @cpu: cpu for per-cpu allocation
  80. * @tables: list of ToPA tables in this buffer
  81. * @first: shorthand for first topa table
  82. * @last: shorthand for last topa table
  83. * @cur: current topa table
  84. * @nr_pages: buffer size in pages
  85. * @cur_idx: current output region's index within @cur table
  86. * @output_off: offset within the current output region
  87. * @data_size: running total of the amount of data in this buffer
  88. * @lost: if data was lost/truncated
  89. * @head: logical write offset inside the buffer
  90. * @snapshot: if this is for a snapshot/overwrite counter
  91. * @stop_pos: STOP topa entry in the buffer
  92. * @intr_pos: INT topa entry in the buffer
  93. * @data_pages: array of pages from perf
  94. * @topa_index: table of topa entries indexed by page offset
  95. */
  96. struct pt_buffer {
  97. int cpu;
  98. struct list_head tables;
  99. struct topa *first, *last, *cur;
  100. unsigned int cur_idx;
  101. size_t output_off;
  102. unsigned long nr_pages;
  103. local_t data_size;
  104. local_t lost;
  105. local64_t head;
  106. bool snapshot;
  107. unsigned long stop_pos, intr_pos;
  108. void **data_pages;
  109. struct topa_entry *topa_index[0];
  110. };
  111. /**
  112. * struct pt - per-cpu pt context
  113. * @handle: perf output handle
  114. * @handle_nmi: do handle PT PMI on this cpu, there's an active event
  115. */
  116. struct pt {
  117. struct perf_output_handle handle;
  118. int handle_nmi;
  119. };
  120. #endif /* __INTEL_PT_H__ */