aesni-intel_glue.c 46 KB

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  1. /*
  2. * Support for Intel AES-NI instructions. This file contains glue
  3. * code, the real AES implementation is in intel-aes_asm.S.
  4. *
  5. * Copyright (C) 2008, Intel Corp.
  6. * Author: Huang Ying <ying.huang@intel.com>
  7. *
  8. * Added RFC4106 AES-GCM support for 128-bit keys under the AEAD
  9. * interface for 64-bit kernels.
  10. * Authors: Adrian Hoban <adrian.hoban@intel.com>
  11. * Gabriele Paoloni <gabriele.paoloni@intel.com>
  12. * Tadeusz Struk (tadeusz.struk@intel.com)
  13. * Aidan O'Mahony (aidan.o.mahony@intel.com)
  14. * Copyright (c) 2010, Intel Corporation.
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2 of the License, or
  19. * (at your option) any later version.
  20. */
  21. #include <linux/hardirq.h>
  22. #include <linux/types.h>
  23. #include <linux/crypto.h>
  24. #include <linux/module.h>
  25. #include <linux/err.h>
  26. #include <crypto/algapi.h>
  27. #include <crypto/aes.h>
  28. #include <crypto/cryptd.h>
  29. #include <crypto/ctr.h>
  30. #include <crypto/b128ops.h>
  31. #include <crypto/lrw.h>
  32. #include <crypto/xts.h>
  33. #include <asm/cpu_device_id.h>
  34. #include <asm/i387.h>
  35. #include <asm/crypto/aes.h>
  36. #include <crypto/ablk_helper.h>
  37. #include <crypto/scatterwalk.h>
  38. #include <crypto/internal/aead.h>
  39. #include <linux/workqueue.h>
  40. #include <linux/spinlock.h>
  41. #ifdef CONFIG_X86_64
  42. #include <asm/crypto/glue_helper.h>
  43. #endif
  44. /* This data is stored at the end of the crypto_tfm struct.
  45. * It's a type of per "session" data storage location.
  46. * This needs to be 16 byte aligned.
  47. */
  48. struct aesni_rfc4106_gcm_ctx {
  49. u8 hash_subkey[16];
  50. struct crypto_aes_ctx aes_key_expanded;
  51. u8 nonce[4];
  52. struct cryptd_aead *cryptd_tfm;
  53. };
  54. struct aesni_gcm_set_hash_subkey_result {
  55. int err;
  56. struct completion completion;
  57. };
  58. struct aesni_hash_subkey_req_data {
  59. u8 iv[16];
  60. struct aesni_gcm_set_hash_subkey_result result;
  61. struct scatterlist sg;
  62. };
  63. #define AESNI_ALIGN (16)
  64. #define AES_BLOCK_MASK (~(AES_BLOCK_SIZE-1))
  65. #define RFC4106_HASH_SUBKEY_SIZE 16
  66. struct aesni_lrw_ctx {
  67. struct lrw_table_ctx lrw_table;
  68. u8 raw_aes_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  69. };
  70. struct aesni_xts_ctx {
  71. u8 raw_tweak_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  72. u8 raw_crypt_ctx[sizeof(struct crypto_aes_ctx) + AESNI_ALIGN - 1];
  73. };
  74. asmlinkage int aesni_set_key(struct crypto_aes_ctx *ctx, const u8 *in_key,
  75. unsigned int key_len);
  76. asmlinkage void aesni_enc(struct crypto_aes_ctx *ctx, u8 *out,
  77. const u8 *in);
  78. asmlinkage void aesni_dec(struct crypto_aes_ctx *ctx, u8 *out,
  79. const u8 *in);
  80. asmlinkage void aesni_ecb_enc(struct crypto_aes_ctx *ctx, u8 *out,
  81. const u8 *in, unsigned int len);
  82. asmlinkage void aesni_ecb_dec(struct crypto_aes_ctx *ctx, u8 *out,
  83. const u8 *in, unsigned int len);
  84. asmlinkage void aesni_cbc_enc(struct crypto_aes_ctx *ctx, u8 *out,
  85. const u8 *in, unsigned int len, u8 *iv);
  86. asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
  87. const u8 *in, unsigned int len, u8 *iv);
  88. int crypto_fpu_init(void);
  89. void crypto_fpu_exit(void);
  90. #define AVX_GEN2_OPTSIZE 640
  91. #define AVX_GEN4_OPTSIZE 4096
  92. #ifdef CONFIG_X86_64
  93. static void (*aesni_ctr_enc_tfm)(struct crypto_aes_ctx *ctx, u8 *out,
  94. const u8 *in, unsigned int len, u8 *iv);
  95. asmlinkage void aesni_ctr_enc(struct crypto_aes_ctx *ctx, u8 *out,
  96. const u8 *in, unsigned int len, u8 *iv);
  97. asmlinkage void aesni_xts_crypt8(struct crypto_aes_ctx *ctx, u8 *out,
  98. const u8 *in, bool enc, u8 *iv);
  99. /* asmlinkage void aesni_gcm_enc()
  100. * void *ctx, AES Key schedule. Starts on a 16 byte boundary.
  101. * u8 *out, Ciphertext output. Encrypt in-place is allowed.
  102. * const u8 *in, Plaintext input
  103. * unsigned long plaintext_len, Length of data in bytes for encryption.
  104. * u8 *iv, Pre-counter block j0: 4 byte salt (from Security Association)
  105. * concatenated with 8 byte Initialisation Vector (from IPSec ESP
  106. * Payload) concatenated with 0x00000001. 16-byte aligned pointer.
  107. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  108. * const u8 *aad, Additional Authentication Data (AAD)
  109. * unsigned long aad_len, Length of AAD in bytes. With RFC4106 this
  110. * is going to be 8 or 12 bytes
  111. * u8 *auth_tag, Authenticated Tag output.
  112. * unsigned long auth_tag_len), Authenticated Tag Length in bytes.
  113. * Valid values are 16 (most likely), 12 or 8.
  114. */
  115. asmlinkage void aesni_gcm_enc(void *ctx, u8 *out,
  116. const u8 *in, unsigned long plaintext_len, u8 *iv,
  117. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  118. u8 *auth_tag, unsigned long auth_tag_len);
  119. /* asmlinkage void aesni_gcm_dec()
  120. * void *ctx, AES Key schedule. Starts on a 16 byte boundary.
  121. * u8 *out, Plaintext output. Decrypt in-place is allowed.
  122. * const u8 *in, Ciphertext input
  123. * unsigned long ciphertext_len, Length of data in bytes for decryption.
  124. * u8 *iv, Pre-counter block j0: 4 byte salt (from Security Association)
  125. * concatenated with 8 byte Initialisation Vector (from IPSec ESP
  126. * Payload) concatenated with 0x00000001. 16-byte aligned pointer.
  127. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  128. * const u8 *aad, Additional Authentication Data (AAD)
  129. * unsigned long aad_len, Length of AAD in bytes. With RFC4106 this is going
  130. * to be 8 or 12 bytes
  131. * u8 *auth_tag, Authenticated Tag output.
  132. * unsigned long auth_tag_len) Authenticated Tag Length in bytes.
  133. * Valid values are 16 (most likely), 12 or 8.
  134. */
  135. asmlinkage void aesni_gcm_dec(void *ctx, u8 *out,
  136. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  137. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  138. u8 *auth_tag, unsigned long auth_tag_len);
  139. #ifdef CONFIG_AS_AVX
  140. asmlinkage void aes_ctr_enc_128_avx_by8(const u8 *in, u8 *iv,
  141. void *keys, u8 *out, unsigned int num_bytes);
  142. asmlinkage void aes_ctr_enc_192_avx_by8(const u8 *in, u8 *iv,
  143. void *keys, u8 *out, unsigned int num_bytes);
  144. asmlinkage void aes_ctr_enc_256_avx_by8(const u8 *in, u8 *iv,
  145. void *keys, u8 *out, unsigned int num_bytes);
  146. /*
  147. * asmlinkage void aesni_gcm_precomp_avx_gen2()
  148. * gcm_data *my_ctx_data, context data
  149. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  150. */
  151. asmlinkage void aesni_gcm_precomp_avx_gen2(void *my_ctx_data, u8 *hash_subkey);
  152. asmlinkage void aesni_gcm_enc_avx_gen2(void *ctx, u8 *out,
  153. const u8 *in, unsigned long plaintext_len, u8 *iv,
  154. const u8 *aad, unsigned long aad_len,
  155. u8 *auth_tag, unsigned long auth_tag_len);
  156. asmlinkage void aesni_gcm_dec_avx_gen2(void *ctx, u8 *out,
  157. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  158. const u8 *aad, unsigned long aad_len,
  159. u8 *auth_tag, unsigned long auth_tag_len);
  160. static void aesni_gcm_enc_avx(void *ctx, u8 *out,
  161. const u8 *in, unsigned long plaintext_len, u8 *iv,
  162. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  163. u8 *auth_tag, unsigned long auth_tag_len)
  164. {
  165. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  166. if ((plaintext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)){
  167. aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
  168. aad_len, auth_tag, auth_tag_len);
  169. } else {
  170. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  171. aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
  172. aad_len, auth_tag, auth_tag_len);
  173. }
  174. }
  175. static void aesni_gcm_dec_avx(void *ctx, u8 *out,
  176. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  177. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  178. u8 *auth_tag, unsigned long auth_tag_len)
  179. {
  180. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  181. if ((ciphertext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  182. aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey, aad,
  183. aad_len, auth_tag, auth_tag_len);
  184. } else {
  185. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  186. aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
  187. aad_len, auth_tag, auth_tag_len);
  188. }
  189. }
  190. #endif
  191. #ifdef CONFIG_AS_AVX2
  192. /*
  193. * asmlinkage void aesni_gcm_precomp_avx_gen4()
  194. * gcm_data *my_ctx_data, context data
  195. * u8 *hash_subkey, the Hash sub key input. Data starts on a 16-byte boundary.
  196. */
  197. asmlinkage void aesni_gcm_precomp_avx_gen4(void *my_ctx_data, u8 *hash_subkey);
  198. asmlinkage void aesni_gcm_enc_avx_gen4(void *ctx, u8 *out,
  199. const u8 *in, unsigned long plaintext_len, u8 *iv,
  200. const u8 *aad, unsigned long aad_len,
  201. u8 *auth_tag, unsigned long auth_tag_len);
  202. asmlinkage void aesni_gcm_dec_avx_gen4(void *ctx, u8 *out,
  203. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  204. const u8 *aad, unsigned long aad_len,
  205. u8 *auth_tag, unsigned long auth_tag_len);
  206. static void aesni_gcm_enc_avx2(void *ctx, u8 *out,
  207. const u8 *in, unsigned long plaintext_len, u8 *iv,
  208. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  209. u8 *auth_tag, unsigned long auth_tag_len)
  210. {
  211. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  212. if ((plaintext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  213. aesni_gcm_enc(ctx, out, in, plaintext_len, iv, hash_subkey, aad,
  214. aad_len, auth_tag, auth_tag_len);
  215. } else if (plaintext_len < AVX_GEN4_OPTSIZE) {
  216. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  217. aesni_gcm_enc_avx_gen2(ctx, out, in, plaintext_len, iv, aad,
  218. aad_len, auth_tag, auth_tag_len);
  219. } else {
  220. aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
  221. aesni_gcm_enc_avx_gen4(ctx, out, in, plaintext_len, iv, aad,
  222. aad_len, auth_tag, auth_tag_len);
  223. }
  224. }
  225. static void aesni_gcm_dec_avx2(void *ctx, u8 *out,
  226. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  227. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  228. u8 *auth_tag, unsigned long auth_tag_len)
  229. {
  230. struct crypto_aes_ctx *aes_ctx = (struct crypto_aes_ctx*)ctx;
  231. if ((ciphertext_len < AVX_GEN2_OPTSIZE) || (aes_ctx-> key_length != AES_KEYSIZE_128)) {
  232. aesni_gcm_dec(ctx, out, in, ciphertext_len, iv, hash_subkey,
  233. aad, aad_len, auth_tag, auth_tag_len);
  234. } else if (ciphertext_len < AVX_GEN4_OPTSIZE) {
  235. aesni_gcm_precomp_avx_gen2(ctx, hash_subkey);
  236. aesni_gcm_dec_avx_gen2(ctx, out, in, ciphertext_len, iv, aad,
  237. aad_len, auth_tag, auth_tag_len);
  238. } else {
  239. aesni_gcm_precomp_avx_gen4(ctx, hash_subkey);
  240. aesni_gcm_dec_avx_gen4(ctx, out, in, ciphertext_len, iv, aad,
  241. aad_len, auth_tag, auth_tag_len);
  242. }
  243. }
  244. #endif
  245. static void (*aesni_gcm_enc_tfm)(void *ctx, u8 *out,
  246. const u8 *in, unsigned long plaintext_len, u8 *iv,
  247. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  248. u8 *auth_tag, unsigned long auth_tag_len);
  249. static void (*aesni_gcm_dec_tfm)(void *ctx, u8 *out,
  250. const u8 *in, unsigned long ciphertext_len, u8 *iv,
  251. u8 *hash_subkey, const u8 *aad, unsigned long aad_len,
  252. u8 *auth_tag, unsigned long auth_tag_len);
  253. static inline struct
  254. aesni_rfc4106_gcm_ctx *aesni_rfc4106_gcm_ctx_get(struct crypto_aead *tfm)
  255. {
  256. return
  257. (struct aesni_rfc4106_gcm_ctx *)
  258. PTR_ALIGN((u8 *)
  259. crypto_tfm_ctx(crypto_aead_tfm(tfm)), AESNI_ALIGN);
  260. }
  261. #endif
  262. static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx)
  263. {
  264. unsigned long addr = (unsigned long)raw_ctx;
  265. unsigned long align = AESNI_ALIGN;
  266. if (align <= crypto_tfm_ctx_alignment())
  267. align = 1;
  268. return (struct crypto_aes_ctx *)ALIGN(addr, align);
  269. }
  270. static int aes_set_key_common(struct crypto_tfm *tfm, void *raw_ctx,
  271. const u8 *in_key, unsigned int key_len)
  272. {
  273. struct crypto_aes_ctx *ctx = aes_ctx(raw_ctx);
  274. u32 *flags = &tfm->crt_flags;
  275. int err;
  276. if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
  277. key_len != AES_KEYSIZE_256) {
  278. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  279. return -EINVAL;
  280. }
  281. if (!irq_fpu_usable())
  282. err = crypto_aes_expand_key(ctx, in_key, key_len);
  283. else {
  284. kernel_fpu_begin();
  285. err = aesni_set_key(ctx, in_key, key_len);
  286. kernel_fpu_end();
  287. }
  288. return err;
  289. }
  290. static int aes_set_key(struct crypto_tfm *tfm, const u8 *in_key,
  291. unsigned int key_len)
  292. {
  293. return aes_set_key_common(tfm, crypto_tfm_ctx(tfm), in_key, key_len);
  294. }
  295. static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  296. {
  297. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  298. if (!irq_fpu_usable())
  299. crypto_aes_encrypt_x86(ctx, dst, src);
  300. else {
  301. kernel_fpu_begin();
  302. aesni_enc(ctx, dst, src);
  303. kernel_fpu_end();
  304. }
  305. }
  306. static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  307. {
  308. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  309. if (!irq_fpu_usable())
  310. crypto_aes_decrypt_x86(ctx, dst, src);
  311. else {
  312. kernel_fpu_begin();
  313. aesni_dec(ctx, dst, src);
  314. kernel_fpu_end();
  315. }
  316. }
  317. static void __aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  318. {
  319. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  320. aesni_enc(ctx, dst, src);
  321. }
  322. static void __aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
  323. {
  324. struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
  325. aesni_dec(ctx, dst, src);
  326. }
  327. static int ecb_encrypt(struct blkcipher_desc *desc,
  328. struct scatterlist *dst, struct scatterlist *src,
  329. unsigned int nbytes)
  330. {
  331. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  332. struct blkcipher_walk walk;
  333. int err;
  334. blkcipher_walk_init(&walk, dst, src, nbytes);
  335. err = blkcipher_walk_virt(desc, &walk);
  336. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  337. kernel_fpu_begin();
  338. while ((nbytes = walk.nbytes)) {
  339. aesni_ecb_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  340. nbytes & AES_BLOCK_MASK);
  341. nbytes &= AES_BLOCK_SIZE - 1;
  342. err = blkcipher_walk_done(desc, &walk, nbytes);
  343. }
  344. kernel_fpu_end();
  345. return err;
  346. }
  347. static int ecb_decrypt(struct blkcipher_desc *desc,
  348. struct scatterlist *dst, struct scatterlist *src,
  349. unsigned int nbytes)
  350. {
  351. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  352. struct blkcipher_walk walk;
  353. int err;
  354. blkcipher_walk_init(&walk, dst, src, nbytes);
  355. err = blkcipher_walk_virt(desc, &walk);
  356. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  357. kernel_fpu_begin();
  358. while ((nbytes = walk.nbytes)) {
  359. aesni_ecb_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  360. nbytes & AES_BLOCK_MASK);
  361. nbytes &= AES_BLOCK_SIZE - 1;
  362. err = blkcipher_walk_done(desc, &walk, nbytes);
  363. }
  364. kernel_fpu_end();
  365. return err;
  366. }
  367. static int cbc_encrypt(struct blkcipher_desc *desc,
  368. struct scatterlist *dst, struct scatterlist *src,
  369. unsigned int nbytes)
  370. {
  371. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  372. struct blkcipher_walk walk;
  373. int err;
  374. blkcipher_walk_init(&walk, dst, src, nbytes);
  375. err = blkcipher_walk_virt(desc, &walk);
  376. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  377. kernel_fpu_begin();
  378. while ((nbytes = walk.nbytes)) {
  379. aesni_cbc_enc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  380. nbytes & AES_BLOCK_MASK, walk.iv);
  381. nbytes &= AES_BLOCK_SIZE - 1;
  382. err = blkcipher_walk_done(desc, &walk, nbytes);
  383. }
  384. kernel_fpu_end();
  385. return err;
  386. }
  387. static int cbc_decrypt(struct blkcipher_desc *desc,
  388. struct scatterlist *dst, struct scatterlist *src,
  389. unsigned int nbytes)
  390. {
  391. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  392. struct blkcipher_walk walk;
  393. int err;
  394. blkcipher_walk_init(&walk, dst, src, nbytes);
  395. err = blkcipher_walk_virt(desc, &walk);
  396. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  397. kernel_fpu_begin();
  398. while ((nbytes = walk.nbytes)) {
  399. aesni_cbc_dec(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  400. nbytes & AES_BLOCK_MASK, walk.iv);
  401. nbytes &= AES_BLOCK_SIZE - 1;
  402. err = blkcipher_walk_done(desc, &walk, nbytes);
  403. }
  404. kernel_fpu_end();
  405. return err;
  406. }
  407. #ifdef CONFIG_X86_64
  408. static void ctr_crypt_final(struct crypto_aes_ctx *ctx,
  409. struct blkcipher_walk *walk)
  410. {
  411. u8 *ctrblk = walk->iv;
  412. u8 keystream[AES_BLOCK_SIZE];
  413. u8 *src = walk->src.virt.addr;
  414. u8 *dst = walk->dst.virt.addr;
  415. unsigned int nbytes = walk->nbytes;
  416. aesni_enc(ctx, keystream, ctrblk);
  417. crypto_xor(keystream, src, nbytes);
  418. memcpy(dst, keystream, nbytes);
  419. crypto_inc(ctrblk, AES_BLOCK_SIZE);
  420. }
  421. #ifdef CONFIG_AS_AVX
  422. static void aesni_ctr_enc_avx_tfm(struct crypto_aes_ctx *ctx, u8 *out,
  423. const u8 *in, unsigned int len, u8 *iv)
  424. {
  425. /*
  426. * based on key length, override with the by8 version
  427. * of ctr mode encryption/decryption for improved performance
  428. * aes_set_key_common() ensures that key length is one of
  429. * {128,192,256}
  430. */
  431. if (ctx->key_length == AES_KEYSIZE_128)
  432. aes_ctr_enc_128_avx_by8(in, iv, (void *)ctx, out, len);
  433. else if (ctx->key_length == AES_KEYSIZE_192)
  434. aes_ctr_enc_192_avx_by8(in, iv, (void *)ctx, out, len);
  435. else
  436. aes_ctr_enc_256_avx_by8(in, iv, (void *)ctx, out, len);
  437. }
  438. #endif
  439. static int ctr_crypt(struct blkcipher_desc *desc,
  440. struct scatterlist *dst, struct scatterlist *src,
  441. unsigned int nbytes)
  442. {
  443. struct crypto_aes_ctx *ctx = aes_ctx(crypto_blkcipher_ctx(desc->tfm));
  444. struct blkcipher_walk walk;
  445. int err;
  446. blkcipher_walk_init(&walk, dst, src, nbytes);
  447. err = blkcipher_walk_virt_block(desc, &walk, AES_BLOCK_SIZE);
  448. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  449. kernel_fpu_begin();
  450. while ((nbytes = walk.nbytes) >= AES_BLOCK_SIZE) {
  451. aesni_ctr_enc_tfm(ctx, walk.dst.virt.addr, walk.src.virt.addr,
  452. nbytes & AES_BLOCK_MASK, walk.iv);
  453. nbytes &= AES_BLOCK_SIZE - 1;
  454. err = blkcipher_walk_done(desc, &walk, nbytes);
  455. }
  456. if (walk.nbytes) {
  457. ctr_crypt_final(ctx, &walk);
  458. err = blkcipher_walk_done(desc, &walk, 0);
  459. }
  460. kernel_fpu_end();
  461. return err;
  462. }
  463. #endif
  464. static int ablk_ecb_init(struct crypto_tfm *tfm)
  465. {
  466. return ablk_init_common(tfm, "__driver-ecb-aes-aesni");
  467. }
  468. static int ablk_cbc_init(struct crypto_tfm *tfm)
  469. {
  470. return ablk_init_common(tfm, "__driver-cbc-aes-aesni");
  471. }
  472. #ifdef CONFIG_X86_64
  473. static int ablk_ctr_init(struct crypto_tfm *tfm)
  474. {
  475. return ablk_init_common(tfm, "__driver-ctr-aes-aesni");
  476. }
  477. #endif
  478. #if IS_ENABLED(CONFIG_CRYPTO_PCBC)
  479. static int ablk_pcbc_init(struct crypto_tfm *tfm)
  480. {
  481. return ablk_init_common(tfm, "fpu(pcbc(__driver-aes-aesni))");
  482. }
  483. #endif
  484. static void lrw_xts_encrypt_callback(void *ctx, u8 *blks, unsigned int nbytes)
  485. {
  486. aesni_ecb_enc(ctx, blks, blks, nbytes);
  487. }
  488. static void lrw_xts_decrypt_callback(void *ctx, u8 *blks, unsigned int nbytes)
  489. {
  490. aesni_ecb_dec(ctx, blks, blks, nbytes);
  491. }
  492. static int lrw_aesni_setkey(struct crypto_tfm *tfm, const u8 *key,
  493. unsigned int keylen)
  494. {
  495. struct aesni_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
  496. int err;
  497. err = aes_set_key_common(tfm, ctx->raw_aes_ctx, key,
  498. keylen - AES_BLOCK_SIZE);
  499. if (err)
  500. return err;
  501. return lrw_init_table(&ctx->lrw_table, key + keylen - AES_BLOCK_SIZE);
  502. }
  503. static void lrw_aesni_exit_tfm(struct crypto_tfm *tfm)
  504. {
  505. struct aesni_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
  506. lrw_free_table(&ctx->lrw_table);
  507. }
  508. static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  509. struct scatterlist *src, unsigned int nbytes)
  510. {
  511. struct aesni_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  512. be128 buf[8];
  513. struct lrw_crypt_req req = {
  514. .tbuf = buf,
  515. .tbuflen = sizeof(buf),
  516. .table_ctx = &ctx->lrw_table,
  517. .crypt_ctx = aes_ctx(ctx->raw_aes_ctx),
  518. .crypt_fn = lrw_xts_encrypt_callback,
  519. };
  520. int ret;
  521. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  522. kernel_fpu_begin();
  523. ret = lrw_crypt(desc, dst, src, nbytes, &req);
  524. kernel_fpu_end();
  525. return ret;
  526. }
  527. static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  528. struct scatterlist *src, unsigned int nbytes)
  529. {
  530. struct aesni_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  531. be128 buf[8];
  532. struct lrw_crypt_req req = {
  533. .tbuf = buf,
  534. .tbuflen = sizeof(buf),
  535. .table_ctx = &ctx->lrw_table,
  536. .crypt_ctx = aes_ctx(ctx->raw_aes_ctx),
  537. .crypt_fn = lrw_xts_decrypt_callback,
  538. };
  539. int ret;
  540. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  541. kernel_fpu_begin();
  542. ret = lrw_crypt(desc, dst, src, nbytes, &req);
  543. kernel_fpu_end();
  544. return ret;
  545. }
  546. static int xts_aesni_setkey(struct crypto_tfm *tfm, const u8 *key,
  547. unsigned int keylen)
  548. {
  549. struct aesni_xts_ctx *ctx = crypto_tfm_ctx(tfm);
  550. u32 *flags = &tfm->crt_flags;
  551. int err;
  552. /* key consists of keys of equal size concatenated, therefore
  553. * the length must be even
  554. */
  555. if (keylen % 2) {
  556. *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
  557. return -EINVAL;
  558. }
  559. /* first half of xts-key is for crypt */
  560. err = aes_set_key_common(tfm, ctx->raw_crypt_ctx, key, keylen / 2);
  561. if (err)
  562. return err;
  563. /* second half of xts-key is for tweak */
  564. return aes_set_key_common(tfm, ctx->raw_tweak_ctx, key + keylen / 2,
  565. keylen / 2);
  566. }
  567. static void aesni_xts_tweak(void *ctx, u8 *out, const u8 *in)
  568. {
  569. aesni_enc(ctx, out, in);
  570. }
  571. #ifdef CONFIG_X86_64
  572. static void aesni_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  573. {
  574. glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_enc));
  575. }
  576. static void aesni_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  577. {
  578. glue_xts_crypt_128bit_one(ctx, dst, src, iv, GLUE_FUNC_CAST(aesni_dec));
  579. }
  580. static void aesni_xts_enc8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  581. {
  582. aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, true, (u8 *)iv);
  583. }
  584. static void aesni_xts_dec8(void *ctx, u128 *dst, const u128 *src, le128 *iv)
  585. {
  586. aesni_xts_crypt8(ctx, (u8 *)dst, (const u8 *)src, false, (u8 *)iv);
  587. }
  588. static const struct common_glue_ctx aesni_enc_xts = {
  589. .num_funcs = 2,
  590. .fpu_blocks_limit = 1,
  591. .funcs = { {
  592. .num_blocks = 8,
  593. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc8) }
  594. }, {
  595. .num_blocks = 1,
  596. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_enc) }
  597. } }
  598. };
  599. static const struct common_glue_ctx aesni_dec_xts = {
  600. .num_funcs = 2,
  601. .fpu_blocks_limit = 1,
  602. .funcs = { {
  603. .num_blocks = 8,
  604. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec8) }
  605. }, {
  606. .num_blocks = 1,
  607. .fn_u = { .xts = GLUE_XTS_FUNC_CAST(aesni_xts_dec) }
  608. } }
  609. };
  610. static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  611. struct scatterlist *src, unsigned int nbytes)
  612. {
  613. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  614. return glue_xts_crypt_128bit(&aesni_enc_xts, desc, dst, src, nbytes,
  615. XTS_TWEAK_CAST(aesni_xts_tweak),
  616. aes_ctx(ctx->raw_tweak_ctx),
  617. aes_ctx(ctx->raw_crypt_ctx));
  618. }
  619. static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  620. struct scatterlist *src, unsigned int nbytes)
  621. {
  622. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  623. return glue_xts_crypt_128bit(&aesni_dec_xts, desc, dst, src, nbytes,
  624. XTS_TWEAK_CAST(aesni_xts_tweak),
  625. aes_ctx(ctx->raw_tweak_ctx),
  626. aes_ctx(ctx->raw_crypt_ctx));
  627. }
  628. #else
  629. static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  630. struct scatterlist *src, unsigned int nbytes)
  631. {
  632. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  633. be128 buf[8];
  634. struct xts_crypt_req req = {
  635. .tbuf = buf,
  636. .tbuflen = sizeof(buf),
  637. .tweak_ctx = aes_ctx(ctx->raw_tweak_ctx),
  638. .tweak_fn = aesni_xts_tweak,
  639. .crypt_ctx = aes_ctx(ctx->raw_crypt_ctx),
  640. .crypt_fn = lrw_xts_encrypt_callback,
  641. };
  642. int ret;
  643. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  644. kernel_fpu_begin();
  645. ret = xts_crypt(desc, dst, src, nbytes, &req);
  646. kernel_fpu_end();
  647. return ret;
  648. }
  649. static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
  650. struct scatterlist *src, unsigned int nbytes)
  651. {
  652. struct aesni_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
  653. be128 buf[8];
  654. struct xts_crypt_req req = {
  655. .tbuf = buf,
  656. .tbuflen = sizeof(buf),
  657. .tweak_ctx = aes_ctx(ctx->raw_tweak_ctx),
  658. .tweak_fn = aesni_xts_tweak,
  659. .crypt_ctx = aes_ctx(ctx->raw_crypt_ctx),
  660. .crypt_fn = lrw_xts_decrypt_callback,
  661. };
  662. int ret;
  663. desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
  664. kernel_fpu_begin();
  665. ret = xts_crypt(desc, dst, src, nbytes, &req);
  666. kernel_fpu_end();
  667. return ret;
  668. }
  669. #endif
  670. #ifdef CONFIG_X86_64
  671. static int rfc4106_init(struct crypto_tfm *tfm)
  672. {
  673. struct cryptd_aead *cryptd_tfm;
  674. struct aesni_rfc4106_gcm_ctx *ctx = (struct aesni_rfc4106_gcm_ctx *)
  675. PTR_ALIGN((u8 *)crypto_tfm_ctx(tfm), AESNI_ALIGN);
  676. struct crypto_aead *cryptd_child;
  677. struct aesni_rfc4106_gcm_ctx *child_ctx;
  678. cryptd_tfm = cryptd_alloc_aead("__driver-gcm-aes-aesni",
  679. CRYPTO_ALG_INTERNAL,
  680. CRYPTO_ALG_INTERNAL);
  681. if (IS_ERR(cryptd_tfm))
  682. return PTR_ERR(cryptd_tfm);
  683. cryptd_child = cryptd_aead_child(cryptd_tfm);
  684. child_ctx = aesni_rfc4106_gcm_ctx_get(cryptd_child);
  685. memcpy(child_ctx, ctx, sizeof(*ctx));
  686. ctx->cryptd_tfm = cryptd_tfm;
  687. tfm->crt_aead.reqsize = sizeof(struct aead_request)
  688. + crypto_aead_reqsize(&cryptd_tfm->base);
  689. return 0;
  690. }
  691. static void rfc4106_exit(struct crypto_tfm *tfm)
  692. {
  693. struct aesni_rfc4106_gcm_ctx *ctx =
  694. (struct aesni_rfc4106_gcm_ctx *)
  695. PTR_ALIGN((u8 *)crypto_tfm_ctx(tfm), AESNI_ALIGN);
  696. if (!IS_ERR(ctx->cryptd_tfm))
  697. cryptd_free_aead(ctx->cryptd_tfm);
  698. return;
  699. }
  700. static void
  701. rfc4106_set_hash_subkey_done(struct crypto_async_request *req, int err)
  702. {
  703. struct aesni_gcm_set_hash_subkey_result *result = req->data;
  704. if (err == -EINPROGRESS)
  705. return;
  706. result->err = err;
  707. complete(&result->completion);
  708. }
  709. static int
  710. rfc4106_set_hash_subkey(u8 *hash_subkey, const u8 *key, unsigned int key_len)
  711. {
  712. struct crypto_ablkcipher *ctr_tfm;
  713. struct ablkcipher_request *req;
  714. int ret = -EINVAL;
  715. struct aesni_hash_subkey_req_data *req_data;
  716. ctr_tfm = crypto_alloc_ablkcipher("ctr(aes)", 0, 0);
  717. if (IS_ERR(ctr_tfm))
  718. return PTR_ERR(ctr_tfm);
  719. crypto_ablkcipher_clear_flags(ctr_tfm, ~0);
  720. ret = crypto_ablkcipher_setkey(ctr_tfm, key, key_len);
  721. if (ret)
  722. goto out_free_ablkcipher;
  723. ret = -ENOMEM;
  724. req = ablkcipher_request_alloc(ctr_tfm, GFP_KERNEL);
  725. if (!req)
  726. goto out_free_ablkcipher;
  727. req_data = kmalloc(sizeof(*req_data), GFP_KERNEL);
  728. if (!req_data)
  729. goto out_free_request;
  730. memset(req_data->iv, 0, sizeof(req_data->iv));
  731. /* Clear the data in the hash sub key container to zero.*/
  732. /* We want to cipher all zeros to create the hash sub key. */
  733. memset(hash_subkey, 0, RFC4106_HASH_SUBKEY_SIZE);
  734. init_completion(&req_data->result.completion);
  735. sg_init_one(&req_data->sg, hash_subkey, RFC4106_HASH_SUBKEY_SIZE);
  736. ablkcipher_request_set_tfm(req, ctr_tfm);
  737. ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_SLEEP |
  738. CRYPTO_TFM_REQ_MAY_BACKLOG,
  739. rfc4106_set_hash_subkey_done,
  740. &req_data->result);
  741. ablkcipher_request_set_crypt(req, &req_data->sg,
  742. &req_data->sg, RFC4106_HASH_SUBKEY_SIZE, req_data->iv);
  743. ret = crypto_ablkcipher_encrypt(req);
  744. if (ret == -EINPROGRESS || ret == -EBUSY) {
  745. ret = wait_for_completion_interruptible
  746. (&req_data->result.completion);
  747. if (!ret)
  748. ret = req_data->result.err;
  749. }
  750. kfree(req_data);
  751. out_free_request:
  752. ablkcipher_request_free(req);
  753. out_free_ablkcipher:
  754. crypto_free_ablkcipher(ctr_tfm);
  755. return ret;
  756. }
  757. static int common_rfc4106_set_key(struct crypto_aead *aead, const u8 *key,
  758. unsigned int key_len)
  759. {
  760. int ret = 0;
  761. struct crypto_tfm *tfm = crypto_aead_tfm(aead);
  762. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(aead);
  763. u8 *new_key_align, *new_key_mem = NULL;
  764. if (key_len < 4) {
  765. crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  766. return -EINVAL;
  767. }
  768. /*Account for 4 byte nonce at the end.*/
  769. key_len -= 4;
  770. if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_192 &&
  771. key_len != AES_KEYSIZE_256) {
  772. crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  773. return -EINVAL;
  774. }
  775. memcpy(ctx->nonce, key + key_len, sizeof(ctx->nonce));
  776. /*This must be on a 16 byte boundary!*/
  777. if ((unsigned long)(&(ctx->aes_key_expanded.key_enc[0])) % AESNI_ALIGN)
  778. return -EINVAL;
  779. if ((unsigned long)key % AESNI_ALIGN) {
  780. /*key is not aligned: use an auxuliar aligned pointer*/
  781. new_key_mem = kmalloc(key_len+AESNI_ALIGN, GFP_KERNEL);
  782. if (!new_key_mem)
  783. return -ENOMEM;
  784. new_key_align = PTR_ALIGN(new_key_mem, AESNI_ALIGN);
  785. memcpy(new_key_align, key, key_len);
  786. key = new_key_align;
  787. }
  788. if (!irq_fpu_usable())
  789. ret = crypto_aes_expand_key(&(ctx->aes_key_expanded),
  790. key, key_len);
  791. else {
  792. kernel_fpu_begin();
  793. ret = aesni_set_key(&(ctx->aes_key_expanded), key, key_len);
  794. kernel_fpu_end();
  795. }
  796. /*This must be on a 16 byte boundary!*/
  797. if ((unsigned long)(&(ctx->hash_subkey[0])) % AESNI_ALIGN) {
  798. ret = -EINVAL;
  799. goto exit;
  800. }
  801. ret = rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len);
  802. exit:
  803. kfree(new_key_mem);
  804. return ret;
  805. }
  806. static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
  807. unsigned int key_len)
  808. {
  809. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent);
  810. struct crypto_aead *child = cryptd_aead_child(ctx->cryptd_tfm);
  811. struct aesni_rfc4106_gcm_ctx *c_ctx = aesni_rfc4106_gcm_ctx_get(child);
  812. struct cryptd_aead *cryptd_tfm = ctx->cryptd_tfm;
  813. int ret;
  814. ret = crypto_aead_setkey(child, key, key_len);
  815. if (!ret) {
  816. memcpy(ctx, c_ctx, sizeof(*ctx));
  817. ctx->cryptd_tfm = cryptd_tfm;
  818. }
  819. return ret;
  820. }
  821. static int common_rfc4106_set_authsize(struct crypto_aead *aead,
  822. unsigned int authsize)
  823. {
  824. switch (authsize) {
  825. case 8:
  826. case 12:
  827. case 16:
  828. break;
  829. default:
  830. return -EINVAL;
  831. }
  832. crypto_aead_crt(aead)->authsize = authsize;
  833. return 0;
  834. }
  835. /* This is the Integrity Check Value (aka the authentication tag length and can
  836. * be 8, 12 or 16 bytes long. */
  837. static int rfc4106_set_authsize(struct crypto_aead *parent,
  838. unsigned int authsize)
  839. {
  840. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent);
  841. struct crypto_aead *child = cryptd_aead_child(ctx->cryptd_tfm);
  842. int ret;
  843. ret = crypto_aead_setauthsize(child, authsize);
  844. if (!ret)
  845. crypto_aead_crt(parent)->authsize = authsize;
  846. return ret;
  847. }
  848. static int __driver_rfc4106_encrypt(struct aead_request *req)
  849. {
  850. u8 one_entry_in_sg = 0;
  851. u8 *src, *dst, *assoc;
  852. __be32 counter = cpu_to_be32(1);
  853. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  854. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  855. u32 key_len = ctx->aes_key_expanded.key_length;
  856. void *aes_ctx = &(ctx->aes_key_expanded);
  857. unsigned long auth_tag_len = crypto_aead_authsize(tfm);
  858. u8 iv_tab[16+AESNI_ALIGN];
  859. u8* iv = (u8 *) PTR_ALIGN((u8 *)iv_tab, AESNI_ALIGN);
  860. struct scatter_walk src_sg_walk;
  861. struct scatter_walk assoc_sg_walk;
  862. struct scatter_walk dst_sg_walk;
  863. unsigned int i;
  864. /* Assuming we are supporting rfc4106 64-bit extended */
  865. /* sequence numbers We need to have the AAD length equal */
  866. /* to 8 or 12 bytes */
  867. if (unlikely(req->assoclen != 8 && req->assoclen != 12))
  868. return -EINVAL;
  869. if (unlikely(auth_tag_len != 8 && auth_tag_len != 12 && auth_tag_len != 16))
  870. return -EINVAL;
  871. if (unlikely(key_len != AES_KEYSIZE_128 &&
  872. key_len != AES_KEYSIZE_192 &&
  873. key_len != AES_KEYSIZE_256))
  874. return -EINVAL;
  875. /* IV below built */
  876. for (i = 0; i < 4; i++)
  877. *(iv+i) = ctx->nonce[i];
  878. for (i = 0; i < 8; i++)
  879. *(iv+4+i) = req->iv[i];
  880. *((__be32 *)(iv+12)) = counter;
  881. if ((sg_is_last(req->src)) && (sg_is_last(req->assoc))) {
  882. one_entry_in_sg = 1;
  883. scatterwalk_start(&src_sg_walk, req->src);
  884. scatterwalk_start(&assoc_sg_walk, req->assoc);
  885. src = scatterwalk_map(&src_sg_walk);
  886. assoc = scatterwalk_map(&assoc_sg_walk);
  887. dst = src;
  888. if (unlikely(req->src != req->dst)) {
  889. scatterwalk_start(&dst_sg_walk, req->dst);
  890. dst = scatterwalk_map(&dst_sg_walk);
  891. }
  892. } else {
  893. /* Allocate memory for src, dst, assoc */
  894. src = kmalloc(req->cryptlen + auth_tag_len + req->assoclen,
  895. GFP_ATOMIC);
  896. if (unlikely(!src))
  897. return -ENOMEM;
  898. assoc = (src + req->cryptlen + auth_tag_len);
  899. scatterwalk_map_and_copy(src, req->src, 0, req->cryptlen, 0);
  900. scatterwalk_map_and_copy(assoc, req->assoc, 0,
  901. req->assoclen, 0);
  902. dst = src;
  903. }
  904. aesni_gcm_enc_tfm(aes_ctx, dst, src, (unsigned long)req->cryptlen, iv,
  905. ctx->hash_subkey, assoc, (unsigned long)req->assoclen, dst
  906. + ((unsigned long)req->cryptlen), auth_tag_len);
  907. /* The authTag (aka the Integrity Check Value) needs to be written
  908. * back to the packet. */
  909. if (one_entry_in_sg) {
  910. if (unlikely(req->src != req->dst)) {
  911. scatterwalk_unmap(dst);
  912. scatterwalk_done(&dst_sg_walk, 0, 0);
  913. }
  914. scatterwalk_unmap(src);
  915. scatterwalk_unmap(assoc);
  916. scatterwalk_done(&src_sg_walk, 0, 0);
  917. scatterwalk_done(&assoc_sg_walk, 0, 0);
  918. } else {
  919. scatterwalk_map_and_copy(dst, req->dst, 0,
  920. req->cryptlen + auth_tag_len, 1);
  921. kfree(src);
  922. }
  923. return 0;
  924. }
  925. static int __driver_rfc4106_decrypt(struct aead_request *req)
  926. {
  927. u8 one_entry_in_sg = 0;
  928. u8 *src, *dst, *assoc;
  929. unsigned long tempCipherLen = 0;
  930. __be32 counter = cpu_to_be32(1);
  931. int retval = 0;
  932. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  933. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  934. u32 key_len = ctx->aes_key_expanded.key_length;
  935. void *aes_ctx = &(ctx->aes_key_expanded);
  936. unsigned long auth_tag_len = crypto_aead_authsize(tfm);
  937. u8 iv_and_authTag[32+AESNI_ALIGN];
  938. u8 *iv = (u8 *) PTR_ALIGN((u8 *)iv_and_authTag, AESNI_ALIGN);
  939. u8 *authTag = iv + 16;
  940. struct scatter_walk src_sg_walk;
  941. struct scatter_walk assoc_sg_walk;
  942. struct scatter_walk dst_sg_walk;
  943. unsigned int i;
  944. if (unlikely((req->cryptlen < auth_tag_len) ||
  945. (req->assoclen != 8 && req->assoclen != 12)))
  946. return -EINVAL;
  947. if (unlikely(auth_tag_len != 8 && auth_tag_len != 12 && auth_tag_len != 16))
  948. return -EINVAL;
  949. if (unlikely(key_len != AES_KEYSIZE_128 &&
  950. key_len != AES_KEYSIZE_192 &&
  951. key_len != AES_KEYSIZE_256))
  952. return -EINVAL;
  953. /* Assuming we are supporting rfc4106 64-bit extended */
  954. /* sequence numbers We need to have the AAD length */
  955. /* equal to 8 or 12 bytes */
  956. tempCipherLen = (unsigned long)(req->cryptlen - auth_tag_len);
  957. /* IV below built */
  958. for (i = 0; i < 4; i++)
  959. *(iv+i) = ctx->nonce[i];
  960. for (i = 0; i < 8; i++)
  961. *(iv+4+i) = req->iv[i];
  962. *((__be32 *)(iv+12)) = counter;
  963. if ((sg_is_last(req->src)) && (sg_is_last(req->assoc))) {
  964. one_entry_in_sg = 1;
  965. scatterwalk_start(&src_sg_walk, req->src);
  966. scatterwalk_start(&assoc_sg_walk, req->assoc);
  967. src = scatterwalk_map(&src_sg_walk);
  968. assoc = scatterwalk_map(&assoc_sg_walk);
  969. dst = src;
  970. if (unlikely(req->src != req->dst)) {
  971. scatterwalk_start(&dst_sg_walk, req->dst);
  972. dst = scatterwalk_map(&dst_sg_walk);
  973. }
  974. } else {
  975. /* Allocate memory for src, dst, assoc */
  976. src = kmalloc(req->cryptlen + req->assoclen, GFP_ATOMIC);
  977. if (!src)
  978. return -ENOMEM;
  979. assoc = (src + req->cryptlen);
  980. scatterwalk_map_and_copy(src, req->src, 0, req->cryptlen, 0);
  981. scatterwalk_map_and_copy(assoc, req->assoc, 0,
  982. req->assoclen, 0);
  983. dst = src;
  984. }
  985. aesni_gcm_dec_tfm(aes_ctx, dst, src, tempCipherLen, iv,
  986. ctx->hash_subkey, assoc, (unsigned long)req->assoclen,
  987. authTag, auth_tag_len);
  988. /* Compare generated tag with passed in tag. */
  989. retval = crypto_memneq(src + tempCipherLen, authTag, auth_tag_len) ?
  990. -EBADMSG : 0;
  991. if (one_entry_in_sg) {
  992. if (unlikely(req->src != req->dst)) {
  993. scatterwalk_unmap(dst);
  994. scatterwalk_done(&dst_sg_walk, 0, 0);
  995. }
  996. scatterwalk_unmap(src);
  997. scatterwalk_unmap(assoc);
  998. scatterwalk_done(&src_sg_walk, 0, 0);
  999. scatterwalk_done(&assoc_sg_walk, 0, 0);
  1000. } else {
  1001. scatterwalk_map_and_copy(dst, req->dst, 0, tempCipherLen, 1);
  1002. kfree(src);
  1003. }
  1004. return retval;
  1005. }
  1006. static int rfc4106_encrypt(struct aead_request *req)
  1007. {
  1008. int ret;
  1009. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  1010. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  1011. if (!irq_fpu_usable()) {
  1012. struct aead_request *cryptd_req =
  1013. (struct aead_request *) aead_request_ctx(req);
  1014. memcpy(cryptd_req, req, sizeof(*req));
  1015. aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
  1016. ret = crypto_aead_encrypt(cryptd_req);
  1017. } else {
  1018. kernel_fpu_begin();
  1019. ret = __driver_rfc4106_encrypt(req);
  1020. kernel_fpu_end();
  1021. }
  1022. return ret;
  1023. }
  1024. static int rfc4106_decrypt(struct aead_request *req)
  1025. {
  1026. int ret;
  1027. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  1028. struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
  1029. if (!irq_fpu_usable()) {
  1030. struct aead_request *cryptd_req =
  1031. (struct aead_request *) aead_request_ctx(req);
  1032. memcpy(cryptd_req, req, sizeof(*req));
  1033. aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
  1034. ret = crypto_aead_decrypt(cryptd_req);
  1035. } else {
  1036. kernel_fpu_begin();
  1037. ret = __driver_rfc4106_decrypt(req);
  1038. kernel_fpu_end();
  1039. }
  1040. return ret;
  1041. }
  1042. static int helper_rfc4106_encrypt(struct aead_request *req)
  1043. {
  1044. int ret;
  1045. if (unlikely(!irq_fpu_usable())) {
  1046. WARN_ONCE(1, "__gcm-aes-aesni alg used in invalid context");
  1047. ret = -EINVAL;
  1048. } else {
  1049. kernel_fpu_begin();
  1050. ret = __driver_rfc4106_encrypt(req);
  1051. kernel_fpu_end();
  1052. }
  1053. return ret;
  1054. }
  1055. static int helper_rfc4106_decrypt(struct aead_request *req)
  1056. {
  1057. int ret;
  1058. if (unlikely(!irq_fpu_usable())) {
  1059. WARN_ONCE(1, "__gcm-aes-aesni alg used in invalid context");
  1060. ret = -EINVAL;
  1061. } else {
  1062. kernel_fpu_begin();
  1063. ret = __driver_rfc4106_decrypt(req);
  1064. kernel_fpu_end();
  1065. }
  1066. return ret;
  1067. }
  1068. #endif
  1069. static struct crypto_alg aesni_algs[] = { {
  1070. .cra_name = "aes",
  1071. .cra_driver_name = "aes-aesni",
  1072. .cra_priority = 300,
  1073. .cra_flags = CRYPTO_ALG_TYPE_CIPHER,
  1074. .cra_blocksize = AES_BLOCK_SIZE,
  1075. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1076. AESNI_ALIGN - 1,
  1077. .cra_alignmask = 0,
  1078. .cra_module = THIS_MODULE,
  1079. .cra_u = {
  1080. .cipher = {
  1081. .cia_min_keysize = AES_MIN_KEY_SIZE,
  1082. .cia_max_keysize = AES_MAX_KEY_SIZE,
  1083. .cia_setkey = aes_set_key,
  1084. .cia_encrypt = aes_encrypt,
  1085. .cia_decrypt = aes_decrypt
  1086. }
  1087. }
  1088. }, {
  1089. .cra_name = "__aes-aesni",
  1090. .cra_driver_name = "__driver-aes-aesni",
  1091. .cra_priority = 0,
  1092. .cra_flags = CRYPTO_ALG_TYPE_CIPHER | CRYPTO_ALG_INTERNAL,
  1093. .cra_blocksize = AES_BLOCK_SIZE,
  1094. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1095. AESNI_ALIGN - 1,
  1096. .cra_alignmask = 0,
  1097. .cra_module = THIS_MODULE,
  1098. .cra_u = {
  1099. .cipher = {
  1100. .cia_min_keysize = AES_MIN_KEY_SIZE,
  1101. .cia_max_keysize = AES_MAX_KEY_SIZE,
  1102. .cia_setkey = aes_set_key,
  1103. .cia_encrypt = __aes_encrypt,
  1104. .cia_decrypt = __aes_decrypt
  1105. }
  1106. }
  1107. }, {
  1108. .cra_name = "__ecb-aes-aesni",
  1109. .cra_driver_name = "__driver-ecb-aes-aesni",
  1110. .cra_priority = 0,
  1111. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1112. CRYPTO_ALG_INTERNAL,
  1113. .cra_blocksize = AES_BLOCK_SIZE,
  1114. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1115. AESNI_ALIGN - 1,
  1116. .cra_alignmask = 0,
  1117. .cra_type = &crypto_blkcipher_type,
  1118. .cra_module = THIS_MODULE,
  1119. .cra_u = {
  1120. .blkcipher = {
  1121. .min_keysize = AES_MIN_KEY_SIZE,
  1122. .max_keysize = AES_MAX_KEY_SIZE,
  1123. .setkey = aes_set_key,
  1124. .encrypt = ecb_encrypt,
  1125. .decrypt = ecb_decrypt,
  1126. },
  1127. },
  1128. }, {
  1129. .cra_name = "__cbc-aes-aesni",
  1130. .cra_driver_name = "__driver-cbc-aes-aesni",
  1131. .cra_priority = 0,
  1132. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1133. CRYPTO_ALG_INTERNAL,
  1134. .cra_blocksize = AES_BLOCK_SIZE,
  1135. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1136. AESNI_ALIGN - 1,
  1137. .cra_alignmask = 0,
  1138. .cra_type = &crypto_blkcipher_type,
  1139. .cra_module = THIS_MODULE,
  1140. .cra_u = {
  1141. .blkcipher = {
  1142. .min_keysize = AES_MIN_KEY_SIZE,
  1143. .max_keysize = AES_MAX_KEY_SIZE,
  1144. .setkey = aes_set_key,
  1145. .encrypt = cbc_encrypt,
  1146. .decrypt = cbc_decrypt,
  1147. },
  1148. },
  1149. }, {
  1150. .cra_name = "ecb(aes)",
  1151. .cra_driver_name = "ecb-aes-aesni",
  1152. .cra_priority = 400,
  1153. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1154. .cra_blocksize = AES_BLOCK_SIZE,
  1155. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1156. .cra_alignmask = 0,
  1157. .cra_type = &crypto_ablkcipher_type,
  1158. .cra_module = THIS_MODULE,
  1159. .cra_init = ablk_ecb_init,
  1160. .cra_exit = ablk_exit,
  1161. .cra_u = {
  1162. .ablkcipher = {
  1163. .min_keysize = AES_MIN_KEY_SIZE,
  1164. .max_keysize = AES_MAX_KEY_SIZE,
  1165. .setkey = ablk_set_key,
  1166. .encrypt = ablk_encrypt,
  1167. .decrypt = ablk_decrypt,
  1168. },
  1169. },
  1170. }, {
  1171. .cra_name = "cbc(aes)",
  1172. .cra_driver_name = "cbc-aes-aesni",
  1173. .cra_priority = 400,
  1174. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1175. .cra_blocksize = AES_BLOCK_SIZE,
  1176. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1177. .cra_alignmask = 0,
  1178. .cra_type = &crypto_ablkcipher_type,
  1179. .cra_module = THIS_MODULE,
  1180. .cra_init = ablk_cbc_init,
  1181. .cra_exit = ablk_exit,
  1182. .cra_u = {
  1183. .ablkcipher = {
  1184. .min_keysize = AES_MIN_KEY_SIZE,
  1185. .max_keysize = AES_MAX_KEY_SIZE,
  1186. .ivsize = AES_BLOCK_SIZE,
  1187. .setkey = ablk_set_key,
  1188. .encrypt = ablk_encrypt,
  1189. .decrypt = ablk_decrypt,
  1190. },
  1191. },
  1192. #ifdef CONFIG_X86_64
  1193. }, {
  1194. .cra_name = "__ctr-aes-aesni",
  1195. .cra_driver_name = "__driver-ctr-aes-aesni",
  1196. .cra_priority = 0,
  1197. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1198. CRYPTO_ALG_INTERNAL,
  1199. .cra_blocksize = 1,
  1200. .cra_ctxsize = sizeof(struct crypto_aes_ctx) +
  1201. AESNI_ALIGN - 1,
  1202. .cra_alignmask = 0,
  1203. .cra_type = &crypto_blkcipher_type,
  1204. .cra_module = THIS_MODULE,
  1205. .cra_u = {
  1206. .blkcipher = {
  1207. .min_keysize = AES_MIN_KEY_SIZE,
  1208. .max_keysize = AES_MAX_KEY_SIZE,
  1209. .ivsize = AES_BLOCK_SIZE,
  1210. .setkey = aes_set_key,
  1211. .encrypt = ctr_crypt,
  1212. .decrypt = ctr_crypt,
  1213. },
  1214. },
  1215. }, {
  1216. .cra_name = "ctr(aes)",
  1217. .cra_driver_name = "ctr-aes-aesni",
  1218. .cra_priority = 400,
  1219. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1220. .cra_blocksize = 1,
  1221. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1222. .cra_alignmask = 0,
  1223. .cra_type = &crypto_ablkcipher_type,
  1224. .cra_module = THIS_MODULE,
  1225. .cra_init = ablk_ctr_init,
  1226. .cra_exit = ablk_exit,
  1227. .cra_u = {
  1228. .ablkcipher = {
  1229. .min_keysize = AES_MIN_KEY_SIZE,
  1230. .max_keysize = AES_MAX_KEY_SIZE,
  1231. .ivsize = AES_BLOCK_SIZE,
  1232. .setkey = ablk_set_key,
  1233. .encrypt = ablk_encrypt,
  1234. .decrypt = ablk_encrypt,
  1235. .geniv = "chainiv",
  1236. },
  1237. },
  1238. }, {
  1239. .cra_name = "__gcm-aes-aesni",
  1240. .cra_driver_name = "__driver-gcm-aes-aesni",
  1241. .cra_priority = 0,
  1242. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_INTERNAL,
  1243. .cra_blocksize = 1,
  1244. .cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) +
  1245. AESNI_ALIGN,
  1246. .cra_alignmask = 0,
  1247. .cra_type = &crypto_aead_type,
  1248. .cra_module = THIS_MODULE,
  1249. .cra_u = {
  1250. .aead = {
  1251. .setkey = common_rfc4106_set_key,
  1252. .setauthsize = common_rfc4106_set_authsize,
  1253. .encrypt = helper_rfc4106_encrypt,
  1254. .decrypt = helper_rfc4106_decrypt,
  1255. .ivsize = 8,
  1256. .maxauthsize = 16,
  1257. },
  1258. },
  1259. }, {
  1260. .cra_name = "rfc4106(gcm(aes))",
  1261. .cra_driver_name = "rfc4106-gcm-aesni",
  1262. .cra_priority = 400,
  1263. .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
  1264. .cra_blocksize = 1,
  1265. .cra_ctxsize = sizeof(struct aesni_rfc4106_gcm_ctx) +
  1266. AESNI_ALIGN,
  1267. .cra_alignmask = 0,
  1268. .cra_type = &crypto_nivaead_type,
  1269. .cra_module = THIS_MODULE,
  1270. .cra_init = rfc4106_init,
  1271. .cra_exit = rfc4106_exit,
  1272. .cra_u = {
  1273. .aead = {
  1274. .setkey = rfc4106_set_key,
  1275. .setauthsize = rfc4106_set_authsize,
  1276. .encrypt = rfc4106_encrypt,
  1277. .decrypt = rfc4106_decrypt,
  1278. .geniv = "seqiv",
  1279. .ivsize = 8,
  1280. .maxauthsize = 16,
  1281. },
  1282. },
  1283. #endif
  1284. #if IS_ENABLED(CONFIG_CRYPTO_PCBC)
  1285. }, {
  1286. .cra_name = "pcbc(aes)",
  1287. .cra_driver_name = "pcbc-aes-aesni",
  1288. .cra_priority = 400,
  1289. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1290. .cra_blocksize = AES_BLOCK_SIZE,
  1291. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1292. .cra_alignmask = 0,
  1293. .cra_type = &crypto_ablkcipher_type,
  1294. .cra_module = THIS_MODULE,
  1295. .cra_init = ablk_pcbc_init,
  1296. .cra_exit = ablk_exit,
  1297. .cra_u = {
  1298. .ablkcipher = {
  1299. .min_keysize = AES_MIN_KEY_SIZE,
  1300. .max_keysize = AES_MAX_KEY_SIZE,
  1301. .ivsize = AES_BLOCK_SIZE,
  1302. .setkey = ablk_set_key,
  1303. .encrypt = ablk_encrypt,
  1304. .decrypt = ablk_decrypt,
  1305. },
  1306. },
  1307. #endif
  1308. }, {
  1309. .cra_name = "__lrw-aes-aesni",
  1310. .cra_driver_name = "__driver-lrw-aes-aesni",
  1311. .cra_priority = 0,
  1312. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1313. CRYPTO_ALG_INTERNAL,
  1314. .cra_blocksize = AES_BLOCK_SIZE,
  1315. .cra_ctxsize = sizeof(struct aesni_lrw_ctx),
  1316. .cra_alignmask = 0,
  1317. .cra_type = &crypto_blkcipher_type,
  1318. .cra_module = THIS_MODULE,
  1319. .cra_exit = lrw_aesni_exit_tfm,
  1320. .cra_u = {
  1321. .blkcipher = {
  1322. .min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
  1323. .max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
  1324. .ivsize = AES_BLOCK_SIZE,
  1325. .setkey = lrw_aesni_setkey,
  1326. .encrypt = lrw_encrypt,
  1327. .decrypt = lrw_decrypt,
  1328. },
  1329. },
  1330. }, {
  1331. .cra_name = "__xts-aes-aesni",
  1332. .cra_driver_name = "__driver-xts-aes-aesni",
  1333. .cra_priority = 0,
  1334. .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER |
  1335. CRYPTO_ALG_INTERNAL,
  1336. .cra_blocksize = AES_BLOCK_SIZE,
  1337. .cra_ctxsize = sizeof(struct aesni_xts_ctx),
  1338. .cra_alignmask = 0,
  1339. .cra_type = &crypto_blkcipher_type,
  1340. .cra_module = THIS_MODULE,
  1341. .cra_u = {
  1342. .blkcipher = {
  1343. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1344. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1345. .ivsize = AES_BLOCK_SIZE,
  1346. .setkey = xts_aesni_setkey,
  1347. .encrypt = xts_encrypt,
  1348. .decrypt = xts_decrypt,
  1349. },
  1350. },
  1351. }, {
  1352. .cra_name = "lrw(aes)",
  1353. .cra_driver_name = "lrw-aes-aesni",
  1354. .cra_priority = 400,
  1355. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1356. .cra_blocksize = AES_BLOCK_SIZE,
  1357. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1358. .cra_alignmask = 0,
  1359. .cra_type = &crypto_ablkcipher_type,
  1360. .cra_module = THIS_MODULE,
  1361. .cra_init = ablk_init,
  1362. .cra_exit = ablk_exit,
  1363. .cra_u = {
  1364. .ablkcipher = {
  1365. .min_keysize = AES_MIN_KEY_SIZE + AES_BLOCK_SIZE,
  1366. .max_keysize = AES_MAX_KEY_SIZE + AES_BLOCK_SIZE,
  1367. .ivsize = AES_BLOCK_SIZE,
  1368. .setkey = ablk_set_key,
  1369. .encrypt = ablk_encrypt,
  1370. .decrypt = ablk_decrypt,
  1371. },
  1372. },
  1373. }, {
  1374. .cra_name = "xts(aes)",
  1375. .cra_driver_name = "xts-aes-aesni",
  1376. .cra_priority = 400,
  1377. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  1378. .cra_blocksize = AES_BLOCK_SIZE,
  1379. .cra_ctxsize = sizeof(struct async_helper_ctx),
  1380. .cra_alignmask = 0,
  1381. .cra_type = &crypto_ablkcipher_type,
  1382. .cra_module = THIS_MODULE,
  1383. .cra_init = ablk_init,
  1384. .cra_exit = ablk_exit,
  1385. .cra_u = {
  1386. .ablkcipher = {
  1387. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  1388. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  1389. .ivsize = AES_BLOCK_SIZE,
  1390. .setkey = ablk_set_key,
  1391. .encrypt = ablk_encrypt,
  1392. .decrypt = ablk_decrypt,
  1393. },
  1394. },
  1395. } };
  1396. static const struct x86_cpu_id aesni_cpu_id[] = {
  1397. X86_FEATURE_MATCH(X86_FEATURE_AES),
  1398. {}
  1399. };
  1400. MODULE_DEVICE_TABLE(x86cpu, aesni_cpu_id);
  1401. static int __init aesni_init(void)
  1402. {
  1403. int err;
  1404. if (!x86_match_cpu(aesni_cpu_id))
  1405. return -ENODEV;
  1406. #ifdef CONFIG_X86_64
  1407. #ifdef CONFIG_AS_AVX2
  1408. if (boot_cpu_has(X86_FEATURE_AVX2)) {
  1409. pr_info("AVX2 version of gcm_enc/dec engaged.\n");
  1410. aesni_gcm_enc_tfm = aesni_gcm_enc_avx2;
  1411. aesni_gcm_dec_tfm = aesni_gcm_dec_avx2;
  1412. } else
  1413. #endif
  1414. #ifdef CONFIG_AS_AVX
  1415. if (boot_cpu_has(X86_FEATURE_AVX)) {
  1416. pr_info("AVX version of gcm_enc/dec engaged.\n");
  1417. aesni_gcm_enc_tfm = aesni_gcm_enc_avx;
  1418. aesni_gcm_dec_tfm = aesni_gcm_dec_avx;
  1419. } else
  1420. #endif
  1421. {
  1422. pr_info("SSE version of gcm_enc/dec engaged.\n");
  1423. aesni_gcm_enc_tfm = aesni_gcm_enc;
  1424. aesni_gcm_dec_tfm = aesni_gcm_dec;
  1425. }
  1426. aesni_ctr_enc_tfm = aesni_ctr_enc;
  1427. #ifdef CONFIG_AS_AVX
  1428. if (cpu_has_avx) {
  1429. /* optimize performance of ctr mode encryption transform */
  1430. aesni_ctr_enc_tfm = aesni_ctr_enc_avx_tfm;
  1431. pr_info("AES CTR mode by8 optimization enabled\n");
  1432. }
  1433. #endif
  1434. #endif
  1435. err = crypto_fpu_init();
  1436. if (err)
  1437. return err;
  1438. return crypto_register_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1439. }
  1440. static void __exit aesni_exit(void)
  1441. {
  1442. crypto_unregister_algs(aesni_algs, ARRAY_SIZE(aesni_algs));
  1443. crypto_fpu_exit();
  1444. }
  1445. module_init(aesni_init);
  1446. module_exit(aesni_exit);
  1447. MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm, Intel AES-NI instructions optimized");
  1448. MODULE_LICENSE("GPL");
  1449. MODULE_ALIAS_CRYPTO("aes");