anatop.c 4.2 KB

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  1. /*
  2. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/of.h>
  14. #include <linux/of_address.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/regmap.h>
  17. #include "common.h"
  18. #include "hardware.h"
  19. #define REG_SET 0x4
  20. #define REG_CLR 0x8
  21. #define ANADIG_REG_2P5 0x130
  22. #define ANADIG_REG_CORE 0x140
  23. #define ANADIG_ANA_MISC0 0x150
  24. #define ANADIG_USB1_CHRG_DETECT 0x1b0
  25. #define ANADIG_USB2_CHRG_DETECT 0x210
  26. #define ANADIG_DIGPROG 0x260
  27. #define ANADIG_DIGPROG_IMX6SL 0x280
  28. #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
  29. #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
  30. #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
  31. #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
  32. /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
  33. #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
  34. #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
  35. #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
  36. static struct regmap *anatop;
  37. static void imx_anatop_enable_weak2p5(bool enable)
  38. {
  39. u32 reg, val;
  40. regmap_read(anatop, ANADIG_ANA_MISC0, &val);
  41. /* can only be enabled when stop_mode_config is clear. */
  42. reg = ANADIG_REG_2P5;
  43. reg += (enable && (val & BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
  44. REG_SET : REG_CLR;
  45. regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
  46. }
  47. static void imx_anatop_enable_fet_odrive(bool enable)
  48. {
  49. regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
  50. BM_ANADIG_REG_CORE_FET_ODRIVE);
  51. }
  52. static inline void imx_anatop_enable_2p5_pulldown(bool enable)
  53. {
  54. regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
  55. BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
  56. }
  57. static inline void imx_anatop_disconnect_high_snvs(bool enable)
  58. {
  59. regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
  60. BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
  61. }
  62. void imx_anatop_pre_suspend(void)
  63. {
  64. if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
  65. imx_anatop_enable_2p5_pulldown(true);
  66. else
  67. imx_anatop_enable_weak2p5(true);
  68. imx_anatop_enable_fet_odrive(true);
  69. if (cpu_is_imx6sl())
  70. imx_anatop_disconnect_high_snvs(true);
  71. }
  72. void imx_anatop_post_resume(void)
  73. {
  74. if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
  75. imx_anatop_enable_2p5_pulldown(false);
  76. else
  77. imx_anatop_enable_weak2p5(false);
  78. imx_anatop_enable_fet_odrive(false);
  79. if (cpu_is_imx6sl())
  80. imx_anatop_disconnect_high_snvs(false);
  81. }
  82. static void imx_anatop_usb_chrg_detect_disable(void)
  83. {
  84. regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
  85. BM_ANADIG_USB_CHRG_DETECT_EN_B
  86. | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
  87. regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
  88. BM_ANADIG_USB_CHRG_DETECT_EN_B |
  89. BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
  90. }
  91. void __init imx_init_revision_from_anatop(void)
  92. {
  93. struct device_node *np;
  94. void __iomem *anatop_base;
  95. unsigned int revision;
  96. u32 digprog;
  97. u16 offset = ANADIG_DIGPROG;
  98. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
  99. anatop_base = of_iomap(np, 0);
  100. WARN_ON(!anatop_base);
  101. if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
  102. offset = ANADIG_DIGPROG_IMX6SL;
  103. digprog = readl_relaxed(anatop_base + offset);
  104. iounmap(anatop_base);
  105. switch (digprog & 0xff) {
  106. case 0:
  107. revision = IMX_CHIP_REVISION_1_0;
  108. break;
  109. case 1:
  110. revision = IMX_CHIP_REVISION_1_1;
  111. break;
  112. case 2:
  113. revision = IMX_CHIP_REVISION_1_2;
  114. break;
  115. case 3:
  116. revision = IMX_CHIP_REVISION_1_3;
  117. break;
  118. case 4:
  119. revision = IMX_CHIP_REVISION_1_4;
  120. break;
  121. case 5:
  122. /*
  123. * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
  124. * as 'D' in Part Number last character.
  125. */
  126. revision = IMX_CHIP_REVISION_1_5;
  127. break;
  128. default:
  129. revision = IMX_CHIP_REVISION_UNKNOWN;
  130. }
  131. mxc_set_cpu_type(digprog >> 16 & 0xff);
  132. imx_set_soc_revision(revision);
  133. }
  134. void __init imx_anatop_init(void)
  135. {
  136. anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
  137. if (IS_ERR(anatop)) {
  138. pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
  139. return;
  140. }
  141. imx_anatop_usb_chrg_detect_disable();
  142. }