spi-fsl-lib.c 4.4 KB

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  1. /*
  2. * Freescale SPI/eSPI controller driver library.
  3. *
  4. * Maintainer: Kumar Gala
  5. *
  6. * Copyright (C) 2006 Polycom, Inc.
  7. *
  8. * CPM SPI and QE buffer descriptors mode support:
  9. * Copyright (c) 2009 MontaVista Software, Inc.
  10. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * Copyright 2010 Freescale Semiconductor, Inc.
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. */
  19. #include <linux/dma-mapping.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/kernel.h>
  23. #include <linux/mm.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/spi/spi.h>
  26. #ifdef CONFIG_FSL_SOC
  27. #include <sysdev/fsl_soc.h>
  28. #endif
  29. #include "spi-fsl-lib.h"
  30. #define MPC8XXX_SPI_RX_BUF(type) \
  31. void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
  32. { \
  33. type *rx = mpc8xxx_spi->rx; \
  34. *rx++ = (type)(data >> mpc8xxx_spi->rx_shift); \
  35. mpc8xxx_spi->rx = rx; \
  36. }
  37. #define MPC8XXX_SPI_TX_BUF(type) \
  38. u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
  39. { \
  40. u32 data; \
  41. const type *tx = mpc8xxx_spi->tx; \
  42. if (!tx) \
  43. return 0; \
  44. data = *tx++ << mpc8xxx_spi->tx_shift; \
  45. mpc8xxx_spi->tx = tx; \
  46. return data; \
  47. }
  48. MPC8XXX_SPI_RX_BUF(u8)
  49. MPC8XXX_SPI_RX_BUF(u16)
  50. MPC8XXX_SPI_RX_BUF(u32)
  51. MPC8XXX_SPI_TX_BUF(u8)
  52. MPC8XXX_SPI_TX_BUF(u16)
  53. MPC8XXX_SPI_TX_BUF(u32)
  54. struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
  55. {
  56. return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
  57. }
  58. const char *mpc8xxx_spi_strmode(unsigned int flags)
  59. {
  60. if (flags & SPI_QE_CPU_MODE) {
  61. return "QE CPU";
  62. } else if (flags & SPI_CPM_MODE) {
  63. if (flags & SPI_QE)
  64. return "QE";
  65. else if (flags & SPI_CPM2)
  66. return "CPM2";
  67. else
  68. return "CPM1";
  69. }
  70. return "CPU";
  71. }
  72. void mpc8xxx_spi_probe(struct device *dev, struct resource *mem,
  73. unsigned int irq)
  74. {
  75. struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
  76. struct spi_master *master;
  77. struct mpc8xxx_spi *mpc8xxx_spi;
  78. master = dev_get_drvdata(dev);
  79. /* the spi->mode bits understood by this driver: */
  80. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH
  81. | SPI_LSB_FIRST | SPI_LOOP;
  82. master->dev.of_node = dev->of_node;
  83. mpc8xxx_spi = spi_master_get_devdata(master);
  84. mpc8xxx_spi->dev = dev;
  85. mpc8xxx_spi->get_rx = mpc8xxx_spi_rx_buf_u8;
  86. mpc8xxx_spi->get_tx = mpc8xxx_spi_tx_buf_u8;
  87. mpc8xxx_spi->flags = pdata->flags;
  88. mpc8xxx_spi->spibrg = pdata->sysclk;
  89. mpc8xxx_spi->irq = irq;
  90. mpc8xxx_spi->rx_shift = 0;
  91. mpc8xxx_spi->tx_shift = 0;
  92. init_completion(&mpc8xxx_spi->done);
  93. master->bus_num = pdata->bus_num;
  94. master->num_chipselect = pdata->max_chipselect;
  95. init_completion(&mpc8xxx_spi->done);
  96. }
  97. int mpc8xxx_spi_remove(struct device *dev)
  98. {
  99. struct mpc8xxx_spi *mpc8xxx_spi;
  100. struct spi_master *master;
  101. master = dev_get_drvdata(dev);
  102. mpc8xxx_spi = spi_master_get_devdata(master);
  103. spi_unregister_master(master);
  104. free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
  105. if (mpc8xxx_spi->spi_remove)
  106. mpc8xxx_spi->spi_remove(mpc8xxx_spi);
  107. return 0;
  108. }
  109. int of_mpc8xxx_spi_probe(struct platform_device *ofdev)
  110. {
  111. struct device *dev = &ofdev->dev;
  112. struct device_node *np = ofdev->dev.of_node;
  113. struct mpc8xxx_spi_probe_info *pinfo;
  114. struct fsl_spi_platform_data *pdata;
  115. const void *prop;
  116. int ret = -ENOMEM;
  117. pinfo = devm_kzalloc(&ofdev->dev, sizeof(*pinfo), GFP_KERNEL);
  118. if (!pinfo)
  119. return ret;
  120. pdata = &pinfo->pdata;
  121. dev->platform_data = pdata;
  122. /* Allocate bus num dynamically. */
  123. pdata->bus_num = -1;
  124. #ifdef CONFIG_FSL_SOC
  125. /* SPI controller is either clocked from QE or SoC clock. */
  126. pdata->sysclk = get_brgfreq();
  127. if (pdata->sysclk == -1) {
  128. pdata->sysclk = fsl_get_sys_freq();
  129. if (pdata->sysclk == -1)
  130. return -ENODEV;
  131. }
  132. #else
  133. ret = of_property_read_u32(np, "clock-frequency", &pdata->sysclk);
  134. if (ret)
  135. return ret;
  136. #endif
  137. prop = of_get_property(np, "mode", NULL);
  138. if (prop && !strcmp(prop, "cpu-qe"))
  139. pdata->flags = SPI_QE_CPU_MODE;
  140. else if (prop && !strcmp(prop, "qe"))
  141. pdata->flags = SPI_CPM_MODE | SPI_QE;
  142. else if (of_device_is_compatible(np, "fsl,cpm2-spi"))
  143. pdata->flags = SPI_CPM_MODE | SPI_CPM2;
  144. else if (of_device_is_compatible(np, "fsl,cpm1-spi"))
  145. pdata->flags = SPI_CPM_MODE | SPI_CPM1;
  146. return 0;
  147. }