dal_asic_id.h 4.2 KB

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  1. /*
  2. * Copyright 2012-15 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: AMD
  23. *
  24. */
  25. #ifndef __DAL_ASIC_ID_H__
  26. #define __DAL_ASIC_ID_H__
  27. /*
  28. * ASIC internal revision ID
  29. */
  30. /* DCE80 (based on ci_id.h in Perforce) */
  31. #define CI_BONAIRE_M_A0 0x14
  32. #define CI_BONAIRE_M_A1 0x15
  33. #define CI_HAWAII_P_A0 0x28
  34. #define CI_UNKNOWN 0xFF
  35. #define ASIC_REV_IS_BONAIRE_M(rev) \
  36. ((rev >= CI_BONAIRE_M_A0) && (rev < CI_HAWAII_P_A0))
  37. #define ASIC_REV_IS_HAWAII_P(rev) \
  38. (rev >= CI_HAWAII_P_A0)
  39. /* KV1 with Spectre GFX core, 8-8-1-2 (CU-Pix-Primitive-RB) */
  40. #define KV_SPECTRE_A0 0x01
  41. /* KV2 with Spooky GFX core, including downgraded from Spectre core,
  42. * 3-4-1-1 (CU-Pix-Primitive-RB) */
  43. #define KV_SPOOKY_A0 0x41
  44. /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
  45. #define KB_KALINDI_A0 0x81
  46. /* KB with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
  47. #define KB_KALINDI_A1 0x82
  48. /* BV with Kalindi GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
  49. #define BV_KALINDI_A2 0x85
  50. /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
  51. #define ML_GODAVARI_A0 0xA1
  52. /* ML with Godavari GFX core, 2-4-1-1 (CU-Pix-Primitive-RB) */
  53. #define ML_GODAVARI_A1 0xA2
  54. #define KV_UNKNOWN 0xFF
  55. #define ASIC_REV_IS_KALINDI(rev) \
  56. ((rev >= KB_KALINDI_A0) && (rev < KV_UNKNOWN))
  57. #define ASIC_REV_IS_BHAVANI(rev) \
  58. ((rev >= BV_KALINDI_A2) && (rev < ML_GODAVARI_A0))
  59. #define ASIC_REV_IS_GODAVARI(rev) \
  60. ((rev >= ML_GODAVARI_A0) && (rev < KV_UNKNOWN))
  61. /* VI Family */
  62. /* DCE10 */
  63. #define VI_TONGA_P_A0 20
  64. #define VI_TONGA_P_A1 21
  65. #define VI_FIJI_P_A0 60
  66. /* DCE112 */
  67. #define VI_POLARIS10_P_A0 80
  68. #define VI_POLARIS11_M_A0 90
  69. #define VI_POLARIS12_V_A0 100
  70. #define VI_UNKNOWN 0xFF
  71. #define ASIC_REV_IS_TONGA_P(eChipRev) ((eChipRev >= VI_TONGA_P_A0) && \
  72. (eChipRev < 40))
  73. #define ASIC_REV_IS_FIJI_P(eChipRev) ((eChipRev >= VI_FIJI_P_A0) && \
  74. (eChipRev < 80))
  75. #define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \
  76. (eChipRev < VI_POLARIS11_M_A0))
  77. #define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \
  78. (eChipRev < VI_POLARIS12_V_A0))
  79. #define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0)
  80. /* DCE11 */
  81. #define CZ_CARRIZO_A0 0x01
  82. #define STONEY_A0 0x61
  83. #define CZ_UNKNOWN 0xFF
  84. #define ASIC_REV_IS_STONEY(rev) \
  85. ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN))
  86. /* DCN1_0 */
  87. #define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
  88. #define RAVEN_A0 0x01
  89. #define RAVEN_B0 0x21
  90. #define RAVEN_UNKNOWN 0xFF
  91. #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
  92. #define RAVEN1_F0 0xF0
  93. #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
  94. #define FAMILY_RV 142 /* DCN 1*/
  95. /*
  96. * ASIC chip ID
  97. */
  98. /* DCE80 */
  99. #define DEVICE_ID_KALINDI_9834 0x9834
  100. #define DEVICE_ID_TEMASH_9839 0x9839
  101. #define DEVICE_ID_TEMASH_983D 0x983D
  102. /* Asic Family IDs for different asic family. */
  103. #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */
  104. #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */
  105. #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */
  106. #define FAMILY_CZ 135 /* Carrizo */
  107. #define FAMILY_AI 141
  108. #define FAMILY_UNKNOWN 0xFF
  109. #endif /* __DAL_ASIC_ID_H__ */