pci-keystone.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe host controller driver for Texas Instruments Keystone SoCs
  4. *
  5. * Copyright (C) 2013-2014 Texas Instruments., Ltd.
  6. * http://www.ti.com
  7. *
  8. * Author: Murali Karicheri <m-karicheri2@ti.com>
  9. * Implementation based on pci-exynos.c and pcie-designware.c
  10. */
  11. #include <linux/irqchip/chained_irq.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/init.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/msi.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of.h>
  21. #include <linux/of_pci.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/phy/phy.h>
  24. #include <linux/regmap.h>
  25. #include <linux/resource.h>
  26. #include <linux/signal.h>
  27. #include "pcie-designware.h"
  28. #define DRIVER_NAME "keystone-pcie"
  29. #define PCIE_VENDORID_MASK 0xffff
  30. #define PCIE_DEVICEID_SHIFT 16
  31. /* DEV_STAT_CTRL */
  32. #define PCIE_CAP_BASE 0x70
  33. /* Application register defines */
  34. #define LTSSM_EN_VAL BIT(0)
  35. #define LTSSM_STATE_MASK 0x1f
  36. #define LTSSM_STATE_L0 0x11
  37. #define DBI_CS2_EN_VAL 0x20
  38. #define OB_XLAT_EN_VAL 2
  39. /* Application registers */
  40. #define CMD_STATUS 0x004
  41. #define CFG_SETUP 0x008
  42. #define CFG_BUS(x) (((x) & 0xff) << 16)
  43. #define CFG_DEVICE(x) (((x) & 0x1f) << 8)
  44. #define CFG_FUNC(x) ((x) & 0x7)
  45. #define CFG_TYPE1 BIT(24)
  46. #define OB_SIZE 0x030
  47. #define CFG_PCIM_WIN_SZ_IDX 3
  48. #define SPACE0_REMOTE_CFG_OFFSET 0x1000
  49. #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n)))
  50. #define OB_OFFSET_HI(n) (0x204 + (8 * (n)))
  51. /* IRQ register defines */
  52. #define IRQ_EOI 0x050
  53. #define IRQ_STATUS 0x184
  54. #define IRQ_ENABLE_SET 0x188
  55. #define IRQ_ENABLE_CLR 0x18c
  56. #define MSI_IRQ 0x054
  57. #define MSI0_IRQ_STATUS 0x104
  58. #define MSI0_IRQ_ENABLE_SET 0x108
  59. #define MSI0_IRQ_ENABLE_CLR 0x10c
  60. #define IRQ_STATUS 0x184
  61. #define MSI_IRQ_OFFSET 4
  62. /* Error IRQ bits */
  63. #define ERR_AER BIT(5) /* ECRC error */
  64. #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */
  65. #define ERR_CORR BIT(3) /* Correctable error */
  66. #define ERR_NONFATAL BIT(2) /* Non-fatal error */
  67. #define ERR_FATAL BIT(1) /* Fatal error */
  68. #define ERR_SYS BIT(0) /* System (fatal, non-fatal, or correctable) */
  69. #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \
  70. ERR_NONFATAL | ERR_FATAL | ERR_SYS)
  71. #define ERR_FATAL_IRQ (ERR_FATAL | ERR_AXI)
  72. #define ERR_IRQ_STATUS_RAW 0x1c0
  73. #define ERR_IRQ_STATUS 0x1c4
  74. #define ERR_IRQ_ENABLE_SET 0x1c8
  75. #define ERR_IRQ_ENABLE_CLR 0x1cc
  76. /* Config space registers */
  77. #define DEBUG0 0x728
  78. #define MAX_MSI_HOST_IRQS 8
  79. /* PCIE controller device IDs */
  80. #define PCIE_RC_K2HK 0xb008
  81. #define PCIE_RC_K2E 0xb009
  82. #define PCIE_RC_K2L 0xb00a
  83. #define PCIE_RC_K2G 0xb00b
  84. #define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
  85. struct keystone_pcie {
  86. struct dw_pcie *pci;
  87. /* PCI Device ID */
  88. u32 device_id;
  89. int num_legacy_host_irqs;
  90. int legacy_host_irqs[PCI_NUM_INTX];
  91. struct device_node *legacy_intc_np;
  92. int num_msi_host_irqs;
  93. int msi_host_irqs[MAX_MSI_HOST_IRQS];
  94. int num_lanes;
  95. u32 num_viewport;
  96. struct phy **phy;
  97. struct device_link **link;
  98. struct device_node *msi_intc_np;
  99. struct irq_domain *legacy_irq_domain;
  100. struct device_node *np;
  101. int error_irq;
  102. /* Application register space */
  103. void __iomem *va_app_base; /* DT 1st resource */
  104. struct resource app;
  105. };
  106. static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
  107. u32 *bit_pos)
  108. {
  109. *reg_offset = offset % 8;
  110. *bit_pos = offset >> 3;
  111. }
  112. static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp)
  113. {
  114. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  115. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  116. return ks_pcie->app.start + MSI_IRQ;
  117. }
  118. static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset)
  119. {
  120. return readl(ks_pcie->va_app_base + offset);
  121. }
  122. static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset,
  123. u32 val)
  124. {
  125. writel(val, ks_pcie->va_app_base + offset);
  126. }
  127. static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
  128. {
  129. struct dw_pcie *pci = ks_pcie->pci;
  130. struct pcie_port *pp = &pci->pp;
  131. struct device *dev = pci->dev;
  132. u32 pending, vector;
  133. int src, virq;
  134. pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4));
  135. /*
  136. * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
  137. * shows 1, 9, 17, 25 and so forth
  138. */
  139. for (src = 0; src < 4; src++) {
  140. if (BIT(src) & pending) {
  141. vector = offset + (src << 3);
  142. virq = irq_linear_revmap(pp->irq_domain, vector);
  143. dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n",
  144. src, vector, virq);
  145. generic_handle_irq(virq);
  146. }
  147. }
  148. }
  149. static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
  150. {
  151. u32 reg_offset, bit_pos;
  152. struct keystone_pcie *ks_pcie;
  153. struct dw_pcie *pci;
  154. pci = to_dw_pcie_from_pp(pp);
  155. ks_pcie = to_keystone_pcie(pci);
  156. update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
  157. ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
  158. BIT(bit_pos));
  159. ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET);
  160. }
  161. static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq)
  162. {
  163. u32 reg_offset, bit_pos;
  164. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  165. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  166. update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
  167. ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
  168. BIT(bit_pos));
  169. }
  170. static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
  171. {
  172. u32 reg_offset, bit_pos;
  173. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  174. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  175. update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
  176. ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
  177. BIT(bit_pos));
  178. }
  179. static int ks_pcie_msi_host_init(struct pcie_port *pp)
  180. {
  181. return dw_pcie_allocate_domains(pp);
  182. }
  183. static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
  184. {
  185. int i;
  186. for (i = 0; i < PCI_NUM_INTX; i++)
  187. ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1);
  188. }
  189. static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
  190. int offset)
  191. {
  192. struct dw_pcie *pci = ks_pcie->pci;
  193. struct device *dev = pci->dev;
  194. u32 pending;
  195. int virq;
  196. pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4));
  197. if (BIT(0) & pending) {
  198. virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
  199. dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
  200. generic_handle_irq(virq);
  201. }
  202. /* EOI the INTx interrupt */
  203. ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
  204. }
  205. static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie)
  206. {
  207. ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL);
  208. }
  209. static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
  210. {
  211. u32 status;
  212. status = ks_pcie_app_readl(ks_pcie, ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL;
  213. if (!status)
  214. return IRQ_NONE;
  215. if (status & ERR_FATAL_IRQ)
  216. dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
  217. status);
  218. /* Ack the IRQ; status bits are RW1C */
  219. ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, status);
  220. return IRQ_HANDLED;
  221. }
  222. static void ks_pcie_ack_legacy_irq(struct irq_data *d)
  223. {
  224. }
  225. static void ks_pcie_mask_legacy_irq(struct irq_data *d)
  226. {
  227. }
  228. static void ks_pcie_unmask_legacy_irq(struct irq_data *d)
  229. {
  230. }
  231. static struct irq_chip ks_pcie_legacy_irq_chip = {
  232. .name = "Keystone-PCI-Legacy-IRQ",
  233. .irq_ack = ks_pcie_ack_legacy_irq,
  234. .irq_mask = ks_pcie_mask_legacy_irq,
  235. .irq_unmask = ks_pcie_unmask_legacy_irq,
  236. };
  237. static int ks_pcie_init_legacy_irq_map(struct irq_domain *d,
  238. unsigned int irq,
  239. irq_hw_number_t hw_irq)
  240. {
  241. irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip,
  242. handle_level_irq);
  243. irq_set_chip_data(irq, d->host_data);
  244. return 0;
  245. }
  246. static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = {
  247. .map = ks_pcie_init_legacy_irq_map,
  248. .xlate = irq_domain_xlate_onetwocell,
  249. };
  250. /**
  251. * ks_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
  252. * registers
  253. *
  254. * Since modification of dbi_cs2 involves different clock domain, read the
  255. * status back to ensure the transition is complete.
  256. */
  257. static void ks_pcie_set_dbi_mode(struct keystone_pcie *ks_pcie)
  258. {
  259. u32 val;
  260. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  261. ks_pcie_app_writel(ks_pcie, CMD_STATUS, DBI_CS2_EN_VAL | val);
  262. do {
  263. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  264. } while (!(val & DBI_CS2_EN_VAL));
  265. }
  266. /**
  267. * ks_pcie_clear_dbi_mode() - Disable DBI mode
  268. *
  269. * Since modification of dbi_cs2 involves different clock domain, read the
  270. * status back to ensure the transition is complete.
  271. */
  272. static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
  273. {
  274. u32 val;
  275. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  276. ks_pcie_app_writel(ks_pcie, CMD_STATUS, ~DBI_CS2_EN_VAL & val);
  277. do {
  278. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  279. } while (val & DBI_CS2_EN_VAL);
  280. }
  281. static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
  282. {
  283. u32 num_viewport = ks_pcie->num_viewport;
  284. struct dw_pcie *pci = ks_pcie->pci;
  285. struct pcie_port *pp = &pci->pp;
  286. u32 start = pp->mem->start, end = pp->mem->end;
  287. int i, tr_size;
  288. u32 val;
  289. /* Disable BARs for inbound access */
  290. ks_pcie_set_dbi_mode(ks_pcie);
  291. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
  292. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
  293. ks_pcie_clear_dbi_mode(ks_pcie);
  294. /* Set outbound translation size per window division */
  295. ks_pcie_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7);
  296. tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M;
  297. /* Using Direct 1:1 mapping of RC <-> PCI memory space */
  298. for (i = 0; (i < num_viewport) && (start < end); i++) {
  299. ks_pcie_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1);
  300. ks_pcie_app_writel(ks_pcie, OB_OFFSET_HI(i), 0);
  301. start += tr_size;
  302. }
  303. /* Enable OB translation */
  304. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  305. ks_pcie_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val);
  306. }
  307. static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
  308. unsigned int devfn, int where, int size,
  309. u32 *val)
  310. {
  311. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  312. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  313. u32 reg;
  314. reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
  315. CFG_FUNC(PCI_FUNC(devfn));
  316. if (bus->parent->number != pp->root_bus_nr)
  317. reg |= CFG_TYPE1;
  318. ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
  319. return dw_pcie_read(pp->va_cfg0_base + where, size, val);
  320. }
  321. static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
  322. unsigned int devfn, int where, int size,
  323. u32 val)
  324. {
  325. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  326. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  327. u32 reg;
  328. reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) |
  329. CFG_FUNC(PCI_FUNC(devfn));
  330. if (bus->parent->number != pp->root_bus_nr)
  331. reg |= CFG_TYPE1;
  332. ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg);
  333. return dw_pcie_write(pp->va_cfg0_base + where, size, val);
  334. }
  335. /**
  336. * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
  337. *
  338. * This sets BAR0 to enable inbound access for MSI_IRQ register
  339. */
  340. static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp)
  341. {
  342. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  343. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  344. /* Configure and set up BAR0 */
  345. ks_pcie_set_dbi_mode(ks_pcie);
  346. /* Enable BAR0 */
  347. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
  348. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
  349. ks_pcie_clear_dbi_mode(ks_pcie);
  350. /*
  351. * For BAR0, just setting bus address for inbound writes (MSI) should
  352. * be sufficient. Use physical address to avoid any conflicts.
  353. */
  354. dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
  355. }
  356. /**
  357. * ks_pcie_link_up() - Check if link up
  358. */
  359. static int ks_pcie_link_up(struct dw_pcie *pci)
  360. {
  361. u32 val;
  362. val = dw_pcie_readl_dbi(pci, DEBUG0);
  363. return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
  364. }
  365. static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
  366. {
  367. u32 val;
  368. /* Disable Link training */
  369. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  370. val &= ~LTSSM_EN_VAL;
  371. ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
  372. /* Initiate Link Training */
  373. val = ks_pcie_app_readl(ks_pcie, CMD_STATUS);
  374. ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val);
  375. }
  376. /**
  377. * ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware
  378. *
  379. * Ioremap the register resources, initialize legacy irq domain
  380. * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
  381. * PCI host controller.
  382. */
  383. static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie)
  384. {
  385. struct dw_pcie *pci = ks_pcie->pci;
  386. struct pcie_port *pp = &pci->pp;
  387. struct device *dev = pci->dev;
  388. struct platform_device *pdev = to_platform_device(dev);
  389. struct resource *res;
  390. /* Index 0 is the config reg. space address */
  391. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  392. pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
  393. if (IS_ERR(pci->dbi_base))
  394. return PTR_ERR(pci->dbi_base);
  395. /*
  396. * We set these same and is used in pcie rd/wr_other_conf
  397. * functions
  398. */
  399. pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
  400. pp->va_cfg1_base = pp->va_cfg0_base;
  401. /* Index 1 is the application reg. space address */
  402. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  403. ks_pcie->va_app_base = devm_ioremap_resource(dev, res);
  404. if (IS_ERR(ks_pcie->va_app_base))
  405. return PTR_ERR(ks_pcie->va_app_base);
  406. ks_pcie->app = *res;
  407. /* Create legacy IRQ domain */
  408. ks_pcie->legacy_irq_domain =
  409. irq_domain_add_linear(ks_pcie->legacy_intc_np,
  410. PCI_NUM_INTX,
  411. &ks_pcie_legacy_irq_domain_ops,
  412. NULL);
  413. if (!ks_pcie->legacy_irq_domain) {
  414. dev_err(dev, "Failed to add irq domain for legacy irqs\n");
  415. return -EINVAL;
  416. }
  417. return dw_pcie_host_init(pp);
  418. }
  419. static void ks_pcie_quirk(struct pci_dev *dev)
  420. {
  421. struct pci_bus *bus = dev->bus;
  422. struct pci_dev *bridge;
  423. static const struct pci_device_id rc_pci_devids[] = {
  424. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
  425. .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  426. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
  427. .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  428. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
  429. .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  430. { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
  431. .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  432. { 0, },
  433. };
  434. if (pci_is_root_bus(bus))
  435. bridge = dev;
  436. /* look for the host bridge */
  437. while (!pci_is_root_bus(bus)) {
  438. bridge = bus->self;
  439. bus = bus->parent;
  440. }
  441. if (!bridge)
  442. return;
  443. /*
  444. * Keystone PCI controller has a h/w limitation of
  445. * 256 bytes maximum read request size. It can't handle
  446. * anything higher than this. So force this limit on
  447. * all downstream devices.
  448. */
  449. if (pci_match_id(rc_pci_devids, bridge)) {
  450. if (pcie_get_readrq(dev) > 256) {
  451. dev_info(&dev->dev, "limiting MRRS to 256\n");
  452. pcie_set_readrq(dev, 256);
  453. }
  454. }
  455. }
  456. DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
  457. static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
  458. {
  459. struct dw_pcie *pci = ks_pcie->pci;
  460. struct device *dev = pci->dev;
  461. if (dw_pcie_link_up(pci)) {
  462. dev_info(dev, "Link already up\n");
  463. return 0;
  464. }
  465. ks_pcie_initiate_link_train(ks_pcie);
  466. /* check if the link is up or not */
  467. if (!dw_pcie_wait_for_link(pci))
  468. return 0;
  469. dev_err(dev, "phy link never came up\n");
  470. return -ETIMEDOUT;
  471. }
  472. static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
  473. {
  474. unsigned int irq = irq_desc_get_irq(desc);
  475. struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
  476. u32 offset = irq - ks_pcie->msi_host_irqs[0];
  477. struct dw_pcie *pci = ks_pcie->pci;
  478. struct device *dev = pci->dev;
  479. struct irq_chip *chip = irq_desc_get_chip(desc);
  480. dev_dbg(dev, "%s, irq %d\n", __func__, irq);
  481. /*
  482. * The chained irq handler installation would have replaced normal
  483. * interrupt driver handler so we need to take care of mask/unmask and
  484. * ack operation.
  485. */
  486. chained_irq_enter(chip, desc);
  487. ks_pcie_handle_msi_irq(ks_pcie, offset);
  488. chained_irq_exit(chip, desc);
  489. }
  490. /**
  491. * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
  492. * @irq: IRQ line for legacy interrupts
  493. * @desc: Pointer to irq descriptor
  494. *
  495. * Traverse through pending legacy interrupts and invoke handler for each. Also
  496. * takes care of interrupt controller level mask/ack operation.
  497. */
  498. static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
  499. {
  500. unsigned int irq = irq_desc_get_irq(desc);
  501. struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
  502. struct dw_pcie *pci = ks_pcie->pci;
  503. struct device *dev = pci->dev;
  504. u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
  505. struct irq_chip *chip = irq_desc_get_chip(desc);
  506. dev_dbg(dev, ": Handling legacy irq %d\n", irq);
  507. /*
  508. * The chained irq handler installation would have replaced normal
  509. * interrupt driver handler so we need to take care of mask/unmask and
  510. * ack operation.
  511. */
  512. chained_irq_enter(chip, desc);
  513. ks_pcie_handle_legacy_irq(ks_pcie, irq_offset);
  514. chained_irq_exit(chip, desc);
  515. }
  516. static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
  517. char *controller, int *num_irqs)
  518. {
  519. int temp, max_host_irqs, legacy = 1, *host_irqs;
  520. struct device *dev = ks_pcie->pci->dev;
  521. struct device_node *np_pcie = dev->of_node, **np_temp;
  522. if (!strcmp(controller, "msi-interrupt-controller"))
  523. legacy = 0;
  524. if (legacy) {
  525. np_temp = &ks_pcie->legacy_intc_np;
  526. max_host_irqs = PCI_NUM_INTX;
  527. host_irqs = &ks_pcie->legacy_host_irqs[0];
  528. } else {
  529. np_temp = &ks_pcie->msi_intc_np;
  530. max_host_irqs = MAX_MSI_HOST_IRQS;
  531. host_irqs = &ks_pcie->msi_host_irqs[0];
  532. }
  533. /* interrupt controller is in a child node */
  534. *np_temp = of_get_child_by_name(np_pcie, controller);
  535. if (!(*np_temp)) {
  536. dev_err(dev, "Node for %s is absent\n", controller);
  537. return -EINVAL;
  538. }
  539. temp = of_irq_count(*np_temp);
  540. if (!temp) {
  541. dev_err(dev, "No IRQ entries in %s\n", controller);
  542. of_node_put(*np_temp);
  543. return -EINVAL;
  544. }
  545. if (temp > max_host_irqs)
  546. dev_warn(dev, "Too many %s interrupts defined %u\n",
  547. (legacy ? "legacy" : "MSI"), temp);
  548. /*
  549. * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
  550. * 7 (MSI)
  551. */
  552. for (temp = 0; temp < max_host_irqs; temp++) {
  553. host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
  554. if (!host_irqs[temp])
  555. break;
  556. }
  557. of_node_put(*np_temp);
  558. if (temp) {
  559. *num_irqs = temp;
  560. return 0;
  561. }
  562. return -EINVAL;
  563. }
  564. static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
  565. {
  566. int i;
  567. /* Legacy IRQ */
  568. for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
  569. irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
  570. ks_pcie_legacy_irq_handler,
  571. ks_pcie);
  572. }
  573. ks_pcie_enable_legacy_irqs(ks_pcie);
  574. /* MSI IRQ */
  575. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  576. for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
  577. irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
  578. ks_pcie_msi_irq_handler,
  579. ks_pcie);
  580. }
  581. }
  582. if (ks_pcie->error_irq > 0)
  583. ks_pcie_enable_error_irq(ks_pcie);
  584. }
  585. /*
  586. * When a PCI device does not exist during config cycles, keystone host gets a
  587. * bus error instead of returning 0xffffffff. This handler always returns 0
  588. * for this kind of faults.
  589. */
  590. static int ks_pcie_fault(unsigned long addr, unsigned int fsr,
  591. struct pt_regs *regs)
  592. {
  593. unsigned long instr = *(unsigned long *) instruction_pointer(regs);
  594. if ((instr & 0x0e100090) == 0x00100090) {
  595. int reg = (instr >> 12) & 15;
  596. regs->uregs[reg] = -1;
  597. regs->ARM_pc += 4;
  598. }
  599. return 0;
  600. }
  601. static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie)
  602. {
  603. int ret;
  604. unsigned int id;
  605. struct regmap *devctrl_regs;
  606. struct dw_pcie *pci = ks_pcie->pci;
  607. struct device *dev = pci->dev;
  608. struct device_node *np = dev->of_node;
  609. devctrl_regs = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-id");
  610. if (IS_ERR(devctrl_regs))
  611. return PTR_ERR(devctrl_regs);
  612. ret = regmap_read(devctrl_regs, 0, &id);
  613. if (ret)
  614. return ret;
  615. dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK);
  616. dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT);
  617. return 0;
  618. }
  619. static int __init ks_pcie_host_init(struct pcie_port *pp)
  620. {
  621. struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
  622. struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
  623. int ret;
  624. dw_pcie_setup_rc(pp);
  625. ks_pcie_establish_link(ks_pcie);
  626. ks_pcie_setup_rc_app_regs(ks_pcie);
  627. ks_pcie_setup_interrupts(ks_pcie);
  628. writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
  629. pci->dbi_base + PCI_IO_BASE);
  630. ret = ks_pcie_init_id(ks_pcie);
  631. if (ret < 0)
  632. return ret;
  633. /*
  634. * PCIe access errors that result into OCP errors are caught by ARM as
  635. * "External aborts"
  636. */
  637. hook_fault_code(17, ks_pcie_fault, SIGBUS, 0,
  638. "Asynchronous external abort");
  639. return 0;
  640. }
  641. static const struct dw_pcie_host_ops ks_pcie_host_ops = {
  642. .rd_other_conf = ks_pcie_rd_other_conf,
  643. .wr_other_conf = ks_pcie_wr_other_conf,
  644. .host_init = ks_pcie_host_init,
  645. .msi_set_irq = ks_pcie_msi_set_irq,
  646. .msi_clear_irq = ks_pcie_msi_clear_irq,
  647. .get_msi_addr = ks_pcie_get_msi_addr,
  648. .msi_host_init = ks_pcie_msi_host_init,
  649. .msi_irq_ack = ks_pcie_msi_irq_ack,
  650. .scan_bus = ks_pcie_v3_65_scan_bus,
  651. };
  652. static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv)
  653. {
  654. struct keystone_pcie *ks_pcie = priv;
  655. return ks_pcie_handle_error_irq(ks_pcie);
  656. }
  657. static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie,
  658. struct platform_device *pdev)
  659. {
  660. struct dw_pcie *pci = ks_pcie->pci;
  661. struct pcie_port *pp = &pci->pp;
  662. struct device *dev = &pdev->dev;
  663. int ret;
  664. ret = ks_pcie_get_irq_controller_info(ks_pcie,
  665. "legacy-interrupt-controller",
  666. &ks_pcie->num_legacy_host_irqs);
  667. if (ret)
  668. return ret;
  669. if (IS_ENABLED(CONFIG_PCI_MSI)) {
  670. ret = ks_pcie_get_irq_controller_info(ks_pcie,
  671. "msi-interrupt-controller",
  672. &ks_pcie->num_msi_host_irqs);
  673. if (ret)
  674. return ret;
  675. }
  676. /*
  677. * Index 0 is the platform interrupt for error interrupt
  678. * from RC. This is optional.
  679. */
  680. ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
  681. if (ks_pcie->error_irq <= 0)
  682. dev_info(dev, "no error IRQ defined\n");
  683. else {
  684. ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler,
  685. IRQF_SHARED, "pcie-error-irq", ks_pcie);
  686. if (ret < 0) {
  687. dev_err(dev, "failed to request error IRQ %d\n",
  688. ks_pcie->error_irq);
  689. return ret;
  690. }
  691. }
  692. pp->ops = &ks_pcie_host_ops;
  693. ret = ks_pcie_dw_host_init(ks_pcie);
  694. if (ret) {
  695. dev_err(dev, "failed to initialize host\n");
  696. return ret;
  697. }
  698. return 0;
  699. }
  700. static const struct of_device_id ks_pcie_of_match[] = {
  701. {
  702. .type = "pci",
  703. .compatible = "ti,keystone-pcie",
  704. },
  705. { },
  706. };
  707. static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = {
  708. .link_up = ks_pcie_link_up,
  709. };
  710. static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie)
  711. {
  712. int num_lanes = ks_pcie->num_lanes;
  713. while (num_lanes--) {
  714. phy_power_off(ks_pcie->phy[num_lanes]);
  715. phy_exit(ks_pcie->phy[num_lanes]);
  716. }
  717. }
  718. static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie)
  719. {
  720. int i;
  721. int ret;
  722. int num_lanes = ks_pcie->num_lanes;
  723. for (i = 0; i < num_lanes; i++) {
  724. ret = phy_init(ks_pcie->phy[i]);
  725. if (ret < 0)
  726. goto err_phy;
  727. ret = phy_power_on(ks_pcie->phy[i]);
  728. if (ret < 0) {
  729. phy_exit(ks_pcie->phy[i]);
  730. goto err_phy;
  731. }
  732. }
  733. return 0;
  734. err_phy:
  735. while (--i >= 0) {
  736. phy_power_off(ks_pcie->phy[i]);
  737. phy_exit(ks_pcie->phy[i]);
  738. }
  739. return ret;
  740. }
  741. static int __init ks_pcie_probe(struct platform_device *pdev)
  742. {
  743. struct device *dev = &pdev->dev;
  744. struct device_node *np = dev->of_node;
  745. struct dw_pcie *pci;
  746. struct keystone_pcie *ks_pcie;
  747. struct device_link **link;
  748. u32 num_viewport;
  749. struct phy **phy;
  750. u32 num_lanes;
  751. char name[10];
  752. int ret;
  753. int i;
  754. ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
  755. if (!ks_pcie)
  756. return -ENOMEM;
  757. pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
  758. if (!pci)
  759. return -ENOMEM;
  760. pci->dev = dev;
  761. pci->ops = &ks_pcie_dw_pcie_ops;
  762. ret = of_property_read_u32(np, "num-viewport", &num_viewport);
  763. if (ret < 0) {
  764. dev_err(dev, "unable to read *num-viewport* property\n");
  765. return ret;
  766. }
  767. ret = of_property_read_u32(np, "num-lanes", &num_lanes);
  768. if (ret)
  769. num_lanes = 1;
  770. phy = devm_kzalloc(dev, sizeof(*phy) * num_lanes, GFP_KERNEL);
  771. if (!phy)
  772. return -ENOMEM;
  773. link = devm_kzalloc(dev, sizeof(*link) * num_lanes, GFP_KERNEL);
  774. if (!link)
  775. return -ENOMEM;
  776. for (i = 0; i < num_lanes; i++) {
  777. snprintf(name, sizeof(name), "pcie-phy%d", i);
  778. phy[i] = devm_phy_optional_get(dev, name);
  779. if (IS_ERR(phy[i])) {
  780. ret = PTR_ERR(phy[i]);
  781. goto err_link;
  782. }
  783. if (!phy[i])
  784. continue;
  785. link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
  786. if (!link[i]) {
  787. ret = -EINVAL;
  788. goto err_link;
  789. }
  790. }
  791. ks_pcie->np = np;
  792. ks_pcie->pci = pci;
  793. ks_pcie->link = link;
  794. ks_pcie->num_lanes = num_lanes;
  795. ks_pcie->num_viewport = num_viewport;
  796. ks_pcie->phy = phy;
  797. ret = ks_pcie_enable_phy(ks_pcie);
  798. if (ret) {
  799. dev_err(dev, "failed to enable phy\n");
  800. goto err_link;
  801. }
  802. platform_set_drvdata(pdev, ks_pcie);
  803. pm_runtime_enable(dev);
  804. ret = pm_runtime_get_sync(dev);
  805. if (ret < 0) {
  806. dev_err(dev, "pm_runtime_get_sync failed\n");
  807. goto err_get_sync;
  808. }
  809. ret = ks_pcie_add_pcie_port(ks_pcie, pdev);
  810. if (ret < 0)
  811. goto err_get_sync;
  812. return 0;
  813. err_get_sync:
  814. pm_runtime_put(dev);
  815. pm_runtime_disable(dev);
  816. ks_pcie_disable_phy(ks_pcie);
  817. err_link:
  818. while (--i >= 0 && link[i])
  819. device_link_del(link[i]);
  820. return ret;
  821. }
  822. static int __exit ks_pcie_remove(struct platform_device *pdev)
  823. {
  824. struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
  825. struct device_link **link = ks_pcie->link;
  826. int num_lanes = ks_pcie->num_lanes;
  827. struct device *dev = &pdev->dev;
  828. pm_runtime_put(dev);
  829. pm_runtime_disable(dev);
  830. ks_pcie_disable_phy(ks_pcie);
  831. while (num_lanes--)
  832. device_link_del(link[num_lanes]);
  833. return 0;
  834. }
  835. static struct platform_driver ks_pcie_driver __refdata = {
  836. .probe = ks_pcie_probe,
  837. .remove = __exit_p(ks_pcie_remove),
  838. .driver = {
  839. .name = "keystone-pcie",
  840. .of_match_table = of_match_ptr(ks_pcie_of_match),
  841. },
  842. };
  843. builtin_platform_driver(ks_pcie_driver);