nicvf_main.c 57 KB

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  1. /*
  2. * Copyright (C) 2015 Cavium, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of version 2 of the GNU General Public License
  6. * as published by the Free Software Foundation.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/pci.h>
  11. #include <linux/netdevice.h>
  12. #include <linux/if_vlan.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/ethtool.h>
  15. #include <linux/log2.h>
  16. #include <linux/prefetch.h>
  17. #include <linux/irq.h>
  18. #include <linux/iommu.h>
  19. #include <linux/bpf.h>
  20. #include <linux/bpf_trace.h>
  21. #include <linux/filter.h>
  22. #include <linux/net_tstamp.h>
  23. #include <linux/workqueue.h>
  24. #include "nic_reg.h"
  25. #include "nic.h"
  26. #include "nicvf_queues.h"
  27. #include "thunder_bgx.h"
  28. #include "../common/cavium_ptp.h"
  29. #define DRV_NAME "nicvf"
  30. #define DRV_VERSION "1.0"
  31. /* Supported devices */
  32. static const struct pci_device_id nicvf_id_table[] = {
  33. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  34. PCI_DEVICE_ID_THUNDER_NIC_VF,
  35. PCI_VENDOR_ID_CAVIUM,
  36. PCI_SUBSYS_DEVID_88XX_NIC_VF) },
  37. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  38. PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
  39. PCI_VENDOR_ID_CAVIUM,
  40. PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF) },
  41. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  42. PCI_DEVICE_ID_THUNDER_NIC_VF,
  43. PCI_VENDOR_ID_CAVIUM,
  44. PCI_SUBSYS_DEVID_81XX_NIC_VF) },
  45. { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
  46. PCI_DEVICE_ID_THUNDER_NIC_VF,
  47. PCI_VENDOR_ID_CAVIUM,
  48. PCI_SUBSYS_DEVID_83XX_NIC_VF) },
  49. { 0, } /* end of table */
  50. };
  51. MODULE_AUTHOR("Sunil Goutham");
  52. MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
  53. MODULE_LICENSE("GPL v2");
  54. MODULE_VERSION(DRV_VERSION);
  55. MODULE_DEVICE_TABLE(pci, nicvf_id_table);
  56. static int debug = 0x00;
  57. module_param(debug, int, 0644);
  58. MODULE_PARM_DESC(debug, "Debug message level bitmap");
  59. static int cpi_alg = CPI_ALG_NONE;
  60. module_param(cpi_alg, int, 0444);
  61. MODULE_PARM_DESC(cpi_alg,
  62. "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
  63. /* workqueue for handling kernel ndo_set_rx_mode() calls */
  64. static struct workqueue_struct *nicvf_rx_mode_wq;
  65. static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx)
  66. {
  67. if (nic->sqs_mode)
  68. return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS);
  69. else
  70. return qidx;
  71. }
  72. /* The Cavium ThunderX network controller can *only* be found in SoCs
  73. * containing the ThunderX ARM64 CPU implementation. All accesses to the device
  74. * registers on this platform are implicitly strongly ordered with respect
  75. * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
  76. * with no memory barriers in this driver. The readq()/writeq() functions add
  77. * explicit ordering operation which in this case are redundant, and only
  78. * add overhead.
  79. */
  80. /* Register read/write APIs */
  81. void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
  82. {
  83. writeq_relaxed(val, nic->reg_base + offset);
  84. }
  85. u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
  86. {
  87. return readq_relaxed(nic->reg_base + offset);
  88. }
  89. void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
  90. u64 qidx, u64 val)
  91. {
  92. void __iomem *addr = nic->reg_base + offset;
  93. writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
  94. }
  95. u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
  96. {
  97. void __iomem *addr = nic->reg_base + offset;
  98. return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
  99. }
  100. /* VF -> PF mailbox communication */
  101. static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
  102. {
  103. u64 *msg = (u64 *)mbx;
  104. nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
  105. nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
  106. }
  107. int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
  108. {
  109. int timeout = NIC_MBOX_MSG_TIMEOUT;
  110. int sleep = 10;
  111. nic->pf_acked = false;
  112. nic->pf_nacked = false;
  113. nicvf_write_to_mbx(nic, mbx);
  114. /* Wait for previous message to be acked, timeout 2sec */
  115. while (!nic->pf_acked) {
  116. if (nic->pf_nacked) {
  117. netdev_err(nic->netdev,
  118. "PF NACK to mbox msg 0x%02x from VF%d\n",
  119. (mbx->msg.msg & 0xFF), nic->vf_id);
  120. return -EINVAL;
  121. }
  122. msleep(sleep);
  123. if (nic->pf_acked)
  124. break;
  125. timeout -= sleep;
  126. if (!timeout) {
  127. netdev_err(nic->netdev,
  128. "PF didn't ACK to mbox msg 0x%02x from VF%d\n",
  129. (mbx->msg.msg & 0xFF), nic->vf_id);
  130. return -EBUSY;
  131. }
  132. }
  133. return 0;
  134. }
  135. /* Checks if VF is able to comminicate with PF
  136. * and also gets the VNIC number this VF is associated to.
  137. */
  138. static int nicvf_check_pf_ready(struct nicvf *nic)
  139. {
  140. union nic_mbx mbx = {};
  141. mbx.msg.msg = NIC_MBOX_MSG_READY;
  142. if (nicvf_send_msg_to_pf(nic, &mbx)) {
  143. netdev_err(nic->netdev,
  144. "PF didn't respond to READY msg\n");
  145. return 0;
  146. }
  147. return 1;
  148. }
  149. static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
  150. {
  151. if (bgx->rx)
  152. nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
  153. else
  154. nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
  155. }
  156. static void nicvf_handle_mbx_intr(struct nicvf *nic)
  157. {
  158. union nic_mbx mbx = {};
  159. u64 *mbx_data;
  160. u64 mbx_addr;
  161. int i;
  162. mbx_addr = NIC_VF_PF_MAILBOX_0_1;
  163. mbx_data = (u64 *)&mbx;
  164. for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
  165. *mbx_data = nicvf_reg_read(nic, mbx_addr);
  166. mbx_data++;
  167. mbx_addr += sizeof(u64);
  168. }
  169. netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
  170. switch (mbx.msg.msg) {
  171. case NIC_MBOX_MSG_READY:
  172. nic->pf_acked = true;
  173. nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
  174. nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
  175. nic->node = mbx.nic_cfg.node_id;
  176. if (!nic->set_mac_pending)
  177. ether_addr_copy(nic->netdev->dev_addr,
  178. mbx.nic_cfg.mac_addr);
  179. nic->sqs_mode = mbx.nic_cfg.sqs_mode;
  180. nic->loopback_supported = mbx.nic_cfg.loopback_supported;
  181. nic->link_up = false;
  182. nic->duplex = 0;
  183. nic->speed = 0;
  184. break;
  185. case NIC_MBOX_MSG_ACK:
  186. nic->pf_acked = true;
  187. break;
  188. case NIC_MBOX_MSG_NACK:
  189. nic->pf_nacked = true;
  190. break;
  191. case NIC_MBOX_MSG_RSS_SIZE:
  192. nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
  193. nic->pf_acked = true;
  194. break;
  195. case NIC_MBOX_MSG_BGX_STATS:
  196. nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
  197. nic->pf_acked = true;
  198. break;
  199. case NIC_MBOX_MSG_BGX_LINK_CHANGE:
  200. nic->pf_acked = true;
  201. nic->link_up = mbx.link_status.link_up;
  202. nic->duplex = mbx.link_status.duplex;
  203. nic->speed = mbx.link_status.speed;
  204. nic->mac_type = mbx.link_status.mac_type;
  205. if (nic->link_up) {
  206. netdev_info(nic->netdev, "Link is Up %d Mbps %s duplex\n",
  207. nic->speed,
  208. nic->duplex == DUPLEX_FULL ?
  209. "Full" : "Half");
  210. netif_carrier_on(nic->netdev);
  211. netif_tx_start_all_queues(nic->netdev);
  212. } else {
  213. netdev_info(nic->netdev, "Link is Down\n");
  214. netif_carrier_off(nic->netdev);
  215. netif_tx_stop_all_queues(nic->netdev);
  216. }
  217. break;
  218. case NIC_MBOX_MSG_ALLOC_SQS:
  219. nic->sqs_count = mbx.sqs_alloc.qs_count;
  220. nic->pf_acked = true;
  221. break;
  222. case NIC_MBOX_MSG_SNICVF_PTR:
  223. /* Primary VF: make note of secondary VF's pointer
  224. * to be used while packet transmission.
  225. */
  226. nic->snicvf[mbx.nicvf.sqs_id] =
  227. (struct nicvf *)mbx.nicvf.nicvf;
  228. nic->pf_acked = true;
  229. break;
  230. case NIC_MBOX_MSG_PNICVF_PTR:
  231. /* Secondary VF/Qset: make note of primary VF's pointer
  232. * to be used while packet reception, to handover packet
  233. * to primary VF's netdev.
  234. */
  235. nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf;
  236. nic->pf_acked = true;
  237. break;
  238. case NIC_MBOX_MSG_PFC:
  239. nic->pfc.autoneg = mbx.pfc.autoneg;
  240. nic->pfc.fc_rx = mbx.pfc.fc_rx;
  241. nic->pfc.fc_tx = mbx.pfc.fc_tx;
  242. nic->pf_acked = true;
  243. break;
  244. default:
  245. netdev_err(nic->netdev,
  246. "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
  247. break;
  248. }
  249. nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
  250. }
  251. static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
  252. {
  253. union nic_mbx mbx = {};
  254. mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
  255. mbx.mac.vf_id = nic->vf_id;
  256. ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr);
  257. return nicvf_send_msg_to_pf(nic, &mbx);
  258. }
  259. static void nicvf_config_cpi(struct nicvf *nic)
  260. {
  261. union nic_mbx mbx = {};
  262. mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
  263. mbx.cpi_cfg.vf_id = nic->vf_id;
  264. mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
  265. mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
  266. nicvf_send_msg_to_pf(nic, &mbx);
  267. }
  268. static void nicvf_get_rss_size(struct nicvf *nic)
  269. {
  270. union nic_mbx mbx = {};
  271. mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
  272. mbx.rss_size.vf_id = nic->vf_id;
  273. nicvf_send_msg_to_pf(nic, &mbx);
  274. }
  275. void nicvf_config_rss(struct nicvf *nic)
  276. {
  277. union nic_mbx mbx = {};
  278. struct nicvf_rss_info *rss = &nic->rss_info;
  279. int ind_tbl_len = rss->rss_size;
  280. int i, nextq = 0;
  281. mbx.rss_cfg.vf_id = nic->vf_id;
  282. mbx.rss_cfg.hash_bits = rss->hash_bits;
  283. while (ind_tbl_len) {
  284. mbx.rss_cfg.tbl_offset = nextq;
  285. mbx.rss_cfg.tbl_len = min(ind_tbl_len,
  286. RSS_IND_TBL_LEN_PER_MBX_MSG);
  287. mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
  288. NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
  289. for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
  290. mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
  291. nicvf_send_msg_to_pf(nic, &mbx);
  292. ind_tbl_len -= mbx.rss_cfg.tbl_len;
  293. }
  294. }
  295. void nicvf_set_rss_key(struct nicvf *nic)
  296. {
  297. struct nicvf_rss_info *rss = &nic->rss_info;
  298. u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
  299. int idx;
  300. for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
  301. nicvf_reg_write(nic, key_addr, rss->key[idx]);
  302. key_addr += sizeof(u64);
  303. }
  304. }
  305. static int nicvf_rss_init(struct nicvf *nic)
  306. {
  307. struct nicvf_rss_info *rss = &nic->rss_info;
  308. int idx;
  309. nicvf_get_rss_size(nic);
  310. if (cpi_alg != CPI_ALG_NONE) {
  311. rss->enable = false;
  312. rss->hash_bits = 0;
  313. return 0;
  314. }
  315. rss->enable = true;
  316. netdev_rss_key_fill(rss->key, RSS_HASH_KEY_SIZE * sizeof(u64));
  317. nicvf_set_rss_key(nic);
  318. rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
  319. nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
  320. rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
  321. for (idx = 0; idx < rss->rss_size; idx++)
  322. rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
  323. nic->rx_queues);
  324. nicvf_config_rss(nic);
  325. return 1;
  326. }
  327. /* Request PF to allocate additional Qsets */
  328. static void nicvf_request_sqs(struct nicvf *nic)
  329. {
  330. union nic_mbx mbx = {};
  331. int sqs;
  332. int sqs_count = nic->sqs_count;
  333. int rx_queues = 0, tx_queues = 0;
  334. /* Only primary VF should request */
  335. if (nic->sqs_mode || !nic->sqs_count)
  336. return;
  337. mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
  338. mbx.sqs_alloc.vf_id = nic->vf_id;
  339. mbx.sqs_alloc.qs_count = nic->sqs_count;
  340. if (nicvf_send_msg_to_pf(nic, &mbx)) {
  341. /* No response from PF */
  342. nic->sqs_count = 0;
  343. return;
  344. }
  345. /* Return if no Secondary Qsets available */
  346. if (!nic->sqs_count)
  347. return;
  348. if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS)
  349. rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS;
  350. tx_queues = nic->tx_queues + nic->xdp_tx_queues;
  351. if (tx_queues > MAX_SND_QUEUES_PER_QS)
  352. tx_queues = tx_queues - MAX_SND_QUEUES_PER_QS;
  353. /* Set no of Rx/Tx queues in each of the SQsets */
  354. for (sqs = 0; sqs < nic->sqs_count; sqs++) {
  355. mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
  356. mbx.nicvf.vf_id = nic->vf_id;
  357. mbx.nicvf.sqs_id = sqs;
  358. nicvf_send_msg_to_pf(nic, &mbx);
  359. nic->snicvf[sqs]->sqs_id = sqs;
  360. if (rx_queues > MAX_RCV_QUEUES_PER_QS) {
  361. nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS;
  362. rx_queues -= MAX_RCV_QUEUES_PER_QS;
  363. } else {
  364. nic->snicvf[sqs]->qs->rq_cnt = rx_queues;
  365. rx_queues = 0;
  366. }
  367. if (tx_queues > MAX_SND_QUEUES_PER_QS) {
  368. nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS;
  369. tx_queues -= MAX_SND_QUEUES_PER_QS;
  370. } else {
  371. nic->snicvf[sqs]->qs->sq_cnt = tx_queues;
  372. tx_queues = 0;
  373. }
  374. nic->snicvf[sqs]->qs->cq_cnt =
  375. max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt);
  376. /* Initialize secondary Qset's queues and its interrupts */
  377. nicvf_open(nic->snicvf[sqs]->netdev);
  378. }
  379. /* Update stack with actual Rx/Tx queue count allocated */
  380. if (sqs_count != nic->sqs_count)
  381. nicvf_set_real_num_queues(nic->netdev,
  382. nic->tx_queues, nic->rx_queues);
  383. }
  384. /* Send this Qset's nicvf pointer to PF.
  385. * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs
  386. * so that packets received by these Qsets can use primary VF's netdev
  387. */
  388. static void nicvf_send_vf_struct(struct nicvf *nic)
  389. {
  390. union nic_mbx mbx = {};
  391. mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR;
  392. mbx.nicvf.sqs_mode = nic->sqs_mode;
  393. mbx.nicvf.nicvf = (u64)nic;
  394. nicvf_send_msg_to_pf(nic, &mbx);
  395. }
  396. static void nicvf_get_primary_vf_struct(struct nicvf *nic)
  397. {
  398. union nic_mbx mbx = {};
  399. mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
  400. nicvf_send_msg_to_pf(nic, &mbx);
  401. }
  402. int nicvf_set_real_num_queues(struct net_device *netdev,
  403. int tx_queues, int rx_queues)
  404. {
  405. int err = 0;
  406. err = netif_set_real_num_tx_queues(netdev, tx_queues);
  407. if (err) {
  408. netdev_err(netdev,
  409. "Failed to set no of Tx queues: %d\n", tx_queues);
  410. return err;
  411. }
  412. err = netif_set_real_num_rx_queues(netdev, rx_queues);
  413. if (err)
  414. netdev_err(netdev,
  415. "Failed to set no of Rx queues: %d\n", rx_queues);
  416. return err;
  417. }
  418. static int nicvf_init_resources(struct nicvf *nic)
  419. {
  420. int err;
  421. /* Enable Qset */
  422. nicvf_qset_config(nic, true);
  423. /* Initialize queues and HW for data transfer */
  424. err = nicvf_config_data_transfer(nic, true);
  425. if (err) {
  426. netdev_err(nic->netdev,
  427. "Failed to alloc/config VF's QSet resources\n");
  428. return err;
  429. }
  430. return 0;
  431. }
  432. static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
  433. struct cqe_rx_t *cqe_rx, struct snd_queue *sq,
  434. struct rcv_queue *rq, struct sk_buff **skb)
  435. {
  436. struct xdp_buff xdp;
  437. struct page *page;
  438. u32 action;
  439. u16 len, offset = 0;
  440. u64 dma_addr, cpu_addr;
  441. void *orig_data;
  442. /* Retrieve packet buffer's DMA address and length */
  443. len = *((u16 *)((void *)cqe_rx + (3 * sizeof(u64))));
  444. dma_addr = *((u64 *)((void *)cqe_rx + (7 * sizeof(u64))));
  445. cpu_addr = nicvf_iova_to_phys(nic, dma_addr);
  446. if (!cpu_addr)
  447. return false;
  448. cpu_addr = (u64)phys_to_virt(cpu_addr);
  449. page = virt_to_page((void *)cpu_addr);
  450. xdp.data_hard_start = page_address(page);
  451. xdp.data = (void *)cpu_addr;
  452. xdp_set_data_meta_invalid(&xdp);
  453. xdp.data_end = xdp.data + len;
  454. xdp.rxq = &rq->xdp_rxq;
  455. orig_data = xdp.data;
  456. rcu_read_lock();
  457. action = bpf_prog_run_xdp(prog, &xdp);
  458. rcu_read_unlock();
  459. len = xdp.data_end - xdp.data;
  460. /* Check if XDP program has changed headers */
  461. if (orig_data != xdp.data) {
  462. offset = orig_data - xdp.data;
  463. dma_addr -= offset;
  464. }
  465. switch (action) {
  466. case XDP_PASS:
  467. /* Check if it's a recycled page, if not
  468. * unmap the DMA mapping.
  469. *
  470. * Recycled page holds an extra reference.
  471. */
  472. if (page_ref_count(page) == 1) {
  473. dma_addr &= PAGE_MASK;
  474. dma_unmap_page_attrs(&nic->pdev->dev, dma_addr,
  475. RCV_FRAG_LEN + XDP_PACKET_HEADROOM,
  476. DMA_FROM_DEVICE,
  477. DMA_ATTR_SKIP_CPU_SYNC);
  478. }
  479. /* Build SKB and pass on packet to network stack */
  480. *skb = build_skb(xdp.data,
  481. RCV_FRAG_LEN - cqe_rx->align_pad + offset);
  482. if (!*skb)
  483. put_page(page);
  484. else
  485. skb_put(*skb, len);
  486. return false;
  487. case XDP_TX:
  488. nicvf_xdp_sq_append_pkt(nic, sq, (u64)xdp.data, dma_addr, len);
  489. return true;
  490. default:
  491. bpf_warn_invalid_xdp_action(action);
  492. /* fall through */
  493. case XDP_ABORTED:
  494. trace_xdp_exception(nic->netdev, prog, action);
  495. /* fall through */
  496. case XDP_DROP:
  497. /* Check if it's a recycled page, if not
  498. * unmap the DMA mapping.
  499. *
  500. * Recycled page holds an extra reference.
  501. */
  502. if (page_ref_count(page) == 1) {
  503. dma_addr &= PAGE_MASK;
  504. dma_unmap_page_attrs(&nic->pdev->dev, dma_addr,
  505. RCV_FRAG_LEN + XDP_PACKET_HEADROOM,
  506. DMA_FROM_DEVICE,
  507. DMA_ATTR_SKIP_CPU_SYNC);
  508. }
  509. put_page(page);
  510. return true;
  511. }
  512. return false;
  513. }
  514. static void nicvf_snd_ptp_handler(struct net_device *netdev,
  515. struct cqe_send_t *cqe_tx)
  516. {
  517. struct nicvf *nic = netdev_priv(netdev);
  518. struct skb_shared_hwtstamps ts;
  519. u64 ns;
  520. nic = nic->pnicvf;
  521. /* Sync for 'ptp_skb' */
  522. smp_rmb();
  523. /* New timestamp request can be queued now */
  524. atomic_set(&nic->tx_ptp_skbs, 0);
  525. /* Check for timestamp requested skb */
  526. if (!nic->ptp_skb)
  527. return;
  528. /* Check if timestamping is timedout, which is set to 10us */
  529. if (cqe_tx->send_status == CQ_TX_ERROP_TSTMP_TIMEOUT ||
  530. cqe_tx->send_status == CQ_TX_ERROP_TSTMP_CONFLICT)
  531. goto no_tstamp;
  532. /* Get the timestamp */
  533. memset(&ts, 0, sizeof(ts));
  534. ns = cavium_ptp_tstamp2time(nic->ptp_clock, cqe_tx->ptp_timestamp);
  535. ts.hwtstamp = ns_to_ktime(ns);
  536. skb_tstamp_tx(nic->ptp_skb, &ts);
  537. no_tstamp:
  538. /* Free the original skb */
  539. dev_kfree_skb_any(nic->ptp_skb);
  540. nic->ptp_skb = NULL;
  541. /* Sync 'ptp_skb' */
  542. smp_wmb();
  543. }
  544. static void nicvf_snd_pkt_handler(struct net_device *netdev,
  545. struct cqe_send_t *cqe_tx,
  546. int budget, int *subdesc_cnt,
  547. unsigned int *tx_pkts, unsigned int *tx_bytes)
  548. {
  549. struct sk_buff *skb = NULL;
  550. struct page *page;
  551. struct nicvf *nic = netdev_priv(netdev);
  552. struct snd_queue *sq;
  553. struct sq_hdr_subdesc *hdr;
  554. struct sq_hdr_subdesc *tso_sqe;
  555. sq = &nic->qs->sq[cqe_tx->sq_idx];
  556. hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
  557. if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
  558. return;
  559. /* Check for errors */
  560. if (cqe_tx->send_status)
  561. nicvf_check_cqe_tx_errs(nic->pnicvf, cqe_tx);
  562. /* Is this a XDP designated Tx queue */
  563. if (sq->is_xdp) {
  564. page = (struct page *)sq->xdp_page[cqe_tx->sqe_ptr];
  565. /* Check if it's recycled page or else unmap DMA mapping */
  566. if (page && (page_ref_count(page) == 1))
  567. nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr,
  568. hdr->subdesc_cnt);
  569. /* Release page reference for recycling */
  570. if (page)
  571. put_page(page);
  572. sq->xdp_page[cqe_tx->sqe_ptr] = (u64)NULL;
  573. *subdesc_cnt += hdr->subdesc_cnt + 1;
  574. return;
  575. }
  576. skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
  577. if (skb) {
  578. /* Check for dummy descriptor used for HW TSO offload on 88xx */
  579. if (hdr->dont_send) {
  580. /* Get actual TSO descriptors and free them */
  581. tso_sqe =
  582. (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, hdr->rsvd2);
  583. nicvf_unmap_sndq_buffers(nic, sq, hdr->rsvd2,
  584. tso_sqe->subdesc_cnt);
  585. *subdesc_cnt += tso_sqe->subdesc_cnt + 1;
  586. } else {
  587. nicvf_unmap_sndq_buffers(nic, sq, cqe_tx->sqe_ptr,
  588. hdr->subdesc_cnt);
  589. }
  590. *subdesc_cnt += hdr->subdesc_cnt + 1;
  591. prefetch(skb);
  592. (*tx_pkts)++;
  593. *tx_bytes += skb->len;
  594. /* If timestamp is requested for this skb, don't free it */
  595. if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
  596. !nic->pnicvf->ptp_skb)
  597. nic->pnicvf->ptp_skb = skb;
  598. else
  599. napi_consume_skb(skb, budget);
  600. sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
  601. } else {
  602. /* In case of SW TSO on 88xx, only last segment will have
  603. * a SKB attached, so just free SQEs here.
  604. */
  605. if (!nic->hw_tso)
  606. *subdesc_cnt += hdr->subdesc_cnt + 1;
  607. }
  608. }
  609. static inline void nicvf_set_rxhash(struct net_device *netdev,
  610. struct cqe_rx_t *cqe_rx,
  611. struct sk_buff *skb)
  612. {
  613. u8 hash_type;
  614. u32 hash;
  615. if (!(netdev->features & NETIF_F_RXHASH))
  616. return;
  617. switch (cqe_rx->rss_alg) {
  618. case RSS_ALG_TCP_IP:
  619. case RSS_ALG_UDP_IP:
  620. hash_type = PKT_HASH_TYPE_L4;
  621. hash = cqe_rx->rss_tag;
  622. break;
  623. case RSS_ALG_IP:
  624. hash_type = PKT_HASH_TYPE_L3;
  625. hash = cqe_rx->rss_tag;
  626. break;
  627. default:
  628. hash_type = PKT_HASH_TYPE_NONE;
  629. hash = 0;
  630. }
  631. skb_set_hash(skb, hash, hash_type);
  632. }
  633. static inline void nicvf_set_rxtstamp(struct nicvf *nic, struct sk_buff *skb)
  634. {
  635. u64 ns;
  636. if (!nic->ptp_clock || !nic->hw_rx_tstamp)
  637. return;
  638. /* The first 8 bytes is the timestamp */
  639. ns = cavium_ptp_tstamp2time(nic->ptp_clock,
  640. be64_to_cpu(*(__be64 *)skb->data));
  641. skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
  642. __skb_pull(skb, 8);
  643. }
  644. static void nicvf_rcv_pkt_handler(struct net_device *netdev,
  645. struct napi_struct *napi,
  646. struct cqe_rx_t *cqe_rx,
  647. struct snd_queue *sq, struct rcv_queue *rq)
  648. {
  649. struct sk_buff *skb = NULL;
  650. struct nicvf *nic = netdev_priv(netdev);
  651. struct nicvf *snic = nic;
  652. int err = 0;
  653. int rq_idx;
  654. rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx);
  655. if (nic->sqs_mode) {
  656. /* Use primary VF's 'nicvf' struct */
  657. nic = nic->pnicvf;
  658. netdev = nic->netdev;
  659. }
  660. /* Check for errors */
  661. if (cqe_rx->err_level || cqe_rx->err_opcode) {
  662. err = nicvf_check_cqe_rx_errs(nic, cqe_rx);
  663. if (err && !cqe_rx->rb_cnt)
  664. return;
  665. }
  666. /* For XDP, ignore pkts spanning multiple pages */
  667. if (nic->xdp_prog && (cqe_rx->rb_cnt == 1)) {
  668. /* Packet consumed by XDP */
  669. if (nicvf_xdp_rx(snic, nic->xdp_prog, cqe_rx, sq, rq, &skb))
  670. return;
  671. } else {
  672. skb = nicvf_get_rcv_skb(snic, cqe_rx,
  673. nic->xdp_prog ? true : false);
  674. }
  675. if (!skb)
  676. return;
  677. if (netif_msg_pktdata(nic)) {
  678. netdev_info(nic->netdev, "skb 0x%p, len=%d\n", skb, skb->len);
  679. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
  680. skb->data, skb->len, true);
  681. }
  682. /* If error packet, drop it here */
  683. if (err) {
  684. dev_kfree_skb_any(skb);
  685. return;
  686. }
  687. nicvf_set_rxtstamp(nic, skb);
  688. nicvf_set_rxhash(netdev, cqe_rx, skb);
  689. skb_record_rx_queue(skb, rq_idx);
  690. if (netdev->hw_features & NETIF_F_RXCSUM) {
  691. /* HW by default verifies TCP/UDP/SCTP checksums */
  692. skb->ip_summed = CHECKSUM_UNNECESSARY;
  693. } else {
  694. skb_checksum_none_assert(skb);
  695. }
  696. skb->protocol = eth_type_trans(skb, netdev);
  697. /* Check for stripped VLAN */
  698. if (cqe_rx->vlan_found && cqe_rx->vlan_stripped)
  699. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  700. ntohs((__force __be16)cqe_rx->vlan_tci));
  701. if (napi && (netdev->features & NETIF_F_GRO))
  702. napi_gro_receive(napi, skb);
  703. else
  704. netif_receive_skb(skb);
  705. }
  706. static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
  707. struct napi_struct *napi, int budget)
  708. {
  709. int processed_cqe, work_done = 0, tx_done = 0;
  710. int cqe_count, cqe_head;
  711. int subdesc_cnt = 0;
  712. struct nicvf *nic = netdev_priv(netdev);
  713. struct queue_set *qs = nic->qs;
  714. struct cmp_queue *cq = &qs->cq[cq_idx];
  715. struct cqe_rx_t *cq_desc;
  716. struct netdev_queue *txq;
  717. struct snd_queue *sq = &qs->sq[cq_idx];
  718. struct rcv_queue *rq = &qs->rq[cq_idx];
  719. unsigned int tx_pkts = 0, tx_bytes = 0, txq_idx;
  720. spin_lock_bh(&cq->lock);
  721. loop:
  722. processed_cqe = 0;
  723. /* Get no of valid CQ entries to process */
  724. cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
  725. cqe_count &= CQ_CQE_COUNT;
  726. if (!cqe_count)
  727. goto done;
  728. /* Get head of the valid CQ entries */
  729. cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
  730. cqe_head &= 0xFFFF;
  731. while (processed_cqe < cqe_count) {
  732. /* Get the CQ descriptor */
  733. cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
  734. cqe_head++;
  735. cqe_head &= (cq->dmem.q_len - 1);
  736. /* Initiate prefetch for next descriptor */
  737. prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
  738. if ((work_done >= budget) && napi &&
  739. (cq_desc->cqe_type != CQE_TYPE_SEND)) {
  740. break;
  741. }
  742. switch (cq_desc->cqe_type) {
  743. case CQE_TYPE_RX:
  744. nicvf_rcv_pkt_handler(netdev, napi, cq_desc, sq, rq);
  745. work_done++;
  746. break;
  747. case CQE_TYPE_SEND:
  748. nicvf_snd_pkt_handler(netdev, (void *)cq_desc,
  749. budget, &subdesc_cnt,
  750. &tx_pkts, &tx_bytes);
  751. tx_done++;
  752. break;
  753. case CQE_TYPE_SEND_PTP:
  754. nicvf_snd_ptp_handler(netdev, (void *)cq_desc);
  755. break;
  756. case CQE_TYPE_INVALID:
  757. case CQE_TYPE_RX_SPLIT:
  758. case CQE_TYPE_RX_TCP:
  759. /* Ignore for now */
  760. break;
  761. }
  762. processed_cqe++;
  763. }
  764. /* Ring doorbell to inform H/W to reuse processed CQEs */
  765. nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
  766. cq_idx, processed_cqe);
  767. if ((work_done < budget) && napi)
  768. goto loop;
  769. done:
  770. /* Update SQ's descriptor free count */
  771. if (subdesc_cnt)
  772. nicvf_put_sq_desc(sq, subdesc_cnt);
  773. txq_idx = nicvf_netdev_qidx(nic, cq_idx);
  774. /* Handle XDP TX queues */
  775. if (nic->pnicvf->xdp_prog) {
  776. if (txq_idx < nic->pnicvf->xdp_tx_queues) {
  777. nicvf_xdp_sq_doorbell(nic, sq, cq_idx);
  778. goto out;
  779. }
  780. nic = nic->pnicvf;
  781. txq_idx -= nic->pnicvf->xdp_tx_queues;
  782. }
  783. /* Wakeup TXQ if its stopped earlier due to SQ full */
  784. if (tx_done ||
  785. (atomic_read(&sq->free_cnt) >= MIN_SQ_DESC_PER_PKT_XMIT)) {
  786. netdev = nic->pnicvf->netdev;
  787. txq = netdev_get_tx_queue(netdev, txq_idx);
  788. if (tx_pkts)
  789. netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
  790. /* To read updated queue and carrier status */
  791. smp_mb();
  792. if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
  793. netif_tx_wake_queue(txq);
  794. nic = nic->pnicvf;
  795. this_cpu_inc(nic->drv_stats->txq_wake);
  796. netif_warn(nic, tx_err, netdev,
  797. "Transmit queue wakeup SQ%d\n", txq_idx);
  798. }
  799. }
  800. out:
  801. spin_unlock_bh(&cq->lock);
  802. return work_done;
  803. }
  804. static int nicvf_poll(struct napi_struct *napi, int budget)
  805. {
  806. u64 cq_head;
  807. int work_done = 0;
  808. struct net_device *netdev = napi->dev;
  809. struct nicvf *nic = netdev_priv(netdev);
  810. struct nicvf_cq_poll *cq;
  811. cq = container_of(napi, struct nicvf_cq_poll, napi);
  812. work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
  813. if (work_done < budget) {
  814. /* Slow packet rate, exit polling */
  815. napi_complete_done(napi, work_done);
  816. /* Re-enable interrupts */
  817. cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
  818. cq->cq_idx);
  819. nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
  820. nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
  821. cq->cq_idx, cq_head);
  822. nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
  823. }
  824. return work_done;
  825. }
  826. /* Qset error interrupt handler
  827. *
  828. * As of now only CQ errors are handled
  829. */
  830. static void nicvf_handle_qs_err(unsigned long data)
  831. {
  832. struct nicvf *nic = (struct nicvf *)data;
  833. struct queue_set *qs = nic->qs;
  834. int qidx;
  835. u64 status;
  836. netif_tx_disable(nic->netdev);
  837. /* Check if it is CQ err */
  838. for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
  839. status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
  840. qidx);
  841. if (!(status & CQ_ERR_MASK))
  842. continue;
  843. /* Process already queued CQEs and reconfig CQ */
  844. nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
  845. nicvf_sq_disable(nic, qidx);
  846. nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
  847. nicvf_cmp_queue_config(nic, qs, qidx, true);
  848. nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
  849. nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
  850. nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
  851. }
  852. netif_tx_start_all_queues(nic->netdev);
  853. /* Re-enable Qset error interrupt */
  854. nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
  855. }
  856. static void nicvf_dump_intr_status(struct nicvf *nic)
  857. {
  858. netif_info(nic, intr, nic->netdev, "interrupt status 0x%llx\n",
  859. nicvf_reg_read(nic, NIC_VF_INT));
  860. }
  861. static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
  862. {
  863. struct nicvf *nic = (struct nicvf *)nicvf_irq;
  864. u64 intr;
  865. nicvf_dump_intr_status(nic);
  866. intr = nicvf_reg_read(nic, NIC_VF_INT);
  867. /* Check for spurious interrupt */
  868. if (!(intr & NICVF_INTR_MBOX_MASK))
  869. return IRQ_HANDLED;
  870. nicvf_handle_mbx_intr(nic);
  871. return IRQ_HANDLED;
  872. }
  873. static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq)
  874. {
  875. struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq;
  876. struct nicvf *nic = cq_poll->nicvf;
  877. int qidx = cq_poll->cq_idx;
  878. nicvf_dump_intr_status(nic);
  879. /* Disable interrupts */
  880. nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
  881. /* Schedule NAPI */
  882. napi_schedule_irqoff(&cq_poll->napi);
  883. /* Clear interrupt */
  884. nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
  885. return IRQ_HANDLED;
  886. }
  887. static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq)
  888. {
  889. struct nicvf *nic = (struct nicvf *)nicvf_irq;
  890. u8 qidx;
  891. nicvf_dump_intr_status(nic);
  892. /* Disable RBDR interrupt and schedule softirq */
  893. for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) {
  894. if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
  895. continue;
  896. nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
  897. tasklet_hi_schedule(&nic->rbdr_task);
  898. /* Clear interrupt */
  899. nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
  900. }
  901. return IRQ_HANDLED;
  902. }
  903. static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq)
  904. {
  905. struct nicvf *nic = (struct nicvf *)nicvf_irq;
  906. nicvf_dump_intr_status(nic);
  907. /* Disable Qset err interrupt and schedule softirq */
  908. nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
  909. tasklet_hi_schedule(&nic->qs_err_task);
  910. nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
  911. return IRQ_HANDLED;
  912. }
  913. static void nicvf_set_irq_affinity(struct nicvf *nic)
  914. {
  915. int vec, cpu;
  916. for (vec = 0; vec < nic->num_vec; vec++) {
  917. if (!nic->irq_allocated[vec])
  918. continue;
  919. if (!zalloc_cpumask_var(&nic->affinity_mask[vec], GFP_KERNEL))
  920. return;
  921. /* CQ interrupts */
  922. if (vec < NICVF_INTR_ID_SQ)
  923. /* Leave CPU0 for RBDR and other interrupts */
  924. cpu = nicvf_netdev_qidx(nic, vec) + 1;
  925. else
  926. cpu = 0;
  927. cpumask_set_cpu(cpumask_local_spread(cpu, nic->node),
  928. nic->affinity_mask[vec]);
  929. irq_set_affinity_hint(pci_irq_vector(nic->pdev, vec),
  930. nic->affinity_mask[vec]);
  931. }
  932. }
  933. static int nicvf_register_interrupts(struct nicvf *nic)
  934. {
  935. int irq, ret = 0;
  936. for_each_cq_irq(irq)
  937. sprintf(nic->irq_name[irq], "%s-rxtx-%d",
  938. nic->pnicvf->netdev->name,
  939. nicvf_netdev_qidx(nic, irq));
  940. for_each_sq_irq(irq)
  941. sprintf(nic->irq_name[irq], "%s-sq-%d",
  942. nic->pnicvf->netdev->name,
  943. nicvf_netdev_qidx(nic, irq - NICVF_INTR_ID_SQ));
  944. for_each_rbdr_irq(irq)
  945. sprintf(nic->irq_name[irq], "%s-rbdr-%d",
  946. nic->pnicvf->netdev->name,
  947. nic->sqs_mode ? (nic->sqs_id + 1) : 0);
  948. /* Register CQ interrupts */
  949. for (irq = 0; irq < nic->qs->cq_cnt; irq++) {
  950. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  951. nicvf_intr_handler,
  952. 0, nic->irq_name[irq], nic->napi[irq]);
  953. if (ret)
  954. goto err;
  955. nic->irq_allocated[irq] = true;
  956. }
  957. /* Register RBDR interrupt */
  958. for (irq = NICVF_INTR_ID_RBDR;
  959. irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) {
  960. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  961. nicvf_rbdr_intr_handler,
  962. 0, nic->irq_name[irq], nic);
  963. if (ret)
  964. goto err;
  965. nic->irq_allocated[irq] = true;
  966. }
  967. /* Register QS error interrupt */
  968. sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR], "%s-qset-err-%d",
  969. nic->pnicvf->netdev->name,
  970. nic->sqs_mode ? (nic->sqs_id + 1) : 0);
  971. irq = NICVF_INTR_ID_QS_ERR;
  972. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  973. nicvf_qs_err_intr_handler,
  974. 0, nic->irq_name[irq], nic);
  975. if (ret)
  976. goto err;
  977. nic->irq_allocated[irq] = true;
  978. /* Set IRQ affinities */
  979. nicvf_set_irq_affinity(nic);
  980. err:
  981. if (ret)
  982. netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq);
  983. return ret;
  984. }
  985. static void nicvf_unregister_interrupts(struct nicvf *nic)
  986. {
  987. struct pci_dev *pdev = nic->pdev;
  988. int irq;
  989. /* Free registered interrupts */
  990. for (irq = 0; irq < nic->num_vec; irq++) {
  991. if (!nic->irq_allocated[irq])
  992. continue;
  993. irq_set_affinity_hint(pci_irq_vector(pdev, irq), NULL);
  994. free_cpumask_var(nic->affinity_mask[irq]);
  995. if (irq < NICVF_INTR_ID_SQ)
  996. free_irq(pci_irq_vector(pdev, irq), nic->napi[irq]);
  997. else
  998. free_irq(pci_irq_vector(pdev, irq), nic);
  999. nic->irq_allocated[irq] = false;
  1000. }
  1001. /* Disable MSI-X */
  1002. pci_free_irq_vectors(pdev);
  1003. nic->num_vec = 0;
  1004. }
  1005. /* Initialize MSIX vectors and register MISC interrupt.
  1006. * Send READY message to PF to check if its alive
  1007. */
  1008. static int nicvf_register_misc_interrupt(struct nicvf *nic)
  1009. {
  1010. int ret = 0;
  1011. int irq = NICVF_INTR_ID_MISC;
  1012. /* Return if mailbox interrupt is already registered */
  1013. if (nic->pdev->msix_enabled)
  1014. return 0;
  1015. /* Enable MSI-X */
  1016. nic->num_vec = pci_msix_vec_count(nic->pdev);
  1017. ret = pci_alloc_irq_vectors(nic->pdev, nic->num_vec, nic->num_vec,
  1018. PCI_IRQ_MSIX);
  1019. if (ret < 0) {
  1020. netdev_err(nic->netdev,
  1021. "Req for #%d msix vectors failed\n", nic->num_vec);
  1022. return 1;
  1023. }
  1024. sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
  1025. /* Register Misc interrupt */
  1026. ret = request_irq(pci_irq_vector(nic->pdev, irq),
  1027. nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
  1028. if (ret)
  1029. return ret;
  1030. nic->irq_allocated[irq] = true;
  1031. /* Enable mailbox interrupt */
  1032. nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
  1033. /* Check if VF is able to communicate with PF */
  1034. if (!nicvf_check_pf_ready(nic)) {
  1035. nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
  1036. nicvf_unregister_interrupts(nic);
  1037. return 1;
  1038. }
  1039. return 0;
  1040. }
  1041. static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
  1042. {
  1043. struct nicvf *nic = netdev_priv(netdev);
  1044. int qid = skb_get_queue_mapping(skb);
  1045. struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
  1046. struct nicvf *snic;
  1047. struct snd_queue *sq;
  1048. int tmp;
  1049. /* Check for minimum packet length */
  1050. if (skb->len <= ETH_HLEN) {
  1051. dev_kfree_skb(skb);
  1052. return NETDEV_TX_OK;
  1053. }
  1054. /* In XDP case, initial HW tx queues are used for XDP,
  1055. * but stack's queue mapping starts at '0', so skip the
  1056. * Tx queues attached to Rx queues for XDP.
  1057. */
  1058. if (nic->xdp_prog)
  1059. qid += nic->xdp_tx_queues;
  1060. snic = nic;
  1061. /* Get secondary Qset's SQ structure */
  1062. if (qid >= MAX_SND_QUEUES_PER_QS) {
  1063. tmp = qid / MAX_SND_QUEUES_PER_QS;
  1064. snic = (struct nicvf *)nic->snicvf[tmp - 1];
  1065. if (!snic) {
  1066. netdev_warn(nic->netdev,
  1067. "Secondary Qset#%d's ptr not initialized\n",
  1068. tmp - 1);
  1069. dev_kfree_skb(skb);
  1070. return NETDEV_TX_OK;
  1071. }
  1072. qid = qid % MAX_SND_QUEUES_PER_QS;
  1073. }
  1074. sq = &snic->qs->sq[qid];
  1075. if (!netif_tx_queue_stopped(txq) &&
  1076. !nicvf_sq_append_skb(snic, sq, skb, qid)) {
  1077. netif_tx_stop_queue(txq);
  1078. /* Barrier, so that stop_queue visible to other cpus */
  1079. smp_mb();
  1080. /* Check again, incase another cpu freed descriptors */
  1081. if (atomic_read(&sq->free_cnt) > MIN_SQ_DESC_PER_PKT_XMIT) {
  1082. netif_tx_wake_queue(txq);
  1083. } else {
  1084. this_cpu_inc(nic->drv_stats->txq_stop);
  1085. netif_warn(nic, tx_err, netdev,
  1086. "Transmit ring full, stopping SQ%d\n", qid);
  1087. }
  1088. return NETDEV_TX_BUSY;
  1089. }
  1090. return NETDEV_TX_OK;
  1091. }
  1092. static inline void nicvf_free_cq_poll(struct nicvf *nic)
  1093. {
  1094. struct nicvf_cq_poll *cq_poll;
  1095. int qidx;
  1096. for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
  1097. cq_poll = nic->napi[qidx];
  1098. if (!cq_poll)
  1099. continue;
  1100. nic->napi[qidx] = NULL;
  1101. kfree(cq_poll);
  1102. }
  1103. }
  1104. int nicvf_stop(struct net_device *netdev)
  1105. {
  1106. int irq, qidx;
  1107. struct nicvf *nic = netdev_priv(netdev);
  1108. struct queue_set *qs = nic->qs;
  1109. struct nicvf_cq_poll *cq_poll = NULL;
  1110. union nic_mbx mbx = {};
  1111. mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
  1112. nicvf_send_msg_to_pf(nic, &mbx);
  1113. netif_carrier_off(netdev);
  1114. netif_tx_stop_all_queues(nic->netdev);
  1115. nic->link_up = false;
  1116. /* Teardown secondary qsets first */
  1117. if (!nic->sqs_mode) {
  1118. for (qidx = 0; qidx < nic->sqs_count; qidx++) {
  1119. if (!nic->snicvf[qidx])
  1120. continue;
  1121. nicvf_stop(nic->snicvf[qidx]->netdev);
  1122. nic->snicvf[qidx] = NULL;
  1123. }
  1124. }
  1125. /* Disable RBDR & QS error interrupts */
  1126. for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
  1127. nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
  1128. nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
  1129. }
  1130. nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
  1131. nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
  1132. /* Wait for pending IRQ handlers to finish */
  1133. for (irq = 0; irq < nic->num_vec; irq++)
  1134. synchronize_irq(pci_irq_vector(nic->pdev, irq));
  1135. tasklet_kill(&nic->rbdr_task);
  1136. tasklet_kill(&nic->qs_err_task);
  1137. if (nic->rb_work_scheduled)
  1138. cancel_delayed_work_sync(&nic->rbdr_work);
  1139. for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
  1140. cq_poll = nic->napi[qidx];
  1141. if (!cq_poll)
  1142. continue;
  1143. napi_synchronize(&cq_poll->napi);
  1144. /* CQ intr is enabled while napi_complete,
  1145. * so disable it now
  1146. */
  1147. nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
  1148. nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
  1149. napi_disable(&cq_poll->napi);
  1150. netif_napi_del(&cq_poll->napi);
  1151. }
  1152. netif_tx_disable(netdev);
  1153. for (qidx = 0; qidx < netdev->num_tx_queues; qidx++)
  1154. netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx));
  1155. /* Free resources */
  1156. nicvf_config_data_transfer(nic, false);
  1157. /* Disable HW Qset */
  1158. nicvf_qset_config(nic, false);
  1159. /* disable mailbox interrupt */
  1160. nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
  1161. nicvf_unregister_interrupts(nic);
  1162. nicvf_free_cq_poll(nic);
  1163. /* Free any pending SKB saved to receive timestamp */
  1164. if (nic->ptp_skb) {
  1165. dev_kfree_skb_any(nic->ptp_skb);
  1166. nic->ptp_skb = NULL;
  1167. }
  1168. /* Clear multiqset info */
  1169. nic->pnicvf = nic;
  1170. return 0;
  1171. }
  1172. static int nicvf_config_hw_rx_tstamp(struct nicvf *nic, bool enable)
  1173. {
  1174. union nic_mbx mbx = {};
  1175. mbx.ptp.msg = NIC_MBOX_MSG_PTP_CFG;
  1176. mbx.ptp.enable = enable;
  1177. return nicvf_send_msg_to_pf(nic, &mbx);
  1178. }
  1179. static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
  1180. {
  1181. union nic_mbx mbx = {};
  1182. mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
  1183. mbx.frs.max_frs = mtu;
  1184. mbx.frs.vf_id = nic->vf_id;
  1185. return nicvf_send_msg_to_pf(nic, &mbx);
  1186. }
  1187. int nicvf_open(struct net_device *netdev)
  1188. {
  1189. int cpu, err, qidx;
  1190. struct nicvf *nic = netdev_priv(netdev);
  1191. struct queue_set *qs = nic->qs;
  1192. struct nicvf_cq_poll *cq_poll = NULL;
  1193. union nic_mbx mbx = {};
  1194. netif_carrier_off(netdev);
  1195. err = nicvf_register_misc_interrupt(nic);
  1196. if (err)
  1197. return err;
  1198. /* Register NAPI handler for processing CQEs */
  1199. for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
  1200. cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
  1201. if (!cq_poll) {
  1202. err = -ENOMEM;
  1203. goto napi_del;
  1204. }
  1205. cq_poll->cq_idx = qidx;
  1206. cq_poll->nicvf = nic;
  1207. netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
  1208. NAPI_POLL_WEIGHT);
  1209. napi_enable(&cq_poll->napi);
  1210. nic->napi[qidx] = cq_poll;
  1211. }
  1212. /* Check if we got MAC address from PF or else generate a radom MAC */
  1213. if (!nic->sqs_mode && is_zero_ether_addr(netdev->dev_addr)) {
  1214. eth_hw_addr_random(netdev);
  1215. nicvf_hw_set_mac_addr(nic, netdev);
  1216. }
  1217. if (nic->set_mac_pending) {
  1218. nic->set_mac_pending = false;
  1219. nicvf_hw_set_mac_addr(nic, netdev);
  1220. }
  1221. /* Init tasklet for handling Qset err interrupt */
  1222. tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
  1223. (unsigned long)nic);
  1224. /* Init RBDR tasklet which will refill RBDR */
  1225. tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
  1226. (unsigned long)nic);
  1227. INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
  1228. /* Configure CPI alorithm */
  1229. nic->cpi_alg = cpi_alg;
  1230. if (!nic->sqs_mode)
  1231. nicvf_config_cpi(nic);
  1232. nicvf_request_sqs(nic);
  1233. if (nic->sqs_mode)
  1234. nicvf_get_primary_vf_struct(nic);
  1235. /* Configure PTP timestamp */
  1236. if (nic->ptp_clock)
  1237. nicvf_config_hw_rx_tstamp(nic, nic->hw_rx_tstamp);
  1238. atomic_set(&nic->tx_ptp_skbs, 0);
  1239. nic->ptp_skb = NULL;
  1240. /* Configure receive side scaling and MTU */
  1241. if (!nic->sqs_mode) {
  1242. nicvf_rss_init(nic);
  1243. err = nicvf_update_hw_max_frs(nic, netdev->mtu);
  1244. if (err)
  1245. goto cleanup;
  1246. /* Clear percpu stats */
  1247. for_each_possible_cpu(cpu)
  1248. memset(per_cpu_ptr(nic->drv_stats, cpu), 0,
  1249. sizeof(struct nicvf_drv_stats));
  1250. }
  1251. err = nicvf_register_interrupts(nic);
  1252. if (err)
  1253. goto cleanup;
  1254. /* Initialize the queues */
  1255. err = nicvf_init_resources(nic);
  1256. if (err)
  1257. goto cleanup;
  1258. /* Make sure queue initialization is written */
  1259. wmb();
  1260. nicvf_reg_write(nic, NIC_VF_INT, -1);
  1261. /* Enable Qset err interrupt */
  1262. nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
  1263. /* Enable completion queue interrupt */
  1264. for (qidx = 0; qidx < qs->cq_cnt; qidx++)
  1265. nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
  1266. /* Enable RBDR threshold interrupt */
  1267. for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
  1268. nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
  1269. /* Send VF config done msg to PF */
  1270. mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
  1271. nicvf_write_to_mbx(nic, &mbx);
  1272. return 0;
  1273. cleanup:
  1274. nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
  1275. nicvf_unregister_interrupts(nic);
  1276. tasklet_kill(&nic->qs_err_task);
  1277. tasklet_kill(&nic->rbdr_task);
  1278. napi_del:
  1279. for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
  1280. cq_poll = nic->napi[qidx];
  1281. if (!cq_poll)
  1282. continue;
  1283. napi_disable(&cq_poll->napi);
  1284. netif_napi_del(&cq_poll->napi);
  1285. }
  1286. nicvf_free_cq_poll(nic);
  1287. return err;
  1288. }
  1289. static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
  1290. {
  1291. struct nicvf *nic = netdev_priv(netdev);
  1292. int orig_mtu = netdev->mtu;
  1293. netdev->mtu = new_mtu;
  1294. if (!netif_running(netdev))
  1295. return 0;
  1296. if (nicvf_update_hw_max_frs(nic, new_mtu)) {
  1297. netdev->mtu = orig_mtu;
  1298. return -EINVAL;
  1299. }
  1300. return 0;
  1301. }
  1302. static int nicvf_set_mac_address(struct net_device *netdev, void *p)
  1303. {
  1304. struct sockaddr *addr = p;
  1305. struct nicvf *nic = netdev_priv(netdev);
  1306. if (!is_valid_ether_addr(addr->sa_data))
  1307. return -EADDRNOTAVAIL;
  1308. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1309. if (nic->pdev->msix_enabled) {
  1310. if (nicvf_hw_set_mac_addr(nic, netdev))
  1311. return -EBUSY;
  1312. } else {
  1313. nic->set_mac_pending = true;
  1314. }
  1315. return 0;
  1316. }
  1317. void nicvf_update_lmac_stats(struct nicvf *nic)
  1318. {
  1319. int stat = 0;
  1320. union nic_mbx mbx = {};
  1321. if (!netif_running(nic->netdev))
  1322. return;
  1323. mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
  1324. mbx.bgx_stats.vf_id = nic->vf_id;
  1325. /* Rx stats */
  1326. mbx.bgx_stats.rx = 1;
  1327. while (stat < BGX_RX_STATS_COUNT) {
  1328. mbx.bgx_stats.idx = stat;
  1329. if (nicvf_send_msg_to_pf(nic, &mbx))
  1330. return;
  1331. stat++;
  1332. }
  1333. stat = 0;
  1334. /* Tx stats */
  1335. mbx.bgx_stats.rx = 0;
  1336. while (stat < BGX_TX_STATS_COUNT) {
  1337. mbx.bgx_stats.idx = stat;
  1338. if (nicvf_send_msg_to_pf(nic, &mbx))
  1339. return;
  1340. stat++;
  1341. }
  1342. }
  1343. void nicvf_update_stats(struct nicvf *nic)
  1344. {
  1345. int qidx, cpu;
  1346. u64 tmp_stats = 0;
  1347. struct nicvf_hw_stats *stats = &nic->hw_stats;
  1348. struct nicvf_drv_stats *drv_stats;
  1349. struct queue_set *qs = nic->qs;
  1350. #define GET_RX_STATS(reg) \
  1351. nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
  1352. #define GET_TX_STATS(reg) \
  1353. nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
  1354. stats->rx_bytes = GET_RX_STATS(RX_OCTS);
  1355. stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST);
  1356. stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST);
  1357. stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST);
  1358. stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
  1359. stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
  1360. stats->rx_drop_red = GET_RX_STATS(RX_RED);
  1361. stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS);
  1362. stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
  1363. stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS);
  1364. stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
  1365. stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
  1366. stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
  1367. stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
  1368. stats->tx_bytes = GET_TX_STATS(TX_OCTS);
  1369. stats->tx_ucast_frames = GET_TX_STATS(TX_UCAST);
  1370. stats->tx_bcast_frames = GET_TX_STATS(TX_BCAST);
  1371. stats->tx_mcast_frames = GET_TX_STATS(TX_MCAST);
  1372. stats->tx_drops = GET_TX_STATS(TX_DROP);
  1373. /* On T88 pass 2.0, the dummy SQE added for TSO notification
  1374. * via CQE has 'dont_send' set. Hence HW drops the pkt pointed
  1375. * pointed by dummy SQE and results in tx_drops counter being
  1376. * incremented. Subtracting it from tx_tso counter will give
  1377. * exact tx_drops counter.
  1378. */
  1379. if (nic->t88 && nic->hw_tso) {
  1380. for_each_possible_cpu(cpu) {
  1381. drv_stats = per_cpu_ptr(nic->drv_stats, cpu);
  1382. tmp_stats += drv_stats->tx_tso;
  1383. }
  1384. stats->tx_drops = tmp_stats - stats->tx_drops;
  1385. }
  1386. stats->tx_frames = stats->tx_ucast_frames +
  1387. stats->tx_bcast_frames +
  1388. stats->tx_mcast_frames;
  1389. stats->rx_frames = stats->rx_ucast_frames +
  1390. stats->rx_bcast_frames +
  1391. stats->rx_mcast_frames;
  1392. stats->rx_drops = stats->rx_drop_red +
  1393. stats->rx_drop_overrun;
  1394. /* Update RQ and SQ stats */
  1395. for (qidx = 0; qidx < qs->rq_cnt; qidx++)
  1396. nicvf_update_rq_stats(nic, qidx);
  1397. for (qidx = 0; qidx < qs->sq_cnt; qidx++)
  1398. nicvf_update_sq_stats(nic, qidx);
  1399. }
  1400. static void nicvf_get_stats64(struct net_device *netdev,
  1401. struct rtnl_link_stats64 *stats)
  1402. {
  1403. struct nicvf *nic = netdev_priv(netdev);
  1404. struct nicvf_hw_stats *hw_stats = &nic->hw_stats;
  1405. nicvf_update_stats(nic);
  1406. stats->rx_bytes = hw_stats->rx_bytes;
  1407. stats->rx_packets = hw_stats->rx_frames;
  1408. stats->rx_dropped = hw_stats->rx_drops;
  1409. stats->multicast = hw_stats->rx_mcast_frames;
  1410. stats->tx_bytes = hw_stats->tx_bytes;
  1411. stats->tx_packets = hw_stats->tx_frames;
  1412. stats->tx_dropped = hw_stats->tx_drops;
  1413. }
  1414. static void nicvf_tx_timeout(struct net_device *dev)
  1415. {
  1416. struct nicvf *nic = netdev_priv(dev);
  1417. netif_warn(nic, tx_err, dev, "Transmit timed out, resetting\n");
  1418. this_cpu_inc(nic->drv_stats->tx_timeout);
  1419. schedule_work(&nic->reset_task);
  1420. }
  1421. static void nicvf_reset_task(struct work_struct *work)
  1422. {
  1423. struct nicvf *nic;
  1424. nic = container_of(work, struct nicvf, reset_task);
  1425. if (!netif_running(nic->netdev))
  1426. return;
  1427. nicvf_stop(nic->netdev);
  1428. nicvf_open(nic->netdev);
  1429. netif_trans_update(nic->netdev);
  1430. }
  1431. static int nicvf_config_loopback(struct nicvf *nic,
  1432. netdev_features_t features)
  1433. {
  1434. union nic_mbx mbx = {};
  1435. mbx.lbk.msg = NIC_MBOX_MSG_LOOPBACK;
  1436. mbx.lbk.vf_id = nic->vf_id;
  1437. mbx.lbk.enable = (features & NETIF_F_LOOPBACK) != 0;
  1438. return nicvf_send_msg_to_pf(nic, &mbx);
  1439. }
  1440. static netdev_features_t nicvf_fix_features(struct net_device *netdev,
  1441. netdev_features_t features)
  1442. {
  1443. struct nicvf *nic = netdev_priv(netdev);
  1444. if ((features & NETIF_F_LOOPBACK) &&
  1445. netif_running(netdev) && !nic->loopback_supported)
  1446. features &= ~NETIF_F_LOOPBACK;
  1447. return features;
  1448. }
  1449. static int nicvf_set_features(struct net_device *netdev,
  1450. netdev_features_t features)
  1451. {
  1452. struct nicvf *nic = netdev_priv(netdev);
  1453. netdev_features_t changed = features ^ netdev->features;
  1454. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  1455. nicvf_config_vlan_stripping(nic, features);
  1456. if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev))
  1457. return nicvf_config_loopback(nic, features);
  1458. return 0;
  1459. }
  1460. static void nicvf_set_xdp_queues(struct nicvf *nic, bool bpf_attached)
  1461. {
  1462. u8 cq_count, txq_count;
  1463. /* Set XDP Tx queue count same as Rx queue count */
  1464. if (!bpf_attached)
  1465. nic->xdp_tx_queues = 0;
  1466. else
  1467. nic->xdp_tx_queues = nic->rx_queues;
  1468. /* If queue count > MAX_CMP_QUEUES_PER_QS, then additional qsets
  1469. * needs to be allocated, check how many.
  1470. */
  1471. txq_count = nic->xdp_tx_queues + nic->tx_queues;
  1472. cq_count = max(nic->rx_queues, txq_count);
  1473. if (cq_count > MAX_CMP_QUEUES_PER_QS) {
  1474. nic->sqs_count = roundup(cq_count, MAX_CMP_QUEUES_PER_QS);
  1475. nic->sqs_count = (nic->sqs_count / MAX_CMP_QUEUES_PER_QS) - 1;
  1476. } else {
  1477. nic->sqs_count = 0;
  1478. }
  1479. /* Set primary Qset's resources */
  1480. nic->qs->rq_cnt = min_t(u8, nic->rx_queues, MAX_RCV_QUEUES_PER_QS);
  1481. nic->qs->sq_cnt = min_t(u8, txq_count, MAX_SND_QUEUES_PER_QS);
  1482. nic->qs->cq_cnt = max_t(u8, nic->qs->rq_cnt, nic->qs->sq_cnt);
  1483. /* Update stack */
  1484. nicvf_set_real_num_queues(nic->netdev, nic->tx_queues, nic->rx_queues);
  1485. }
  1486. static int nicvf_xdp_setup(struct nicvf *nic, struct bpf_prog *prog)
  1487. {
  1488. struct net_device *dev = nic->netdev;
  1489. bool if_up = netif_running(nic->netdev);
  1490. struct bpf_prog *old_prog;
  1491. bool bpf_attached = false;
  1492. /* For now just support only the usual MTU sized frames */
  1493. if (prog && (dev->mtu > 1500)) {
  1494. netdev_warn(dev, "Jumbo frames not yet supported with XDP, current MTU %d.\n",
  1495. dev->mtu);
  1496. return -EOPNOTSUPP;
  1497. }
  1498. /* ALL SQs attached to CQs i.e same as RQs, are treated as
  1499. * XDP Tx queues and more Tx queues are allocated for
  1500. * network stack to send pkts out.
  1501. *
  1502. * No of Tx queues are either same as Rx queues or whatever
  1503. * is left in max no of queues possible.
  1504. */
  1505. if ((nic->rx_queues + nic->tx_queues) > nic->max_queues) {
  1506. netdev_warn(dev,
  1507. "Failed to attach BPF prog, RXQs + TXQs > Max %d\n",
  1508. nic->max_queues);
  1509. return -ENOMEM;
  1510. }
  1511. if (if_up)
  1512. nicvf_stop(nic->netdev);
  1513. old_prog = xchg(&nic->xdp_prog, prog);
  1514. /* Detach old prog, if any */
  1515. if (old_prog)
  1516. bpf_prog_put(old_prog);
  1517. if (nic->xdp_prog) {
  1518. /* Attach BPF program */
  1519. nic->xdp_prog = bpf_prog_add(nic->xdp_prog, nic->rx_queues - 1);
  1520. if (!IS_ERR(nic->xdp_prog))
  1521. bpf_attached = true;
  1522. }
  1523. /* Calculate Tx queues needed for XDP and network stack */
  1524. nicvf_set_xdp_queues(nic, bpf_attached);
  1525. if (if_up) {
  1526. /* Reinitialize interface, clean slate */
  1527. nicvf_open(nic->netdev);
  1528. netif_trans_update(nic->netdev);
  1529. }
  1530. return 0;
  1531. }
  1532. static int nicvf_xdp(struct net_device *netdev, struct netdev_bpf *xdp)
  1533. {
  1534. struct nicvf *nic = netdev_priv(netdev);
  1535. /* To avoid checks while retrieving buffer address from CQE_RX,
  1536. * do not support XDP for T88 pass1.x silicons which are anyway
  1537. * not in use widely.
  1538. */
  1539. if (pass1_silicon(nic->pdev))
  1540. return -EOPNOTSUPP;
  1541. switch (xdp->command) {
  1542. case XDP_SETUP_PROG:
  1543. return nicvf_xdp_setup(nic, xdp->prog);
  1544. case XDP_QUERY_PROG:
  1545. xdp->prog_id = nic->xdp_prog ? nic->xdp_prog->aux->id : 0;
  1546. return 0;
  1547. default:
  1548. return -EINVAL;
  1549. }
  1550. }
  1551. static int nicvf_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr)
  1552. {
  1553. struct hwtstamp_config config;
  1554. struct nicvf *nic = netdev_priv(netdev);
  1555. if (!nic->ptp_clock)
  1556. return -ENODEV;
  1557. if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
  1558. return -EFAULT;
  1559. /* reserved for future extensions */
  1560. if (config.flags)
  1561. return -EINVAL;
  1562. switch (config.tx_type) {
  1563. case HWTSTAMP_TX_OFF:
  1564. case HWTSTAMP_TX_ON:
  1565. break;
  1566. default:
  1567. return -ERANGE;
  1568. }
  1569. switch (config.rx_filter) {
  1570. case HWTSTAMP_FILTER_NONE:
  1571. nic->hw_rx_tstamp = false;
  1572. break;
  1573. case HWTSTAMP_FILTER_ALL:
  1574. case HWTSTAMP_FILTER_SOME:
  1575. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  1576. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  1577. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  1578. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  1579. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  1580. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  1581. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  1582. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  1583. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  1584. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  1585. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  1586. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  1587. nic->hw_rx_tstamp = true;
  1588. config.rx_filter = HWTSTAMP_FILTER_ALL;
  1589. break;
  1590. default:
  1591. return -ERANGE;
  1592. }
  1593. if (netif_running(netdev))
  1594. nicvf_config_hw_rx_tstamp(nic, nic->hw_rx_tstamp);
  1595. if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
  1596. return -EFAULT;
  1597. return 0;
  1598. }
  1599. static int nicvf_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
  1600. {
  1601. switch (cmd) {
  1602. case SIOCSHWTSTAMP:
  1603. return nicvf_config_hwtstamp(netdev, req);
  1604. default:
  1605. return -EOPNOTSUPP;
  1606. }
  1607. }
  1608. static void __nicvf_set_rx_mode_task(u8 mode, struct xcast_addr_list *mc_addrs,
  1609. struct nicvf *nic)
  1610. {
  1611. union nic_mbx mbx = {};
  1612. int idx;
  1613. /* From the inside of VM code flow we have only 128 bits memory
  1614. * available to send message to host's PF, so send all mc addrs
  1615. * one by one, starting from flush command in case if kernel
  1616. * requests to configure specific MAC filtering
  1617. */
  1618. /* flush DMAC filters and reset RX mode */
  1619. mbx.xcast.msg = NIC_MBOX_MSG_RESET_XCAST;
  1620. nicvf_send_msg_to_pf(nic, &mbx);
  1621. if (mode & BGX_XCAST_MCAST_FILTER) {
  1622. /* once enabling filtering, we need to signal to PF to add
  1623. * its' own LMAC to the filter to accept packets for it.
  1624. */
  1625. mbx.xcast.msg = NIC_MBOX_MSG_ADD_MCAST;
  1626. mbx.xcast.data.mac = 0;
  1627. nicvf_send_msg_to_pf(nic, &mbx);
  1628. }
  1629. /* check if we have any specific MACs to be added to PF DMAC filter */
  1630. if (mc_addrs) {
  1631. /* now go through kernel list of MACs and add them one by one */
  1632. for (idx = 0; idx < mc_addrs->count; idx++) {
  1633. mbx.xcast.msg = NIC_MBOX_MSG_ADD_MCAST;
  1634. mbx.xcast.data.mac = mc_addrs->mc[idx];
  1635. nicvf_send_msg_to_pf(nic, &mbx);
  1636. }
  1637. kfree(mc_addrs);
  1638. }
  1639. /* and finally set rx mode for PF accordingly */
  1640. mbx.xcast.msg = NIC_MBOX_MSG_SET_XCAST;
  1641. mbx.xcast.data.mode = mode;
  1642. nicvf_send_msg_to_pf(nic, &mbx);
  1643. }
  1644. static void nicvf_set_rx_mode_task(struct work_struct *work_arg)
  1645. {
  1646. struct nicvf_work *vf_work = container_of(work_arg, struct nicvf_work,
  1647. work.work);
  1648. struct nicvf *nic = container_of(vf_work, struct nicvf, rx_mode_work);
  1649. u8 mode;
  1650. struct xcast_addr_list *mc;
  1651. if (!vf_work)
  1652. return;
  1653. /* Save message data locally to prevent them from
  1654. * being overwritten by next ndo_set_rx_mode call().
  1655. */
  1656. spin_lock(&nic->rx_mode_wq_lock);
  1657. mode = vf_work->mode;
  1658. mc = vf_work->mc;
  1659. vf_work->mc = NULL;
  1660. spin_unlock(&nic->rx_mode_wq_lock);
  1661. __nicvf_set_rx_mode_task(mode, mc, nic);
  1662. }
  1663. static void nicvf_set_rx_mode(struct net_device *netdev)
  1664. {
  1665. struct nicvf *nic = netdev_priv(netdev);
  1666. struct netdev_hw_addr *ha;
  1667. struct xcast_addr_list *mc_list = NULL;
  1668. u8 mode = 0;
  1669. if (netdev->flags & IFF_PROMISC) {
  1670. mode = BGX_XCAST_BCAST_ACCEPT | BGX_XCAST_MCAST_ACCEPT;
  1671. } else {
  1672. if (netdev->flags & IFF_BROADCAST)
  1673. mode |= BGX_XCAST_BCAST_ACCEPT;
  1674. if (netdev->flags & IFF_ALLMULTI) {
  1675. mode |= BGX_XCAST_MCAST_ACCEPT;
  1676. } else if (netdev->flags & IFF_MULTICAST) {
  1677. mode |= BGX_XCAST_MCAST_FILTER;
  1678. /* here we need to copy mc addrs */
  1679. if (netdev_mc_count(netdev)) {
  1680. mc_list = kmalloc(offsetof(typeof(*mc_list),
  1681. mc[netdev_mc_count(netdev)]),
  1682. GFP_ATOMIC);
  1683. if (unlikely(!mc_list))
  1684. return;
  1685. mc_list->count = 0;
  1686. netdev_hw_addr_list_for_each(ha, &netdev->mc) {
  1687. mc_list->mc[mc_list->count] =
  1688. ether_addr_to_u64(ha->addr);
  1689. mc_list->count++;
  1690. }
  1691. }
  1692. }
  1693. }
  1694. spin_lock(&nic->rx_mode_wq_lock);
  1695. kfree(nic->rx_mode_work.mc);
  1696. nic->rx_mode_work.mc = mc_list;
  1697. nic->rx_mode_work.mode = mode;
  1698. queue_delayed_work(nicvf_rx_mode_wq, &nic->rx_mode_work.work, 0);
  1699. spin_unlock(&nic->rx_mode_wq_lock);
  1700. }
  1701. static const struct net_device_ops nicvf_netdev_ops = {
  1702. .ndo_open = nicvf_open,
  1703. .ndo_stop = nicvf_stop,
  1704. .ndo_start_xmit = nicvf_xmit,
  1705. .ndo_change_mtu = nicvf_change_mtu,
  1706. .ndo_set_mac_address = nicvf_set_mac_address,
  1707. .ndo_get_stats64 = nicvf_get_stats64,
  1708. .ndo_tx_timeout = nicvf_tx_timeout,
  1709. .ndo_fix_features = nicvf_fix_features,
  1710. .ndo_set_features = nicvf_set_features,
  1711. .ndo_bpf = nicvf_xdp,
  1712. .ndo_do_ioctl = nicvf_ioctl,
  1713. .ndo_set_rx_mode = nicvf_set_rx_mode,
  1714. };
  1715. static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1716. {
  1717. struct device *dev = &pdev->dev;
  1718. struct net_device *netdev;
  1719. struct nicvf *nic;
  1720. int err, qcount;
  1721. u16 sdevid;
  1722. struct cavium_ptp *ptp_clock;
  1723. ptp_clock = cavium_ptp_get();
  1724. if (IS_ERR(ptp_clock)) {
  1725. if (PTR_ERR(ptp_clock) == -ENODEV)
  1726. /* In virtualized environment we proceed without ptp */
  1727. ptp_clock = NULL;
  1728. else
  1729. return PTR_ERR(ptp_clock);
  1730. }
  1731. err = pci_enable_device(pdev);
  1732. if (err) {
  1733. dev_err(dev, "Failed to enable PCI device\n");
  1734. return err;
  1735. }
  1736. err = pci_request_regions(pdev, DRV_NAME);
  1737. if (err) {
  1738. dev_err(dev, "PCI request regions failed 0x%x\n", err);
  1739. goto err_disable_device;
  1740. }
  1741. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
  1742. if (err) {
  1743. dev_err(dev, "Unable to get usable DMA configuration\n");
  1744. goto err_release_regions;
  1745. }
  1746. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
  1747. if (err) {
  1748. dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
  1749. goto err_release_regions;
  1750. }
  1751. qcount = netif_get_num_default_rss_queues();
  1752. /* Restrict multiqset support only for host bound VFs */
  1753. if (pdev->is_virtfn) {
  1754. /* Set max number of queues per VF */
  1755. qcount = min_t(int, num_online_cpus(),
  1756. (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS);
  1757. }
  1758. netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount);
  1759. if (!netdev) {
  1760. err = -ENOMEM;
  1761. goto err_release_regions;
  1762. }
  1763. pci_set_drvdata(pdev, netdev);
  1764. SET_NETDEV_DEV(netdev, &pdev->dev);
  1765. nic = netdev_priv(netdev);
  1766. nic->netdev = netdev;
  1767. nic->pdev = pdev;
  1768. nic->pnicvf = nic;
  1769. nic->max_queues = qcount;
  1770. /* If no of CPUs are too low, there won't be any queues left
  1771. * for XDP_TX, hence double it.
  1772. */
  1773. if (!nic->t88)
  1774. nic->max_queues *= 2;
  1775. nic->ptp_clock = ptp_clock;
  1776. /* MAP VF's configuration registers */
  1777. nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
  1778. if (!nic->reg_base) {
  1779. dev_err(dev, "Cannot map config register space, aborting\n");
  1780. err = -ENOMEM;
  1781. goto err_free_netdev;
  1782. }
  1783. nic->drv_stats = netdev_alloc_pcpu_stats(struct nicvf_drv_stats);
  1784. if (!nic->drv_stats) {
  1785. err = -ENOMEM;
  1786. goto err_free_netdev;
  1787. }
  1788. err = nicvf_set_qset_resources(nic);
  1789. if (err)
  1790. goto err_free_netdev;
  1791. /* Check if PF is alive and get MAC address for this VF */
  1792. err = nicvf_register_misc_interrupt(nic);
  1793. if (err)
  1794. goto err_free_netdev;
  1795. nicvf_send_vf_struct(nic);
  1796. if (!pass1_silicon(nic->pdev))
  1797. nic->hw_tso = true;
  1798. /* Get iommu domain for iova to physical addr conversion */
  1799. nic->iommu_domain = iommu_get_domain_for_dev(dev);
  1800. pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
  1801. if (sdevid == 0xA134)
  1802. nic->t88 = true;
  1803. /* Check if this VF is in QS only mode */
  1804. if (nic->sqs_mode)
  1805. return 0;
  1806. err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues);
  1807. if (err)
  1808. goto err_unregister_interrupts;
  1809. netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_SG |
  1810. NETIF_F_TSO | NETIF_F_GRO | NETIF_F_TSO6 |
  1811. NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1812. NETIF_F_HW_VLAN_CTAG_RX);
  1813. netdev->hw_features |= NETIF_F_RXHASH;
  1814. netdev->features |= netdev->hw_features;
  1815. netdev->hw_features |= NETIF_F_LOOPBACK;
  1816. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  1817. NETIF_F_IPV6_CSUM | NETIF_F_TSO | NETIF_F_TSO6;
  1818. netdev->netdev_ops = &nicvf_netdev_ops;
  1819. netdev->watchdog_timeo = NICVF_TX_TIMEOUT;
  1820. /* MTU range: 64 - 9200 */
  1821. netdev->min_mtu = NIC_HW_MIN_FRS;
  1822. netdev->max_mtu = NIC_HW_MAX_FRS;
  1823. INIT_WORK(&nic->reset_task, nicvf_reset_task);
  1824. INIT_DELAYED_WORK(&nic->rx_mode_work.work, nicvf_set_rx_mode_task);
  1825. spin_lock_init(&nic->rx_mode_wq_lock);
  1826. err = register_netdev(netdev);
  1827. if (err) {
  1828. dev_err(dev, "Failed to register netdevice\n");
  1829. goto err_unregister_interrupts;
  1830. }
  1831. nic->msg_enable = debug;
  1832. nicvf_set_ethtool_ops(netdev);
  1833. return 0;
  1834. err_unregister_interrupts:
  1835. nicvf_unregister_interrupts(nic);
  1836. err_free_netdev:
  1837. pci_set_drvdata(pdev, NULL);
  1838. if (nic->drv_stats)
  1839. free_percpu(nic->drv_stats);
  1840. free_netdev(netdev);
  1841. err_release_regions:
  1842. pci_release_regions(pdev);
  1843. err_disable_device:
  1844. pci_disable_device(pdev);
  1845. return err;
  1846. }
  1847. static void nicvf_remove(struct pci_dev *pdev)
  1848. {
  1849. struct net_device *netdev = pci_get_drvdata(pdev);
  1850. struct nicvf *nic;
  1851. struct net_device *pnetdev;
  1852. if (!netdev)
  1853. return;
  1854. nic = netdev_priv(netdev);
  1855. pnetdev = nic->pnicvf->netdev;
  1856. cancel_delayed_work_sync(&nic->rx_mode_work.work);
  1857. /* Check if this Qset is assigned to different VF.
  1858. * If yes, clean primary and all secondary Qsets.
  1859. */
  1860. if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED))
  1861. unregister_netdev(pnetdev);
  1862. nicvf_unregister_interrupts(nic);
  1863. pci_set_drvdata(pdev, NULL);
  1864. if (nic->drv_stats)
  1865. free_percpu(nic->drv_stats);
  1866. cavium_ptp_put(nic->ptp_clock);
  1867. free_netdev(netdev);
  1868. pci_release_regions(pdev);
  1869. pci_disable_device(pdev);
  1870. }
  1871. static void nicvf_shutdown(struct pci_dev *pdev)
  1872. {
  1873. nicvf_remove(pdev);
  1874. }
  1875. static struct pci_driver nicvf_driver = {
  1876. .name = DRV_NAME,
  1877. .id_table = nicvf_id_table,
  1878. .probe = nicvf_probe,
  1879. .remove = nicvf_remove,
  1880. .shutdown = nicvf_shutdown,
  1881. };
  1882. static int __init nicvf_init_module(void)
  1883. {
  1884. pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
  1885. nicvf_rx_mode_wq = alloc_ordered_workqueue("nicvf_generic",
  1886. WQ_MEM_RECLAIM);
  1887. return pci_register_driver(&nicvf_driver);
  1888. }
  1889. static void __exit nicvf_cleanup_module(void)
  1890. {
  1891. if (nicvf_rx_mode_wq) {
  1892. destroy_workqueue(nicvf_rx_mode_wq);
  1893. nicvf_rx_mode_wq = NULL;
  1894. }
  1895. pci_unregister_driver(&nicvf_driver);
  1896. }
  1897. module_init(nicvf_init_module);
  1898. module_exit(nicvf_cleanup_module);