sdhci-acpi.c 21 KB

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  1. /*
  2. * Secure Digital Host Controller Interface ACPI driver.
  3. *
  4. * Copyright (c) 2012, Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. */
  20. #include <linux/init.h>
  21. #include <linux/export.h>
  22. #include <linux/module.h>
  23. #include <linux/device.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/ioport.h>
  26. #include <linux/io.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/compiler.h>
  29. #include <linux/stddef.h>
  30. #include <linux/bitops.h>
  31. #include <linux/types.h>
  32. #include <linux/err.h>
  33. #include <linux/interrupt.h>
  34. #include <linux/acpi.h>
  35. #include <linux/pm.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/delay.h>
  38. #include <linux/mmc/host.h>
  39. #include <linux/mmc/pm.h>
  40. #include <linux/mmc/slot-gpio.h>
  41. #ifdef CONFIG_X86
  42. #include <asm/cpu_device_id.h>
  43. #include <asm/intel-family.h>
  44. #include <asm/iosf_mbi.h>
  45. #include <linux/pci.h>
  46. #endif
  47. #include "sdhci.h"
  48. enum {
  49. SDHCI_ACPI_SD_CD = BIT(0),
  50. SDHCI_ACPI_RUNTIME_PM = BIT(1),
  51. SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
  52. };
  53. struct sdhci_acpi_chip {
  54. const struct sdhci_ops *ops;
  55. unsigned int quirks;
  56. unsigned int quirks2;
  57. unsigned long caps;
  58. unsigned int caps2;
  59. mmc_pm_flag_t pm_caps;
  60. };
  61. struct sdhci_acpi_slot {
  62. const struct sdhci_acpi_chip *chip;
  63. unsigned int quirks;
  64. unsigned int quirks2;
  65. unsigned long caps;
  66. unsigned int caps2;
  67. mmc_pm_flag_t pm_caps;
  68. unsigned int flags;
  69. size_t priv_size;
  70. int (*probe_slot)(struct platform_device *, const char *, const char *);
  71. int (*remove_slot)(struct platform_device *);
  72. int (*setup_host)(struct platform_device *pdev);
  73. };
  74. struct sdhci_acpi_host {
  75. struct sdhci_host *host;
  76. const struct sdhci_acpi_slot *slot;
  77. struct platform_device *pdev;
  78. bool use_runtime_pm;
  79. unsigned long private[0] ____cacheline_aligned;
  80. };
  81. static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
  82. {
  83. return (void *)c->private;
  84. }
  85. static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
  86. {
  87. return c->slot && (c->slot->flags & flag);
  88. }
  89. #define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
  90. #define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
  91. #define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
  92. #define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
  93. enum {
  94. INTEL_DSM_FNS = 0,
  95. INTEL_DSM_V18_SWITCH = 3,
  96. INTEL_DSM_V33_SWITCH = 4,
  97. INTEL_DSM_HS_CAPS = 8,
  98. };
  99. struct intel_host {
  100. u32 dsm_fns;
  101. u32 hs_caps;
  102. };
  103. static const guid_t intel_dsm_guid =
  104. GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
  105. 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
  106. static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
  107. unsigned int fn, u32 *result)
  108. {
  109. union acpi_object *obj;
  110. int err = 0;
  111. obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
  112. if (!obj)
  113. return -EOPNOTSUPP;
  114. if (obj->type == ACPI_TYPE_INTEGER) {
  115. *result = obj->integer.value;
  116. } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
  117. size_t len = min_t(size_t, obj->buffer.length, 4);
  118. *result = 0;
  119. memcpy(result, obj->buffer.pointer, len);
  120. } else {
  121. dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
  122. __func__, fn, obj->type, obj->buffer.length);
  123. err = -EINVAL;
  124. }
  125. ACPI_FREE(obj);
  126. return err;
  127. }
  128. static int intel_dsm(struct intel_host *intel_host, struct device *dev,
  129. unsigned int fn, u32 *result)
  130. {
  131. if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
  132. return -EOPNOTSUPP;
  133. return __intel_dsm(intel_host, dev, fn, result);
  134. }
  135. static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
  136. struct mmc_host *mmc)
  137. {
  138. int err;
  139. intel_host->hs_caps = ~0;
  140. err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
  141. if (err) {
  142. pr_debug("%s: DSM not supported, error %d\n",
  143. mmc_hostname(mmc), err);
  144. return;
  145. }
  146. pr_debug("%s: DSM function mask %#x\n",
  147. mmc_hostname(mmc), intel_host->dsm_fns);
  148. intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
  149. }
  150. static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
  151. struct mmc_ios *ios)
  152. {
  153. struct device *dev = mmc_dev(mmc);
  154. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  155. struct intel_host *intel_host = sdhci_acpi_priv(c);
  156. unsigned int fn;
  157. u32 result = 0;
  158. int err;
  159. err = sdhci_start_signal_voltage_switch(mmc, ios);
  160. if (err)
  161. return err;
  162. switch (ios->signal_voltage) {
  163. case MMC_SIGNAL_VOLTAGE_330:
  164. fn = INTEL_DSM_V33_SWITCH;
  165. break;
  166. case MMC_SIGNAL_VOLTAGE_180:
  167. fn = INTEL_DSM_V18_SWITCH;
  168. break;
  169. default:
  170. return 0;
  171. }
  172. err = intel_dsm(intel_host, dev, fn, &result);
  173. pr_debug("%s: %s DSM fn %u error %d result %u\n",
  174. mmc_hostname(mmc), __func__, fn, err, result);
  175. return 0;
  176. }
  177. static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
  178. {
  179. u8 reg;
  180. reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
  181. reg |= 0x10;
  182. sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
  183. /* For eMMC, minimum is 1us but give it 9us for good measure */
  184. udelay(9);
  185. reg &= ~0x10;
  186. sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
  187. /* For eMMC, minimum is 200us but give it 300us for good measure */
  188. usleep_range(300, 1000);
  189. }
  190. static const struct sdhci_ops sdhci_acpi_ops_dflt = {
  191. .set_clock = sdhci_set_clock,
  192. .set_bus_width = sdhci_set_bus_width,
  193. .reset = sdhci_reset,
  194. .set_uhs_signaling = sdhci_set_uhs_signaling,
  195. };
  196. static const struct sdhci_ops sdhci_acpi_ops_int = {
  197. .set_clock = sdhci_set_clock,
  198. .set_bus_width = sdhci_set_bus_width,
  199. .reset = sdhci_reset,
  200. .set_uhs_signaling = sdhci_set_uhs_signaling,
  201. .hw_reset = sdhci_acpi_int_hw_reset,
  202. };
  203. static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
  204. .ops = &sdhci_acpi_ops_int,
  205. };
  206. #ifdef CONFIG_X86
  207. static bool sdhci_acpi_byt(void)
  208. {
  209. static const struct x86_cpu_id byt[] = {
  210. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
  211. {}
  212. };
  213. return x86_match_cpu(byt);
  214. }
  215. static bool sdhci_acpi_cht(void)
  216. {
  217. static const struct x86_cpu_id cht[] = {
  218. { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
  219. {}
  220. };
  221. return x86_match_cpu(cht);
  222. }
  223. #define BYT_IOSF_SCCEP 0x63
  224. #define BYT_IOSF_OCP_NETCTRL0 0x1078
  225. #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
  226. static void sdhci_acpi_byt_setting(struct device *dev)
  227. {
  228. u32 val = 0;
  229. if (!sdhci_acpi_byt())
  230. return;
  231. if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
  232. &val)) {
  233. dev_err(dev, "%s read error\n", __func__);
  234. return;
  235. }
  236. if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
  237. return;
  238. val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
  239. if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
  240. val)) {
  241. dev_err(dev, "%s write error\n", __func__);
  242. return;
  243. }
  244. dev_dbg(dev, "%s completed\n", __func__);
  245. }
  246. static bool sdhci_acpi_byt_defer(struct device *dev)
  247. {
  248. if (!sdhci_acpi_byt())
  249. return false;
  250. if (!iosf_mbi_available())
  251. return true;
  252. sdhci_acpi_byt_setting(dev);
  253. return false;
  254. }
  255. static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
  256. unsigned int slot, unsigned int parent_slot)
  257. {
  258. struct pci_dev *dev, *parent, *from = NULL;
  259. while (1) {
  260. dev = pci_get_device(vendor, device, from);
  261. pci_dev_put(from);
  262. if (!dev)
  263. break;
  264. parent = pci_upstream_bridge(dev);
  265. if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
  266. parent && PCI_SLOT(parent->devfn) == parent_slot &&
  267. !pci_upstream_bridge(parent)) {
  268. pci_dev_put(dev);
  269. return true;
  270. }
  271. from = dev;
  272. }
  273. return false;
  274. }
  275. /*
  276. * GPDwin uses PCI wifi which conflicts with SDIO's use of
  277. * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is
  278. * problematic, but since SDIO is only used for wifi, the presence of the PCI
  279. * wifi card in the expected slot with an ACPI companion node, is used to
  280. * indicate that acpi_device_fix_up_power() should be avoided.
  281. */
  282. static inline bool sdhci_acpi_no_fixup_child_power(const char *hid,
  283. const char *uid)
  284. {
  285. return sdhci_acpi_cht() &&
  286. !strcmp(hid, "80860F14") &&
  287. !strcmp(uid, "2") &&
  288. sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
  289. }
  290. #else
  291. static inline void sdhci_acpi_byt_setting(struct device *dev)
  292. {
  293. }
  294. static inline bool sdhci_acpi_byt_defer(struct device *dev)
  295. {
  296. return false;
  297. }
  298. static inline bool sdhci_acpi_no_fixup_child_power(const char *hid,
  299. const char *uid)
  300. {
  301. return false;
  302. }
  303. #endif
  304. static int bxt_get_cd(struct mmc_host *mmc)
  305. {
  306. int gpio_cd = mmc_gpio_get_cd(mmc);
  307. struct sdhci_host *host = mmc_priv(mmc);
  308. unsigned long flags;
  309. int ret = 0;
  310. if (!gpio_cd)
  311. return 0;
  312. spin_lock_irqsave(&host->lock, flags);
  313. if (host->flags & SDHCI_DEVICE_DEAD)
  314. goto out;
  315. ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
  316. out:
  317. spin_unlock_irqrestore(&host->lock, flags);
  318. return ret;
  319. }
  320. static int intel_probe_slot(struct platform_device *pdev, const char *hid,
  321. const char *uid)
  322. {
  323. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  324. struct intel_host *intel_host = sdhci_acpi_priv(c);
  325. struct sdhci_host *host = c->host;
  326. if (hid && uid && !strcmp(hid, "80860F14") && !strcmp(uid, "1") &&
  327. sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
  328. sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
  329. host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
  330. if (hid && !strcmp(hid, "80865ACA"))
  331. host->mmc_host_ops.get_cd = bxt_get_cd;
  332. intel_dsm_init(intel_host, &pdev->dev, host->mmc);
  333. host->mmc_host_ops.start_signal_voltage_switch =
  334. intel_start_signal_voltage_switch;
  335. return 0;
  336. }
  337. static int intel_setup_host(struct platform_device *pdev)
  338. {
  339. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  340. struct intel_host *intel_host = sdhci_acpi_priv(c);
  341. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
  342. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
  343. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
  344. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
  345. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
  346. c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
  347. if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
  348. c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
  349. return 0;
  350. }
  351. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
  352. .chip = &sdhci_acpi_chip_int,
  353. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
  354. MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
  355. MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
  356. .flags = SDHCI_ACPI_RUNTIME_PM,
  357. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  358. .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
  359. SDHCI_QUIRK2_STOP_WITH_TC |
  360. SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
  361. .probe_slot = intel_probe_slot,
  362. .setup_host = intel_setup_host,
  363. .priv_size = sizeof(struct intel_host),
  364. };
  365. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
  366. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
  367. SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  368. .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
  369. .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
  370. MMC_CAP_WAIT_WHILE_BUSY,
  371. .flags = SDHCI_ACPI_RUNTIME_PM,
  372. .pm_caps = MMC_PM_KEEP_POWER,
  373. .probe_slot = intel_probe_slot,
  374. .setup_host = intel_setup_host,
  375. .priv_size = sizeof(struct intel_host),
  376. };
  377. static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
  378. .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
  379. SDHCI_ACPI_RUNTIME_PM,
  380. .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
  381. .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
  382. SDHCI_QUIRK2_STOP_WITH_TC,
  383. .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
  384. .probe_slot = intel_probe_slot,
  385. .setup_host = intel_setup_host,
  386. .priv_size = sizeof(struct intel_host),
  387. };
  388. static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
  389. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  390. .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
  391. .caps = MMC_CAP_NONREMOVABLE,
  392. };
  393. static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
  394. .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
  395. .caps = MMC_CAP_NONREMOVABLE,
  396. };
  397. /* AMD sdhci reset dll register. */
  398. #define SDHCI_AMD_RESET_DLL_REGISTER 0x908
  399. static int amd_select_drive_strength(struct mmc_card *card,
  400. unsigned int max_dtr, int host_drv,
  401. int card_drv, int *drv_type)
  402. {
  403. return MMC_SET_DRIVER_TYPE_A;
  404. }
  405. static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host)
  406. {
  407. /* AMD Platform requires dll setting */
  408. sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
  409. usleep_range(10, 20);
  410. sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
  411. }
  412. /*
  413. * For AMD Platform it is required to disable the tuning
  414. * bit first controller to bring to HS Mode from HS200
  415. * mode, later enable to tune to HS400 mode.
  416. */
  417. static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  418. {
  419. struct sdhci_host *host = mmc_priv(mmc);
  420. unsigned int old_timing = host->timing;
  421. sdhci_set_ios(mmc, ios);
  422. if (old_timing == MMC_TIMING_MMC_HS200 &&
  423. ios->timing == MMC_TIMING_MMC_HS)
  424. sdhci_writew(host, 0x9, SDHCI_HOST_CONTROL2);
  425. if (old_timing != MMC_TIMING_MMC_HS400 &&
  426. ios->timing == MMC_TIMING_MMC_HS400) {
  427. sdhci_writew(host, 0x80, SDHCI_HOST_CONTROL2);
  428. sdhci_acpi_amd_hs400_dll(host);
  429. }
  430. }
  431. static const struct sdhci_ops sdhci_acpi_ops_amd = {
  432. .set_clock = sdhci_set_clock,
  433. .set_bus_width = sdhci_set_bus_width,
  434. .reset = sdhci_reset,
  435. .set_uhs_signaling = sdhci_set_uhs_signaling,
  436. };
  437. static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
  438. .ops = &sdhci_acpi_ops_amd,
  439. };
  440. static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
  441. const char *hid, const char *uid)
  442. {
  443. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  444. struct sdhci_host *host = c->host;
  445. sdhci_read_caps(host);
  446. if (host->caps1 & SDHCI_SUPPORT_DDR50)
  447. host->mmc->caps = MMC_CAP_1_8V_DDR;
  448. if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
  449. (host->mmc->caps & MMC_CAP_1_8V_DDR))
  450. host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
  451. host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
  452. host->mmc_host_ops.set_ios = amd_set_ios;
  453. return 0;
  454. }
  455. static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
  456. .chip = &sdhci_acpi_chip_amd,
  457. .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
  458. .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE |
  459. SDHCI_QUIRK_32BIT_ADMA_SIZE,
  460. .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
  461. };
  462. struct sdhci_acpi_uid_slot {
  463. const char *hid;
  464. const char *uid;
  465. const struct sdhci_acpi_slot *slot;
  466. };
  467. static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
  468. { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
  469. { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
  470. { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
  471. { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
  472. { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
  473. { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
  474. { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
  475. { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
  476. { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
  477. { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
  478. { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
  479. { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
  480. { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
  481. { "PNP0D40" },
  482. { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
  483. { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
  484. { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
  485. { },
  486. };
  487. static const struct acpi_device_id sdhci_acpi_ids[] = {
  488. { "80865ACA" },
  489. { "80865ACC" },
  490. { "80865AD0" },
  491. { "80860F14" },
  492. { "80860F16" },
  493. { "INT33BB" },
  494. { "INT33C6" },
  495. { "INT3436" },
  496. { "INT344D" },
  497. { "PNP0D40" },
  498. { "QCOM8051" },
  499. { "QCOM8052" },
  500. { "AMDI0040" },
  501. { },
  502. };
  503. MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
  504. static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid,
  505. const char *uid)
  506. {
  507. const struct sdhci_acpi_uid_slot *u;
  508. for (u = sdhci_acpi_uids; u->hid; u++) {
  509. if (strcmp(u->hid, hid))
  510. continue;
  511. if (!u->uid)
  512. return u->slot;
  513. if (uid && !strcmp(u->uid, uid))
  514. return u->slot;
  515. }
  516. return NULL;
  517. }
  518. static int sdhci_acpi_probe(struct platform_device *pdev)
  519. {
  520. struct device *dev = &pdev->dev;
  521. const struct sdhci_acpi_slot *slot;
  522. struct acpi_device *device, *child;
  523. struct sdhci_acpi_host *c;
  524. struct sdhci_host *host;
  525. struct resource *iomem;
  526. resource_size_t len;
  527. size_t priv_size;
  528. const char *hid;
  529. const char *uid;
  530. int err;
  531. device = ACPI_COMPANION(dev);
  532. if (!device)
  533. return -ENODEV;
  534. hid = acpi_device_hid(device);
  535. uid = acpi_device_uid(device);
  536. slot = sdhci_acpi_get_slot(hid, uid);
  537. /* Power on the SDHCI controller and its children */
  538. acpi_device_fix_up_power(device);
  539. if (!sdhci_acpi_no_fixup_child_power(hid, uid)) {
  540. list_for_each_entry(child, &device->children, node)
  541. if (child->status.present && child->status.enabled)
  542. acpi_device_fix_up_power(child);
  543. }
  544. if (sdhci_acpi_byt_defer(dev))
  545. return -EPROBE_DEFER;
  546. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  547. if (!iomem)
  548. return -ENOMEM;
  549. len = resource_size(iomem);
  550. if (len < 0x100)
  551. dev_err(dev, "Invalid iomem size!\n");
  552. if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
  553. return -ENOMEM;
  554. priv_size = slot ? slot->priv_size : 0;
  555. host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
  556. if (IS_ERR(host))
  557. return PTR_ERR(host);
  558. c = sdhci_priv(host);
  559. c->host = host;
  560. c->slot = slot;
  561. c->pdev = pdev;
  562. c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
  563. platform_set_drvdata(pdev, c);
  564. host->hw_name = "ACPI";
  565. host->ops = &sdhci_acpi_ops_dflt;
  566. host->irq = platform_get_irq(pdev, 0);
  567. if (host->irq < 0) {
  568. err = -EINVAL;
  569. goto err_free;
  570. }
  571. host->ioaddr = devm_ioremap_nocache(dev, iomem->start,
  572. resource_size(iomem));
  573. if (host->ioaddr == NULL) {
  574. err = -ENOMEM;
  575. goto err_free;
  576. }
  577. if (c->slot) {
  578. if (c->slot->probe_slot) {
  579. err = c->slot->probe_slot(pdev, hid, uid);
  580. if (err)
  581. goto err_free;
  582. }
  583. if (c->slot->chip) {
  584. host->ops = c->slot->chip->ops;
  585. host->quirks |= c->slot->chip->quirks;
  586. host->quirks2 |= c->slot->chip->quirks2;
  587. host->mmc->caps |= c->slot->chip->caps;
  588. host->mmc->caps2 |= c->slot->chip->caps2;
  589. host->mmc->pm_caps |= c->slot->chip->pm_caps;
  590. }
  591. host->quirks |= c->slot->quirks;
  592. host->quirks2 |= c->slot->quirks2;
  593. host->mmc->caps |= c->slot->caps;
  594. host->mmc->caps2 |= c->slot->caps2;
  595. host->mmc->pm_caps |= c->slot->pm_caps;
  596. }
  597. host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
  598. if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
  599. bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
  600. err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0, NULL);
  601. if (err) {
  602. if (err == -EPROBE_DEFER)
  603. goto err_free;
  604. dev_warn(dev, "failed to setup card detect gpio\n");
  605. c->use_runtime_pm = false;
  606. }
  607. }
  608. err = sdhci_setup_host(host);
  609. if (err)
  610. goto err_free;
  611. if (c->slot && c->slot->setup_host) {
  612. err = c->slot->setup_host(pdev);
  613. if (err)
  614. goto err_cleanup;
  615. }
  616. err = __sdhci_add_host(host);
  617. if (err)
  618. goto err_cleanup;
  619. if (c->use_runtime_pm) {
  620. pm_runtime_set_active(dev);
  621. pm_suspend_ignore_children(dev, 1);
  622. pm_runtime_set_autosuspend_delay(dev, 50);
  623. pm_runtime_use_autosuspend(dev);
  624. pm_runtime_enable(dev);
  625. }
  626. device_enable_async_suspend(dev);
  627. return 0;
  628. err_cleanup:
  629. sdhci_cleanup_host(c->host);
  630. err_free:
  631. sdhci_free_host(c->host);
  632. return err;
  633. }
  634. static int sdhci_acpi_remove(struct platform_device *pdev)
  635. {
  636. struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
  637. struct device *dev = &pdev->dev;
  638. int dead;
  639. if (c->use_runtime_pm) {
  640. pm_runtime_get_sync(dev);
  641. pm_runtime_disable(dev);
  642. pm_runtime_put_noidle(dev);
  643. }
  644. if (c->slot && c->slot->remove_slot)
  645. c->slot->remove_slot(pdev);
  646. dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
  647. sdhci_remove_host(c->host, dead);
  648. sdhci_free_host(c->host);
  649. return 0;
  650. }
  651. #ifdef CONFIG_PM_SLEEP
  652. static int sdhci_acpi_suspend(struct device *dev)
  653. {
  654. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  655. struct sdhci_host *host = c->host;
  656. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  657. mmc_retune_needed(host->mmc);
  658. return sdhci_suspend_host(host);
  659. }
  660. static int sdhci_acpi_resume(struct device *dev)
  661. {
  662. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  663. sdhci_acpi_byt_setting(&c->pdev->dev);
  664. return sdhci_resume_host(c->host);
  665. }
  666. #endif
  667. #ifdef CONFIG_PM
  668. static int sdhci_acpi_runtime_suspend(struct device *dev)
  669. {
  670. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  671. struct sdhci_host *host = c->host;
  672. if (host->tuning_mode != SDHCI_TUNING_MODE_3)
  673. mmc_retune_needed(host->mmc);
  674. return sdhci_runtime_suspend_host(host);
  675. }
  676. static int sdhci_acpi_runtime_resume(struct device *dev)
  677. {
  678. struct sdhci_acpi_host *c = dev_get_drvdata(dev);
  679. sdhci_acpi_byt_setting(&c->pdev->dev);
  680. return sdhci_runtime_resume_host(c->host);
  681. }
  682. #endif
  683. static const struct dev_pm_ops sdhci_acpi_pm_ops = {
  684. SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
  685. SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
  686. sdhci_acpi_runtime_resume, NULL)
  687. };
  688. static struct platform_driver sdhci_acpi_driver = {
  689. .driver = {
  690. .name = "sdhci-acpi",
  691. .acpi_match_table = sdhci_acpi_ids,
  692. .pm = &sdhci_acpi_pm_ops,
  693. },
  694. .probe = sdhci_acpi_probe,
  695. .remove = sdhci_acpi_remove,
  696. };
  697. module_platform_driver(sdhci_acpi_driver);
  698. MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
  699. MODULE_AUTHOR("Adrian Hunter");
  700. MODULE_LICENSE("GPL v2");