renesas_sdhi_sys_dmac.c 15 KB

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  1. /*
  2. * DMA support use of SYS DMAC with SDHI SD/SDIO controller
  3. *
  4. * Copyright (C) 2016-17 Renesas Electronics Corporation
  5. * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
  6. * Copyright (C) 2017 Horms Solutions, Simon Horman
  7. * Copyright (C) 2010-2011 Guennadi Liakhovetski
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/device.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmaengine.h>
  16. #include <linux/mfd/tmio.h>
  17. #include <linux/mmc/host.h>
  18. #include <linux/mod_devicetable.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/pagemap.h>
  22. #include <linux/scatterlist.h>
  23. #include <linux/sys_soc.h>
  24. #include "renesas_sdhi.h"
  25. #include "tmio_mmc.h"
  26. #define TMIO_MMC_MIN_DMA_LEN 8
  27. static const struct renesas_sdhi_of_data of_default_cfg = {
  28. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  29. };
  30. static const struct renesas_sdhi_of_data of_rz_compatible = {
  31. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_32BIT_DATA_PORT |
  32. TMIO_MMC_HAVE_CBSY,
  33. .tmio_ocr_mask = MMC_VDD_32_33,
  34. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  35. };
  36. static const struct renesas_sdhi_of_data of_rcar_gen1_compatible = {
  37. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL,
  38. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
  39. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  40. };
  41. /* Definitions for sampling clocks */
  42. static struct renesas_sdhi_scc rcar_gen2_scc_taps[] = {
  43. {
  44. .clk_rate = 156000000,
  45. .tap = 0x00000703,
  46. },
  47. {
  48. .clk_rate = 0,
  49. .tap = 0x00000300,
  50. },
  51. };
  52. static const struct renesas_sdhi_of_data of_rcar_gen2_compatible = {
  53. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  54. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  55. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  56. MMC_CAP_CMD23,
  57. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  58. .dma_buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES,
  59. .dma_rx_offset = 0x2000,
  60. .scc_offset = 0x0300,
  61. .taps = rcar_gen2_scc_taps,
  62. .taps_num = ARRAY_SIZE(rcar_gen2_scc_taps),
  63. };
  64. /* Definitions for sampling clocks */
  65. static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  66. {
  67. .clk_rate = 0,
  68. .tap = 0x00000300,
  69. },
  70. };
  71. static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
  72. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  73. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
  74. TMIO_MMC_HAVE_4TAP_HS400,
  75. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  76. MMC_CAP_CMD23,
  77. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  78. .bus_shift = 2,
  79. .scc_offset = 0x1000,
  80. .taps = rcar_gen3_scc_taps,
  81. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  82. };
  83. static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
  84. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  85. TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
  86. .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  87. MMC_CAP_CMD23,
  88. .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT,
  89. .bus_shift = 2,
  90. .scc_offset = 0x1000,
  91. .taps = rcar_gen3_scc_taps,
  92. .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps),
  93. };
  94. static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
  95. { .compatible = "renesas,sdhi-sh73a0", .data = &of_default_cfg, },
  96. { .compatible = "renesas,sdhi-r8a73a4", .data = &of_default_cfg, },
  97. { .compatible = "renesas,sdhi-r8a7740", .data = &of_default_cfg, },
  98. { .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
  99. { .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
  100. { .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
  101. { .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
  102. { .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
  103. { .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
  104. { .compatible = "renesas,sdhi-r8a7791", .data = &of_rcar_gen2_compatible, },
  105. { .compatible = "renesas,sdhi-r8a7792", .data = &of_rcar_gen2_compatible, },
  106. { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, },
  107. { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, },
  108. { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, },
  109. { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, },
  110. { .compatible = "renesas,rcar-gen1-sdhi", .data = &of_rcar_gen1_compatible, },
  111. { .compatible = "renesas,rcar-gen2-sdhi", .data = &of_rcar_gen2_compatible, },
  112. { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
  113. { .compatible = "renesas,sdhi-shmobile" },
  114. {},
  115. };
  116. MODULE_DEVICE_TABLE(of, renesas_sdhi_sys_dmac_of_match);
  117. static void renesas_sdhi_sys_dmac_enable_dma(struct tmio_mmc_host *host,
  118. bool enable)
  119. {
  120. struct renesas_sdhi *priv = host_to_priv(host);
  121. if (!host->chan_tx || !host->chan_rx)
  122. return;
  123. if (priv->dma_priv.enable)
  124. priv->dma_priv.enable(host, enable);
  125. }
  126. static void renesas_sdhi_sys_dmac_abort_dma(struct tmio_mmc_host *host)
  127. {
  128. renesas_sdhi_sys_dmac_enable_dma(host, false);
  129. if (host->chan_rx)
  130. dmaengine_terminate_all(host->chan_rx);
  131. if (host->chan_tx)
  132. dmaengine_terminate_all(host->chan_tx);
  133. renesas_sdhi_sys_dmac_enable_dma(host, true);
  134. }
  135. static void renesas_sdhi_sys_dmac_dataend_dma(struct tmio_mmc_host *host)
  136. {
  137. struct renesas_sdhi *priv = host_to_priv(host);
  138. complete(&priv->dma_priv.dma_dataend);
  139. }
  140. static void renesas_sdhi_sys_dmac_dma_callback(void *arg)
  141. {
  142. struct tmio_mmc_host *host = arg;
  143. struct renesas_sdhi *priv = host_to_priv(host);
  144. spin_lock_irq(&host->lock);
  145. if (!host->data)
  146. goto out;
  147. if (host->data->flags & MMC_DATA_READ)
  148. dma_unmap_sg(host->chan_rx->device->dev,
  149. host->sg_ptr, host->sg_len,
  150. DMA_FROM_DEVICE);
  151. else
  152. dma_unmap_sg(host->chan_tx->device->dev,
  153. host->sg_ptr, host->sg_len,
  154. DMA_TO_DEVICE);
  155. spin_unlock_irq(&host->lock);
  156. wait_for_completion(&priv->dma_priv.dma_dataend);
  157. spin_lock_irq(&host->lock);
  158. tmio_mmc_do_data_irq(host);
  159. out:
  160. spin_unlock_irq(&host->lock);
  161. }
  162. static void renesas_sdhi_sys_dmac_start_dma_rx(struct tmio_mmc_host *host)
  163. {
  164. struct renesas_sdhi *priv = host_to_priv(host);
  165. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  166. struct dma_async_tx_descriptor *desc = NULL;
  167. struct dma_chan *chan = host->chan_rx;
  168. dma_cookie_t cookie;
  169. int ret, i;
  170. bool aligned = true, multiple = true;
  171. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  172. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  173. if (sg_tmp->offset & align)
  174. aligned = false;
  175. if (sg_tmp->length & align) {
  176. multiple = false;
  177. break;
  178. }
  179. }
  180. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  181. (align & PAGE_MASK))) || !multiple) {
  182. ret = -EINVAL;
  183. goto pio;
  184. }
  185. if (sg->length < TMIO_MMC_MIN_DMA_LEN) {
  186. host->force_pio = true;
  187. return;
  188. }
  189. /* The only sg element can be unaligned, use our bounce buffer then */
  190. if (!aligned) {
  191. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  192. host->sg_ptr = &host->bounce_sg;
  193. sg = host->sg_ptr;
  194. }
  195. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
  196. if (ret > 0)
  197. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_DEV_TO_MEM,
  198. DMA_CTRL_ACK);
  199. if (desc) {
  200. reinit_completion(&priv->dma_priv.dma_dataend);
  201. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  202. desc->callback_param = host;
  203. cookie = dmaengine_submit(desc);
  204. if (cookie < 0) {
  205. desc = NULL;
  206. ret = cookie;
  207. }
  208. }
  209. pio:
  210. if (!desc) {
  211. /* DMA failed, fall back to PIO */
  212. renesas_sdhi_sys_dmac_enable_dma(host, false);
  213. if (ret >= 0)
  214. ret = -EIO;
  215. host->chan_rx = NULL;
  216. dma_release_channel(chan);
  217. /* Free the Tx channel too */
  218. chan = host->chan_tx;
  219. if (chan) {
  220. host->chan_tx = NULL;
  221. dma_release_channel(chan);
  222. }
  223. dev_warn(&host->pdev->dev,
  224. "DMA failed: %d, falling back to PIO\n", ret);
  225. }
  226. }
  227. static void renesas_sdhi_sys_dmac_start_dma_tx(struct tmio_mmc_host *host)
  228. {
  229. struct renesas_sdhi *priv = host_to_priv(host);
  230. struct scatterlist *sg = host->sg_ptr, *sg_tmp;
  231. struct dma_async_tx_descriptor *desc = NULL;
  232. struct dma_chan *chan = host->chan_tx;
  233. dma_cookie_t cookie;
  234. int ret, i;
  235. bool aligned = true, multiple = true;
  236. unsigned int align = (1 << host->pdata->alignment_shift) - 1;
  237. for_each_sg(sg, sg_tmp, host->sg_len, i) {
  238. if (sg_tmp->offset & align)
  239. aligned = false;
  240. if (sg_tmp->length & align) {
  241. multiple = false;
  242. break;
  243. }
  244. }
  245. if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_SIZE ||
  246. (align & PAGE_MASK))) || !multiple) {
  247. ret = -EINVAL;
  248. goto pio;
  249. }
  250. if (sg->length < TMIO_MMC_MIN_DMA_LEN) {
  251. host->force_pio = true;
  252. return;
  253. }
  254. /* The only sg element can be unaligned, use our bounce buffer then */
  255. if (!aligned) {
  256. unsigned long flags;
  257. void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
  258. sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
  259. memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
  260. tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
  261. host->sg_ptr = &host->bounce_sg;
  262. sg = host->sg_ptr;
  263. }
  264. ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
  265. if (ret > 0)
  266. desc = dmaengine_prep_slave_sg(chan, sg, ret, DMA_MEM_TO_DEV,
  267. DMA_CTRL_ACK);
  268. if (desc) {
  269. reinit_completion(&priv->dma_priv.dma_dataend);
  270. desc->callback = renesas_sdhi_sys_dmac_dma_callback;
  271. desc->callback_param = host;
  272. cookie = dmaengine_submit(desc);
  273. if (cookie < 0) {
  274. desc = NULL;
  275. ret = cookie;
  276. }
  277. }
  278. pio:
  279. if (!desc) {
  280. /* DMA failed, fall back to PIO */
  281. renesas_sdhi_sys_dmac_enable_dma(host, false);
  282. if (ret >= 0)
  283. ret = -EIO;
  284. host->chan_tx = NULL;
  285. dma_release_channel(chan);
  286. /* Free the Rx channel too */
  287. chan = host->chan_rx;
  288. if (chan) {
  289. host->chan_rx = NULL;
  290. dma_release_channel(chan);
  291. }
  292. dev_warn(&host->pdev->dev,
  293. "DMA failed: %d, falling back to PIO\n", ret);
  294. }
  295. }
  296. static void renesas_sdhi_sys_dmac_start_dma(struct tmio_mmc_host *host,
  297. struct mmc_data *data)
  298. {
  299. if (data->flags & MMC_DATA_READ) {
  300. if (host->chan_rx)
  301. renesas_sdhi_sys_dmac_start_dma_rx(host);
  302. } else {
  303. if (host->chan_tx)
  304. renesas_sdhi_sys_dmac_start_dma_tx(host);
  305. }
  306. }
  307. static void renesas_sdhi_sys_dmac_issue_tasklet_fn(unsigned long priv)
  308. {
  309. struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
  310. struct dma_chan *chan = NULL;
  311. spin_lock_irq(&host->lock);
  312. if (host->data) {
  313. if (host->data->flags & MMC_DATA_READ)
  314. chan = host->chan_rx;
  315. else
  316. chan = host->chan_tx;
  317. }
  318. spin_unlock_irq(&host->lock);
  319. tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
  320. if (chan)
  321. dma_async_issue_pending(chan);
  322. }
  323. static void renesas_sdhi_sys_dmac_request_dma(struct tmio_mmc_host *host,
  324. struct tmio_mmc_data *pdata)
  325. {
  326. struct renesas_sdhi *priv = host_to_priv(host);
  327. /* We can only either use DMA for both Tx and Rx or not use it at all */
  328. if (!host->pdev->dev.of_node &&
  329. (!pdata->chan_priv_tx || !pdata->chan_priv_rx))
  330. return;
  331. if (!host->chan_tx && !host->chan_rx) {
  332. struct resource *res = platform_get_resource(host->pdev,
  333. IORESOURCE_MEM, 0);
  334. struct dma_slave_config cfg = {};
  335. dma_cap_mask_t mask;
  336. int ret;
  337. if (!res)
  338. return;
  339. dma_cap_zero(mask);
  340. dma_cap_set(DMA_SLAVE, mask);
  341. host->chan_tx = dma_request_slave_channel_compat(mask,
  342. priv->dma_priv.filter, pdata->chan_priv_tx,
  343. &host->pdev->dev, "tx");
  344. dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
  345. host->chan_tx);
  346. if (!host->chan_tx)
  347. return;
  348. cfg.direction = DMA_MEM_TO_DEV;
  349. cfg.dst_addr = res->start +
  350. (CTL_SD_DATA_PORT << host->bus_shift);
  351. cfg.dst_addr_width = priv->dma_priv.dma_buswidth;
  352. if (!cfg.dst_addr_width)
  353. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  354. cfg.src_addr = 0;
  355. ret = dmaengine_slave_config(host->chan_tx, &cfg);
  356. if (ret < 0)
  357. goto ecfgtx;
  358. host->chan_rx = dma_request_slave_channel_compat(mask,
  359. priv->dma_priv.filter, pdata->chan_priv_rx,
  360. &host->pdev->dev, "rx");
  361. dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
  362. host->chan_rx);
  363. if (!host->chan_rx)
  364. goto ereqrx;
  365. cfg.direction = DMA_DEV_TO_MEM;
  366. cfg.src_addr = cfg.dst_addr + host->pdata->dma_rx_offset;
  367. cfg.src_addr_width = priv->dma_priv.dma_buswidth;
  368. if (!cfg.src_addr_width)
  369. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
  370. cfg.dst_addr = 0;
  371. ret = dmaengine_slave_config(host->chan_rx, &cfg);
  372. if (ret < 0)
  373. goto ecfgrx;
  374. host->bounce_buf = (u8 *)__get_free_page(GFP_KERNEL | GFP_DMA);
  375. if (!host->bounce_buf)
  376. goto ebouncebuf;
  377. init_completion(&priv->dma_priv.dma_dataend);
  378. tasklet_init(&host->dma_issue,
  379. renesas_sdhi_sys_dmac_issue_tasklet_fn,
  380. (unsigned long)host);
  381. }
  382. renesas_sdhi_sys_dmac_enable_dma(host, true);
  383. return;
  384. ebouncebuf:
  385. ecfgrx:
  386. dma_release_channel(host->chan_rx);
  387. host->chan_rx = NULL;
  388. ereqrx:
  389. ecfgtx:
  390. dma_release_channel(host->chan_tx);
  391. host->chan_tx = NULL;
  392. }
  393. static void renesas_sdhi_sys_dmac_release_dma(struct tmio_mmc_host *host)
  394. {
  395. if (host->chan_tx) {
  396. struct dma_chan *chan = host->chan_tx;
  397. host->chan_tx = NULL;
  398. dma_release_channel(chan);
  399. }
  400. if (host->chan_rx) {
  401. struct dma_chan *chan = host->chan_rx;
  402. host->chan_rx = NULL;
  403. dma_release_channel(chan);
  404. }
  405. if (host->bounce_buf) {
  406. free_pages((unsigned long)host->bounce_buf, 0);
  407. host->bounce_buf = NULL;
  408. }
  409. }
  410. static const struct tmio_mmc_dma_ops renesas_sdhi_sys_dmac_dma_ops = {
  411. .start = renesas_sdhi_sys_dmac_start_dma,
  412. .enable = renesas_sdhi_sys_dmac_enable_dma,
  413. .request = renesas_sdhi_sys_dmac_request_dma,
  414. .release = renesas_sdhi_sys_dmac_release_dma,
  415. .abort = renesas_sdhi_sys_dmac_abort_dma,
  416. .dataend = renesas_sdhi_sys_dmac_dataend_dma,
  417. };
  418. /*
  419. * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
  420. * implementation. Currently empty as all supported ES versions use
  421. * the internal DMAC.
  422. */
  423. static const struct soc_device_attribute gen3_soc_whitelist[] = {
  424. { /* sentinel */ }
  425. };
  426. static int renesas_sdhi_sys_dmac_probe(struct platform_device *pdev)
  427. {
  428. if (of_device_get_match_data(&pdev->dev) == &of_rcar_gen3_compatible &&
  429. !soc_device_match(gen3_soc_whitelist))
  430. return -ENODEV;
  431. return renesas_sdhi_probe(pdev, &renesas_sdhi_sys_dmac_dma_ops);
  432. }
  433. static const struct dev_pm_ops renesas_sdhi_sys_dmac_dev_pm_ops = {
  434. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  435. pm_runtime_force_resume)
  436. SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
  437. tmio_mmc_host_runtime_resume,
  438. NULL)
  439. };
  440. static struct platform_driver renesas_sys_dmac_sdhi_driver = {
  441. .driver = {
  442. .name = "sh_mobile_sdhi",
  443. .pm = &renesas_sdhi_sys_dmac_dev_pm_ops,
  444. .of_match_table = renesas_sdhi_sys_dmac_of_match,
  445. },
  446. .probe = renesas_sdhi_sys_dmac_probe,
  447. .remove = renesas_sdhi_remove,
  448. };
  449. module_platform_driver(renesas_sys_dmac_sdhi_driver);
  450. MODULE_DESCRIPTION("Renesas SDHI driver");
  451. MODULE_AUTHOR("Magnus Damm");
  452. MODULE_LICENSE("GPL v2");
  453. MODULE_ALIAS("platform:sh_mobile_sdhi");