camss.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * camss.c
  4. *
  5. * Qualcomm MSM Camera Subsystem - Core
  6. *
  7. * Copyright (c) 2015, The Linux Foundation. All rights reserved.
  8. * Copyright (C) 2015-2018 Linaro Ltd.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/media-bus-format.h>
  12. #include <linux/media.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_graph.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/pm_domain.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <media/media-device.h>
  22. #include <media/v4l2-async.h>
  23. #include <media/v4l2-device.h>
  24. #include <media/v4l2-mc.h>
  25. #include <media/v4l2-fwnode.h>
  26. #include "camss.h"
  27. #define CAMSS_CLOCK_MARGIN_NUMERATOR 105
  28. #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
  29. static const struct resources csiphy_res_8x16[] = {
  30. /* CSIPHY0 */
  31. {
  32. .regulator = { NULL },
  33. .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
  34. .clock_rate = { { 0 },
  35. { 0 },
  36. { 0 },
  37. { 100000000, 200000000 } },
  38. .reg = { "csiphy0", "csiphy0_clk_mux" },
  39. .interrupt = { "csiphy0" }
  40. },
  41. /* CSIPHY1 */
  42. {
  43. .regulator = { NULL },
  44. .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
  45. .clock_rate = { { 0 },
  46. { 0 },
  47. { 0 },
  48. { 100000000, 200000000 } },
  49. .reg = { "csiphy1", "csiphy1_clk_mux" },
  50. .interrupt = { "csiphy1" }
  51. }
  52. };
  53. static const struct resources csid_res_8x16[] = {
  54. /* CSID0 */
  55. {
  56. .regulator = { "vdda" },
  57. .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
  58. "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
  59. .clock_rate = { { 0 },
  60. { 0 },
  61. { 0 },
  62. { 0 },
  63. { 100000000, 200000000 },
  64. { 0 },
  65. { 0 },
  66. { 0 } },
  67. .reg = { "csid0" },
  68. .interrupt = { "csid0" }
  69. },
  70. /* CSID1 */
  71. {
  72. .regulator = { "vdda" },
  73. .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
  74. "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
  75. .clock_rate = { { 0 },
  76. { 0 },
  77. { 0 },
  78. { 0 },
  79. { 100000000, 200000000 },
  80. { 0 },
  81. { 0 },
  82. { 0 } },
  83. .reg = { "csid1" },
  84. .interrupt = { "csid1" }
  85. },
  86. };
  87. static const struct resources_ispif ispif_res_8x16 = {
  88. /* ISPIF */
  89. .clock = { "top_ahb", "ahb", "ispif_ahb",
  90. "csi0", "csi0_pix", "csi0_rdi",
  91. "csi1", "csi1_pix", "csi1_rdi" },
  92. .clock_for_reset = { "vfe0", "csi_vfe0" },
  93. .reg = { "ispif", "csi_clk_mux" },
  94. .interrupt = "ispif"
  95. };
  96. static const struct resources vfe_res_8x16[] = {
  97. /* VFE0 */
  98. {
  99. .regulator = { NULL },
  100. .clock = { "top_ahb", "vfe0", "csi_vfe0",
  101. "vfe_ahb", "vfe_axi", "ahb" },
  102. .clock_rate = { { 0 },
  103. { 50000000, 80000000, 100000000, 160000000,
  104. 177780000, 200000000, 266670000, 320000000,
  105. 400000000, 465000000 },
  106. { 0 },
  107. { 0 },
  108. { 0 },
  109. { 0 },
  110. { 0 },
  111. { 0 },
  112. { 0 } },
  113. .reg = { "vfe0" },
  114. .interrupt = { "vfe0" }
  115. }
  116. };
  117. static const struct resources csiphy_res_8x96[] = {
  118. /* CSIPHY0 */
  119. {
  120. .regulator = { NULL },
  121. .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
  122. .clock_rate = { { 0 },
  123. { 0 },
  124. { 0 },
  125. { 100000000, 200000000, 266666667 } },
  126. .reg = { "csiphy0", "csiphy0_clk_mux" },
  127. .interrupt = { "csiphy0" }
  128. },
  129. /* CSIPHY1 */
  130. {
  131. .regulator = { NULL },
  132. .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" },
  133. .clock_rate = { { 0 },
  134. { 0 },
  135. { 0 },
  136. { 100000000, 200000000, 266666667 } },
  137. .reg = { "csiphy1", "csiphy1_clk_mux" },
  138. .interrupt = { "csiphy1" }
  139. },
  140. /* CSIPHY2 */
  141. {
  142. .regulator = { NULL },
  143. .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" },
  144. .clock_rate = { { 0 },
  145. { 0 },
  146. { 0 },
  147. { 100000000, 200000000, 266666667 } },
  148. .reg = { "csiphy2", "csiphy2_clk_mux" },
  149. .interrupt = { "csiphy2" }
  150. }
  151. };
  152. static const struct resources csid_res_8x96[] = {
  153. /* CSID0 */
  154. {
  155. .regulator = { "vdda" },
  156. .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb",
  157. "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" },
  158. .clock_rate = { { 0 },
  159. { 0 },
  160. { 0 },
  161. { 0 },
  162. { 100000000, 200000000, 266666667 },
  163. { 0 },
  164. { 0 },
  165. { 0 } },
  166. .reg = { "csid0" },
  167. .interrupt = { "csid0" }
  168. },
  169. /* CSID1 */
  170. {
  171. .regulator = { "vdda" },
  172. .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb",
  173. "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" },
  174. .clock_rate = { { 0 },
  175. { 0 },
  176. { 0 },
  177. { 0 },
  178. { 100000000, 200000000, 266666667 },
  179. { 0 },
  180. { 0 },
  181. { 0 } },
  182. .reg = { "csid1" },
  183. .interrupt = { "csid1" }
  184. },
  185. /* CSID2 */
  186. {
  187. .regulator = { "vdda" },
  188. .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb",
  189. "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" },
  190. .clock_rate = { { 0 },
  191. { 0 },
  192. { 0 },
  193. { 0 },
  194. { 100000000, 200000000, 266666667 },
  195. { 0 },
  196. { 0 },
  197. { 0 } },
  198. .reg = { "csid2" },
  199. .interrupt = { "csid2" }
  200. },
  201. /* CSID3 */
  202. {
  203. .regulator = { "vdda" },
  204. .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb",
  205. "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" },
  206. .clock_rate = { { 0 },
  207. { 0 },
  208. { 0 },
  209. { 0 },
  210. { 100000000, 200000000, 266666667 },
  211. { 0 },
  212. { 0 },
  213. { 0 } },
  214. .reg = { "csid3" },
  215. .interrupt = { "csid3" }
  216. }
  217. };
  218. static const struct resources_ispif ispif_res_8x96 = {
  219. /* ISPIF */
  220. .clock = { "top_ahb", "ahb", "ispif_ahb",
  221. "csi0", "csi0_pix", "csi0_rdi",
  222. "csi1", "csi1_pix", "csi1_rdi",
  223. "csi2", "csi2_pix", "csi2_rdi",
  224. "csi3", "csi3_pix", "csi3_rdi" },
  225. .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" },
  226. .reg = { "ispif", "csi_clk_mux" },
  227. .interrupt = "ispif"
  228. };
  229. static const struct resources vfe_res_8x96[] = {
  230. /* VFE0 */
  231. {
  232. .regulator = { NULL },
  233. .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb",
  234. "vfe0_ahb", "vfe_axi", "vfe0_stream"},
  235. .clock_rate = { { 0 },
  236. { 0 },
  237. { 75000000, 100000000, 300000000,
  238. 320000000, 480000000, 600000000 },
  239. { 0 },
  240. { 0 },
  241. { 0 },
  242. { 0 },
  243. { 0 } },
  244. .reg = { "vfe0" },
  245. .interrupt = { "vfe0" }
  246. },
  247. /* VFE1 */
  248. {
  249. .regulator = { NULL },
  250. .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb",
  251. "vfe1_ahb", "vfe_axi", "vfe1_stream"},
  252. .clock_rate = { { 0 },
  253. { 0 },
  254. { 75000000, 100000000, 300000000,
  255. 320000000, 480000000, 600000000 },
  256. { 0 },
  257. { 0 },
  258. { 0 },
  259. { 0 },
  260. { 0 } },
  261. .reg = { "vfe1" },
  262. .interrupt = { "vfe1" }
  263. }
  264. };
  265. /*
  266. * camss_add_clock_margin - Add margin to clock frequency rate
  267. * @rate: Clock frequency rate
  268. *
  269. * When making calculations with physical clock frequency values
  270. * some safety margin must be added. Add it.
  271. */
  272. inline void camss_add_clock_margin(u64 *rate)
  273. {
  274. *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR;
  275. *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR);
  276. }
  277. /*
  278. * camss_enable_clocks - Enable multiple clocks
  279. * @nclocks: Number of clocks in clock array
  280. * @clock: Clock array
  281. * @dev: Device
  282. *
  283. * Return 0 on success or a negative error code otherwise
  284. */
  285. int camss_enable_clocks(int nclocks, struct camss_clock *clock,
  286. struct device *dev)
  287. {
  288. int ret;
  289. int i;
  290. for (i = 0; i < nclocks; i++) {
  291. ret = clk_prepare_enable(clock[i].clk);
  292. if (ret) {
  293. dev_err(dev, "clock enable failed: %d\n", ret);
  294. goto error;
  295. }
  296. }
  297. return 0;
  298. error:
  299. for (i--; i >= 0; i--)
  300. clk_disable_unprepare(clock[i].clk);
  301. return ret;
  302. }
  303. /*
  304. * camss_disable_clocks - Disable multiple clocks
  305. * @nclocks: Number of clocks in clock array
  306. * @clock: Clock array
  307. */
  308. void camss_disable_clocks(int nclocks, struct camss_clock *clock)
  309. {
  310. int i;
  311. for (i = nclocks - 1; i >= 0; i--)
  312. clk_disable_unprepare(clock[i].clk);
  313. }
  314. /*
  315. * camss_find_sensor - Find a linked media entity which represents a sensor
  316. * @entity: Media entity to start searching from
  317. *
  318. * Return a pointer to sensor media entity or NULL if not found
  319. */
  320. static struct media_entity *camss_find_sensor(struct media_entity *entity)
  321. {
  322. struct media_pad *pad;
  323. while (1) {
  324. pad = &entity->pads[0];
  325. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  326. return NULL;
  327. pad = media_entity_remote_pad(pad);
  328. if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
  329. return NULL;
  330. entity = pad->entity;
  331. if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
  332. return entity;
  333. }
  334. }
  335. /*
  336. * camss_get_pixel_clock - Get pixel clock rate from sensor
  337. * @entity: Media entity in the current pipeline
  338. * @pixel_clock: Received pixel clock value
  339. *
  340. * Return 0 on success or a negative error code otherwise
  341. */
  342. int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock)
  343. {
  344. struct media_entity *sensor;
  345. struct v4l2_subdev *subdev;
  346. struct v4l2_ctrl *ctrl;
  347. sensor = camss_find_sensor(entity);
  348. if (!sensor)
  349. return -ENODEV;
  350. subdev = media_entity_to_v4l2_subdev(sensor);
  351. ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE);
  352. if (!ctrl)
  353. return -EINVAL;
  354. *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl);
  355. return 0;
  356. }
  357. int camss_pm_domain_on(struct camss *camss, int id)
  358. {
  359. if (camss->version == CAMSS_8x96) {
  360. camss->genpd_link[id] = device_link_add(camss->dev,
  361. camss->genpd[id], DL_FLAG_STATELESS |
  362. DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
  363. if (!camss->genpd_link[id])
  364. return -EINVAL;
  365. }
  366. return 0;
  367. }
  368. void camss_pm_domain_off(struct camss *camss, int id)
  369. {
  370. if (camss->version == CAMSS_8x96)
  371. device_link_del(camss->genpd_link[id]);
  372. }
  373. /*
  374. * camss_of_parse_endpoint_node - Parse port endpoint node
  375. * @dev: Device
  376. * @node: Device node to be parsed
  377. * @csd: Parsed data from port endpoint node
  378. *
  379. * Return 0 on success or a negative error code on failure
  380. */
  381. static int camss_of_parse_endpoint_node(struct device *dev,
  382. struct device_node *node,
  383. struct camss_async_subdev *csd)
  384. {
  385. struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg;
  386. struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2;
  387. struct v4l2_fwnode_endpoint vep = { { 0 } };
  388. unsigned int i;
  389. v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep);
  390. csd->interface.csiphy_id = vep.base.port;
  391. mipi_csi2 = &vep.bus.mipi_csi2;
  392. lncfg->clk.pos = mipi_csi2->clock_lane;
  393. lncfg->clk.pol = mipi_csi2->lane_polarities[0];
  394. lncfg->num_data = mipi_csi2->num_data_lanes;
  395. lncfg->data = devm_kcalloc(dev,
  396. lncfg->num_data, sizeof(*lncfg->data),
  397. GFP_KERNEL);
  398. if (!lncfg->data)
  399. return -ENOMEM;
  400. for (i = 0; i < lncfg->num_data; i++) {
  401. lncfg->data[i].pos = mipi_csi2->data_lanes[i];
  402. lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1];
  403. }
  404. return 0;
  405. }
  406. /*
  407. * camss_of_parse_ports - Parse ports node
  408. * @dev: Device
  409. * @notifier: v4l2_device notifier data
  410. *
  411. * Return number of "port" nodes found in "ports" node
  412. */
  413. static int camss_of_parse_ports(struct device *dev,
  414. struct v4l2_async_notifier *notifier)
  415. {
  416. struct device_node *node = NULL;
  417. struct device_node *remote = NULL;
  418. unsigned int size, i;
  419. int ret;
  420. while ((node = of_graph_get_next_endpoint(dev->of_node, node)))
  421. if (of_device_is_available(node))
  422. notifier->num_subdevs++;
  423. of_node_put(node);
  424. size = sizeof(*notifier->subdevs) * notifier->num_subdevs;
  425. notifier->subdevs = devm_kzalloc(dev, size, GFP_KERNEL);
  426. if (!notifier->subdevs) {
  427. dev_err(dev, "Failed to allocate memory\n");
  428. return -ENOMEM;
  429. }
  430. i = 0;
  431. while ((node = of_graph_get_next_endpoint(dev->of_node, node))) {
  432. struct camss_async_subdev *csd;
  433. if (!of_device_is_available(node))
  434. continue;
  435. csd = devm_kzalloc(dev, sizeof(*csd), GFP_KERNEL);
  436. if (!csd) {
  437. of_node_put(node);
  438. dev_err(dev, "Failed to allocate memory\n");
  439. return -ENOMEM;
  440. }
  441. notifier->subdevs[i++] = &csd->asd;
  442. ret = camss_of_parse_endpoint_node(dev, node, csd);
  443. if (ret < 0) {
  444. of_node_put(node);
  445. return ret;
  446. }
  447. remote = of_graph_get_remote_port_parent(node);
  448. if (!remote) {
  449. dev_err(dev, "Cannot get remote parent\n");
  450. of_node_put(node);
  451. return -EINVAL;
  452. }
  453. csd->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
  454. csd->asd.match.fwnode = of_fwnode_handle(remote);
  455. }
  456. of_node_put(node);
  457. return notifier->num_subdevs;
  458. }
  459. /*
  460. * camss_init_subdevices - Initialize subdev structures and resources
  461. * @camss: CAMSS device
  462. *
  463. * Return 0 on success or a negative error code on failure
  464. */
  465. static int camss_init_subdevices(struct camss *camss)
  466. {
  467. const struct resources *csiphy_res;
  468. const struct resources *csid_res;
  469. const struct resources_ispif *ispif_res;
  470. const struct resources *vfe_res;
  471. unsigned int i;
  472. int ret;
  473. if (camss->version == CAMSS_8x16) {
  474. csiphy_res = csiphy_res_8x16;
  475. csid_res = csid_res_8x16;
  476. ispif_res = &ispif_res_8x16;
  477. vfe_res = vfe_res_8x16;
  478. } else if (camss->version == CAMSS_8x96) {
  479. csiphy_res = csiphy_res_8x96;
  480. csid_res = csid_res_8x96;
  481. ispif_res = &ispif_res_8x96;
  482. vfe_res = vfe_res_8x96;
  483. } else {
  484. return -EINVAL;
  485. }
  486. for (i = 0; i < camss->csiphy_num; i++) {
  487. ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i],
  488. &csiphy_res[i], i);
  489. if (ret < 0) {
  490. dev_err(camss->dev,
  491. "Failed to init csiphy%d sub-device: %d\n",
  492. i, ret);
  493. return ret;
  494. }
  495. }
  496. for (i = 0; i < camss->csid_num; i++) {
  497. ret = msm_csid_subdev_init(camss, &camss->csid[i],
  498. &csid_res[i], i);
  499. if (ret < 0) {
  500. dev_err(camss->dev,
  501. "Failed to init csid%d sub-device: %d\n",
  502. i, ret);
  503. return ret;
  504. }
  505. }
  506. ret = msm_ispif_subdev_init(&camss->ispif, ispif_res);
  507. if (ret < 0) {
  508. dev_err(camss->dev, "Failed to init ispif sub-device: %d\n",
  509. ret);
  510. return ret;
  511. }
  512. for (i = 0; i < camss->vfe_num; i++) {
  513. ret = msm_vfe_subdev_init(camss, &camss->vfe[i],
  514. &vfe_res[i], i);
  515. if (ret < 0) {
  516. dev_err(camss->dev,
  517. "Fail to init vfe%d sub-device: %d\n", i, ret);
  518. return ret;
  519. }
  520. }
  521. return 0;
  522. }
  523. /*
  524. * camss_register_entities - Register subdev nodes and create links
  525. * @camss: CAMSS device
  526. *
  527. * Return 0 on success or a negative error code on failure
  528. */
  529. static int camss_register_entities(struct camss *camss)
  530. {
  531. int i, j, k;
  532. int ret;
  533. for (i = 0; i < camss->csiphy_num; i++) {
  534. ret = msm_csiphy_register_entity(&camss->csiphy[i],
  535. &camss->v4l2_dev);
  536. if (ret < 0) {
  537. dev_err(camss->dev,
  538. "Failed to register csiphy%d entity: %d\n",
  539. i, ret);
  540. goto err_reg_csiphy;
  541. }
  542. }
  543. for (i = 0; i < camss->csid_num; i++) {
  544. ret = msm_csid_register_entity(&camss->csid[i],
  545. &camss->v4l2_dev);
  546. if (ret < 0) {
  547. dev_err(camss->dev,
  548. "Failed to register csid%d entity: %d\n",
  549. i, ret);
  550. goto err_reg_csid;
  551. }
  552. }
  553. ret = msm_ispif_register_entities(&camss->ispif, &camss->v4l2_dev);
  554. if (ret < 0) {
  555. dev_err(camss->dev, "Failed to register ispif entities: %d\n",
  556. ret);
  557. goto err_reg_ispif;
  558. }
  559. for (i = 0; i < camss->vfe_num; i++) {
  560. ret = msm_vfe_register_entities(&camss->vfe[i],
  561. &camss->v4l2_dev);
  562. if (ret < 0) {
  563. dev_err(camss->dev,
  564. "Failed to register vfe%d entities: %d\n",
  565. i, ret);
  566. goto err_reg_vfe;
  567. }
  568. }
  569. for (i = 0; i < camss->csiphy_num; i++) {
  570. for (j = 0; j < camss->csid_num; j++) {
  571. ret = media_create_pad_link(
  572. &camss->csiphy[i].subdev.entity,
  573. MSM_CSIPHY_PAD_SRC,
  574. &camss->csid[j].subdev.entity,
  575. MSM_CSID_PAD_SINK,
  576. 0);
  577. if (ret < 0) {
  578. dev_err(camss->dev,
  579. "Failed to link %s->%s entities: %d\n",
  580. camss->csiphy[i].subdev.entity.name,
  581. camss->csid[j].subdev.entity.name,
  582. ret);
  583. goto err_link;
  584. }
  585. }
  586. }
  587. for (i = 0; i < camss->csid_num; i++) {
  588. for (j = 0; j < camss->ispif.line_num; j++) {
  589. ret = media_create_pad_link(
  590. &camss->csid[i].subdev.entity,
  591. MSM_CSID_PAD_SRC,
  592. &camss->ispif.line[j].subdev.entity,
  593. MSM_ISPIF_PAD_SINK,
  594. 0);
  595. if (ret < 0) {
  596. dev_err(camss->dev,
  597. "Failed to link %s->%s entities: %d\n",
  598. camss->csid[i].subdev.entity.name,
  599. camss->ispif.line[j].subdev.entity.name,
  600. ret);
  601. goto err_link;
  602. }
  603. }
  604. }
  605. for (i = 0; i < camss->ispif.line_num; i++)
  606. for (k = 0; k < camss->vfe_num; k++)
  607. for (j = 0; j < ARRAY_SIZE(camss->vfe[k].line); j++) {
  608. ret = media_create_pad_link(
  609. &camss->ispif.line[i].subdev.entity,
  610. MSM_ISPIF_PAD_SRC,
  611. &camss->vfe[k].line[j].subdev.entity,
  612. MSM_VFE_PAD_SINK,
  613. 0);
  614. if (ret < 0) {
  615. dev_err(camss->dev,
  616. "Failed to link %s->%s entities: %d\n",
  617. camss->ispif.line[i].subdev.entity.name,
  618. camss->vfe[k].line[j].subdev.entity.name,
  619. ret);
  620. goto err_link;
  621. }
  622. }
  623. return 0;
  624. err_link:
  625. i = camss->vfe_num;
  626. err_reg_vfe:
  627. for (i--; i >= 0; i--)
  628. msm_vfe_unregister_entities(&camss->vfe[i]);
  629. msm_ispif_unregister_entities(&camss->ispif);
  630. err_reg_ispif:
  631. i = camss->csid_num;
  632. err_reg_csid:
  633. for (i--; i >= 0; i--)
  634. msm_csid_unregister_entity(&camss->csid[i]);
  635. i = camss->csiphy_num;
  636. err_reg_csiphy:
  637. for (i--; i >= 0; i--)
  638. msm_csiphy_unregister_entity(&camss->csiphy[i]);
  639. return ret;
  640. }
  641. /*
  642. * camss_unregister_entities - Unregister subdev nodes
  643. * @camss: CAMSS device
  644. *
  645. * Return 0 on success or a negative error code on failure
  646. */
  647. static void camss_unregister_entities(struct camss *camss)
  648. {
  649. unsigned int i;
  650. for (i = 0; i < camss->csiphy_num; i++)
  651. msm_csiphy_unregister_entity(&camss->csiphy[i]);
  652. for (i = 0; i < camss->csid_num; i++)
  653. msm_csid_unregister_entity(&camss->csid[i]);
  654. msm_ispif_unregister_entities(&camss->ispif);
  655. for (i = 0; i < camss->vfe_num; i++)
  656. msm_vfe_unregister_entities(&camss->vfe[i]);
  657. }
  658. static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async,
  659. struct v4l2_subdev *subdev,
  660. struct v4l2_async_subdev *asd)
  661. {
  662. struct camss *camss = container_of(async, struct camss, notifier);
  663. struct camss_async_subdev *csd =
  664. container_of(asd, struct camss_async_subdev, asd);
  665. u8 id = csd->interface.csiphy_id;
  666. struct csiphy_device *csiphy = &camss->csiphy[id];
  667. csiphy->cfg.csi2 = &csd->interface.csi2;
  668. subdev->host_priv = csiphy;
  669. return 0;
  670. }
  671. static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
  672. {
  673. struct camss *camss = container_of(async, struct camss, notifier);
  674. struct v4l2_device *v4l2_dev = &camss->v4l2_dev;
  675. struct v4l2_subdev *sd;
  676. int ret;
  677. list_for_each_entry(sd, &v4l2_dev->subdevs, list) {
  678. if (sd->host_priv) {
  679. struct media_entity *sensor = &sd->entity;
  680. struct csiphy_device *csiphy =
  681. (struct csiphy_device *) sd->host_priv;
  682. struct media_entity *input = &csiphy->subdev.entity;
  683. unsigned int i;
  684. for (i = 0; i < sensor->num_pads; i++) {
  685. if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE)
  686. break;
  687. }
  688. if (i == sensor->num_pads) {
  689. dev_err(camss->dev,
  690. "No source pad in external entity\n");
  691. return -EINVAL;
  692. }
  693. ret = media_create_pad_link(sensor, i,
  694. input, MSM_CSIPHY_PAD_SINK,
  695. MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
  696. if (ret < 0) {
  697. dev_err(camss->dev,
  698. "Failed to link %s->%s entities: %d\n",
  699. sensor->name, input->name, ret);
  700. return ret;
  701. }
  702. }
  703. }
  704. ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
  705. if (ret < 0)
  706. return ret;
  707. return media_device_register(&camss->media_dev);
  708. }
  709. static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = {
  710. .bound = camss_subdev_notifier_bound,
  711. .complete = camss_subdev_notifier_complete,
  712. };
  713. static const struct media_device_ops camss_media_ops = {
  714. .link_notify = v4l2_pipeline_link_notify,
  715. };
  716. /*
  717. * camss_probe - Probe CAMSS platform device
  718. * @pdev: Pointer to CAMSS platform device
  719. *
  720. * Return 0 on success or a negative error code on failure
  721. */
  722. static int camss_probe(struct platform_device *pdev)
  723. {
  724. struct device *dev = &pdev->dev;
  725. struct camss *camss;
  726. int ret;
  727. camss = kzalloc(sizeof(*camss), GFP_KERNEL);
  728. if (!camss)
  729. return -ENOMEM;
  730. atomic_set(&camss->ref_count, 0);
  731. camss->dev = dev;
  732. platform_set_drvdata(pdev, camss);
  733. if (of_device_is_compatible(dev->of_node, "qcom,msm8916-camss")) {
  734. camss->version = CAMSS_8x16;
  735. camss->csiphy_num = 2;
  736. camss->csid_num = 2;
  737. camss->vfe_num = 1;
  738. } else if (of_device_is_compatible(dev->of_node,
  739. "qcom,msm8996-camss")) {
  740. camss->version = CAMSS_8x96;
  741. camss->csiphy_num = 3;
  742. camss->csid_num = 4;
  743. camss->vfe_num = 2;
  744. } else {
  745. return -EINVAL;
  746. }
  747. camss->csiphy = devm_kcalloc(dev, camss->csiphy_num,
  748. sizeof(*camss->csiphy), GFP_KERNEL);
  749. if (!camss->csiphy)
  750. return -ENOMEM;
  751. camss->csid = devm_kcalloc(dev, camss->csid_num, sizeof(*camss->csid),
  752. GFP_KERNEL);
  753. if (!camss->csid)
  754. return -ENOMEM;
  755. camss->vfe = devm_kcalloc(dev, camss->vfe_num, sizeof(*camss->vfe),
  756. GFP_KERNEL);
  757. if (!camss->vfe)
  758. return -ENOMEM;
  759. ret = camss_of_parse_ports(dev, &camss->notifier);
  760. if (ret < 0)
  761. return ret;
  762. ret = camss_init_subdevices(camss);
  763. if (ret < 0)
  764. return ret;
  765. ret = dma_set_mask_and_coherent(dev, 0xffffffff);
  766. if (ret)
  767. return ret;
  768. camss->media_dev.dev = camss->dev;
  769. strlcpy(camss->media_dev.model, "Qualcomm Camera Subsystem",
  770. sizeof(camss->media_dev.model));
  771. camss->media_dev.ops = &camss_media_ops;
  772. media_device_init(&camss->media_dev);
  773. camss->v4l2_dev.mdev = &camss->media_dev;
  774. ret = v4l2_device_register(camss->dev, &camss->v4l2_dev);
  775. if (ret < 0) {
  776. dev_err(dev, "Failed to register V4L2 device: %d\n", ret);
  777. return ret;
  778. }
  779. ret = camss_register_entities(camss);
  780. if (ret < 0)
  781. goto err_register_entities;
  782. if (camss->notifier.num_subdevs) {
  783. camss->notifier.ops = &camss_subdev_notifier_ops;
  784. ret = v4l2_async_notifier_register(&camss->v4l2_dev,
  785. &camss->notifier);
  786. if (ret) {
  787. dev_err(dev,
  788. "Failed to register async subdev nodes: %d\n",
  789. ret);
  790. goto err_register_subdevs;
  791. }
  792. } else {
  793. ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev);
  794. if (ret < 0) {
  795. dev_err(dev, "Failed to register subdev nodes: %d\n",
  796. ret);
  797. goto err_register_subdevs;
  798. }
  799. ret = media_device_register(&camss->media_dev);
  800. if (ret < 0) {
  801. dev_err(dev, "Failed to register media device: %d\n",
  802. ret);
  803. goto err_register_subdevs;
  804. }
  805. }
  806. if (camss->version == CAMSS_8x96) {
  807. camss->genpd[PM_DOMAIN_VFE0] = dev_pm_domain_attach_by_id(
  808. camss->dev, PM_DOMAIN_VFE0);
  809. if (IS_ERR(camss->genpd[PM_DOMAIN_VFE0]))
  810. return PTR_ERR(camss->genpd[PM_DOMAIN_VFE0]);
  811. camss->genpd[PM_DOMAIN_VFE1] = dev_pm_domain_attach_by_id(
  812. camss->dev, PM_DOMAIN_VFE1);
  813. if (IS_ERR(camss->genpd[PM_DOMAIN_VFE1])) {
  814. dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0],
  815. true);
  816. return PTR_ERR(camss->genpd[PM_DOMAIN_VFE1]);
  817. }
  818. }
  819. pm_runtime_enable(dev);
  820. return 0;
  821. err_register_subdevs:
  822. camss_unregister_entities(camss);
  823. err_register_entities:
  824. v4l2_device_unregister(&camss->v4l2_dev);
  825. return ret;
  826. }
  827. void camss_delete(struct camss *camss)
  828. {
  829. v4l2_device_unregister(&camss->v4l2_dev);
  830. media_device_unregister(&camss->media_dev);
  831. media_device_cleanup(&camss->media_dev);
  832. pm_runtime_disable(camss->dev);
  833. if (camss->version == CAMSS_8x96) {
  834. dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0], true);
  835. dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE1], true);
  836. }
  837. kfree(camss);
  838. }
  839. /*
  840. * camss_remove - Remove CAMSS platform device
  841. * @pdev: Pointer to CAMSS platform device
  842. *
  843. * Always returns 0.
  844. */
  845. static int camss_remove(struct platform_device *pdev)
  846. {
  847. unsigned int i;
  848. struct camss *camss = platform_get_drvdata(pdev);
  849. for (i = 0; i < camss->vfe_num; i++)
  850. msm_vfe_stop_streaming(&camss->vfe[i]);
  851. v4l2_async_notifier_unregister(&camss->notifier);
  852. camss_unregister_entities(camss);
  853. if (atomic_read(&camss->ref_count) == 0)
  854. camss_delete(camss);
  855. return 0;
  856. }
  857. static const struct of_device_id camss_dt_match[] = {
  858. { .compatible = "qcom,msm8916-camss" },
  859. { .compatible = "qcom,msm8996-camss" },
  860. { }
  861. };
  862. MODULE_DEVICE_TABLE(of, camss_dt_match);
  863. static int __maybe_unused camss_runtime_suspend(struct device *dev)
  864. {
  865. return 0;
  866. }
  867. static int __maybe_unused camss_runtime_resume(struct device *dev)
  868. {
  869. return 0;
  870. }
  871. static const struct dev_pm_ops camss_pm_ops = {
  872. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  873. pm_runtime_force_resume)
  874. SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL)
  875. };
  876. static struct platform_driver qcom_camss_driver = {
  877. .probe = camss_probe,
  878. .remove = camss_remove,
  879. .driver = {
  880. .name = "qcom-camss",
  881. .of_match_table = camss_dt_match,
  882. .pm = &camss_pm_ops,
  883. },
  884. };
  885. module_platform_driver(qcom_camss_driver);
  886. MODULE_ALIAS("platform:qcom-camss");
  887. MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver");
  888. MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
  889. MODULE_LICENSE("GPL v2");