vdec_vp8_if.c 17 KB

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  1. /*
  2. * Copyright (c) 2016 MediaTek Inc.
  3. * Author: Jungchang Tsao <jungchang.tsao@mediatek.com>
  4. * PC Chen <pc.chen@mediatek.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/slab.h>
  16. #include "../vdec_drv_if.h"
  17. #include "../mtk_vcodec_util.h"
  18. #include "../mtk_vcodec_dec.h"
  19. #include "../mtk_vcodec_intr.h"
  20. #include "../vdec_vpu_if.h"
  21. #include "../vdec_drv_base.h"
  22. /* Decoding picture buffer size (3 reference frames plus current frame) */
  23. #define VP8_DPB_SIZE 4
  24. /* HW working buffer size (bytes) */
  25. #define VP8_WORKING_BUF_SZ (45 * 4096)
  26. /* HW control register address */
  27. #define VP8_SEGID_DRAM_ADDR 0x3c
  28. #define VP8_HW_VLD_ADDR 0x93C
  29. #define VP8_HW_VLD_VALUE 0x940
  30. #define VP8_BSASET 0x100
  31. #define VP8_BSDSET 0x104
  32. #define VP8_RW_CKEN_SET 0x0
  33. #define VP8_RW_DCM_CON 0x18
  34. #define VP8_WO_VLD_SRST 0x108
  35. #define VP8_RW_MISC_SYS_SEL 0x84
  36. #define VP8_RW_MISC_SPEC_CON 0xC8
  37. #define VP8_WO_VLD_SRST 0x108
  38. #define VP8_RW_VP8_CTRL 0xA4
  39. #define VP8_RW_MISC_DCM_CON 0xEC
  40. #define VP8_RW_MISC_SRST 0xF4
  41. #define VP8_RW_MISC_FUNC_CON 0xCC
  42. #define VP8_MAX_FRM_BUF_NUM 5
  43. #define VP8_MAX_FRM_BUF_NODE_NUM (VP8_MAX_FRM_BUF_NUM * 2)
  44. /* required buffer size (bytes) to store decode information */
  45. #define VP8_HW_SEGMENT_DATA_SZ 272
  46. #define VP8_HW_SEGMENT_UINT 4
  47. #define VP8_DEC_TABLE_PROC_LOOP 96
  48. #define VP8_DEC_TABLE_UNIT 3
  49. #define VP8_DEC_TABLE_SZ 300
  50. #define VP8_DEC_TABLE_OFFSET 2
  51. #define VP8_DEC_TABLE_RW_UNIT 4
  52. /**
  53. * struct vdec_vp8_dec_info - decode misc information
  54. * @working_buf_dma : working buffer dma address
  55. * @prev_y_dma : previous decoded frame buffer Y plane address
  56. * @cur_y_fb_dma : current plane Y frame buffer dma address
  57. * @cur_c_fb_dma : current plane C frame buffer dma address
  58. * @bs_dma : bitstream dma address
  59. * @bs_sz : bitstream size
  60. * @resolution_changed: resolution change flag 1 - changed, 0 - not change
  61. * @show_frame : display this frame or not
  62. * @wait_key_frame : wait key frame coming
  63. */
  64. struct vdec_vp8_dec_info {
  65. uint64_t working_buf_dma;
  66. uint64_t prev_y_dma;
  67. uint64_t cur_y_fb_dma;
  68. uint64_t cur_c_fb_dma;
  69. uint64_t bs_dma;
  70. uint32_t bs_sz;
  71. uint32_t resolution_changed;
  72. uint32_t show_frame;
  73. uint32_t wait_key_frame;
  74. };
  75. /**
  76. * struct vdec_vp8_vsi - VPU shared information
  77. * @dec : decoding information
  78. * @pic : picture information
  79. * @dec_table : decoder coefficient table
  80. * @segment_buf : segmentation buffer
  81. * @load_data : flag to indicate reload decode data
  82. */
  83. struct vdec_vp8_vsi {
  84. struct vdec_vp8_dec_info dec;
  85. struct vdec_pic_info pic;
  86. uint32_t dec_table[VP8_DEC_TABLE_SZ];
  87. uint32_t segment_buf[VP8_HW_SEGMENT_DATA_SZ][VP8_HW_SEGMENT_UINT];
  88. uint32_t load_data;
  89. };
  90. /**
  91. * struct vdec_vp8_hw_reg_base - HW register base
  92. * @sys : base address for sys
  93. * @misc : base address for misc
  94. * @ld : base address for ld
  95. * @top : base address for top
  96. * @cm : base address for cm
  97. * @hwd : base address for hwd
  98. * @hwb : base address for hwb
  99. */
  100. struct vdec_vp8_hw_reg_base {
  101. void __iomem *sys;
  102. void __iomem *misc;
  103. void __iomem *ld;
  104. void __iomem *top;
  105. void __iomem *cm;
  106. void __iomem *hwd;
  107. void __iomem *hwb;
  108. };
  109. /**
  110. * struct vdec_vp8_vpu_inst - VPU instance for VP8 decode
  111. * @wq_hd : Wait queue to wait VPU message ack
  112. * @signaled : 1 - Host has received ack message from VPU, 0 - not recevie
  113. * @failure : VPU execution result status 0 - success, others - fail
  114. * @inst_addr : VPU decoder instance address
  115. */
  116. struct vdec_vp8_vpu_inst {
  117. wait_queue_head_t wq_hd;
  118. int signaled;
  119. int failure;
  120. uint32_t inst_addr;
  121. };
  122. /* frame buffer (fb) list
  123. * [available_fb_node_list] - decode fb are initialized to 0 and populated in
  124. * [fb_use_list] - fb is set after decode and is moved to this list
  125. * [fb_free_list] - fb is not needed for reference will be moved from
  126. * [fb_use_list] to [fb_free_list] and
  127. * once user remove fb from [fb_free_list],
  128. * it is circulated back to [available_fb_node_list]
  129. * [fb_disp_list] - fb is set after decode and is moved to this list
  130. * once user remove fb from [fb_disp_list] it is
  131. * circulated back to [available_fb_node_list]
  132. */
  133. /**
  134. * struct vdec_vp8_inst - VP8 decoder instance
  135. * @cur_fb : current frame buffer
  136. * @dec_fb : decode frame buffer node
  137. * @available_fb_node_list : list to store available frame buffer node
  138. * @fb_use_list : list to store frame buffer in use
  139. * @fb_free_list : list to store free frame buffer
  140. * @fb_disp_list : list to store display ready frame buffer
  141. * @working_buf : HW decoder working buffer
  142. * @reg_base : HW register base address
  143. * @frm_cnt : decode frame count
  144. * @ctx : V4L2 context
  145. * @vpu : VPU instance for decoder
  146. * @vsi : VPU share information
  147. */
  148. struct vdec_vp8_inst {
  149. struct vdec_fb *cur_fb;
  150. struct vdec_fb_node dec_fb[VP8_MAX_FRM_BUF_NODE_NUM];
  151. struct list_head available_fb_node_list;
  152. struct list_head fb_use_list;
  153. struct list_head fb_free_list;
  154. struct list_head fb_disp_list;
  155. struct mtk_vcodec_mem working_buf;
  156. struct vdec_vp8_hw_reg_base reg_base;
  157. unsigned int frm_cnt;
  158. struct mtk_vcodec_ctx *ctx;
  159. struct vdec_vpu_inst vpu;
  160. struct vdec_vp8_vsi *vsi;
  161. };
  162. static void get_hw_reg_base(struct vdec_vp8_inst *inst)
  163. {
  164. inst->reg_base.top = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_TOP);
  165. inst->reg_base.cm = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_CM);
  166. inst->reg_base.hwd = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWD);
  167. inst->reg_base.sys = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_SYS);
  168. inst->reg_base.misc = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_MISC);
  169. inst->reg_base.ld = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_LD);
  170. inst->reg_base.hwb = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWB);
  171. }
  172. static void write_hw_segmentation_data(struct vdec_vp8_inst *inst)
  173. {
  174. int i, j;
  175. u32 seg_id_addr;
  176. u32 val;
  177. void __iomem *cm = inst->reg_base.cm;
  178. struct vdec_vp8_vsi *vsi = inst->vsi;
  179. seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4;
  180. for (i = 0; i < ARRAY_SIZE(vsi->segment_buf); i++) {
  181. for (j = ARRAY_SIZE(vsi->segment_buf[i]) - 1; j >= 0; j--) {
  182. val = (1 << 16) + ((seg_id_addr + i) << 2) + j;
  183. writel(val, cm + VP8_HW_VLD_ADDR);
  184. val = vsi->segment_buf[i][j];
  185. writel(val, cm + VP8_HW_VLD_VALUE);
  186. }
  187. }
  188. }
  189. static void read_hw_segmentation_data(struct vdec_vp8_inst *inst)
  190. {
  191. int i, j;
  192. u32 seg_id_addr;
  193. u32 val;
  194. void __iomem *cm = inst->reg_base.cm;
  195. struct vdec_vp8_vsi *vsi = inst->vsi;
  196. seg_id_addr = readl(inst->reg_base.top + VP8_SEGID_DRAM_ADDR) >> 4;
  197. for (i = 0; i < ARRAY_SIZE(vsi->segment_buf); i++) {
  198. for (j = ARRAY_SIZE(vsi->segment_buf[i]) - 1; j >= 0; j--) {
  199. val = ((seg_id_addr + i) << 2) + j;
  200. writel(val, cm + VP8_HW_VLD_ADDR);
  201. val = readl(cm + VP8_HW_VLD_VALUE);
  202. vsi->segment_buf[i][j] = val;
  203. }
  204. }
  205. }
  206. /* reset HW and enable HW read/write data function */
  207. static void enable_hw_rw_function(struct vdec_vp8_inst *inst)
  208. {
  209. u32 val = 0;
  210. void __iomem *sys = inst->reg_base.sys;
  211. void __iomem *misc = inst->reg_base.misc;
  212. void __iomem *ld = inst->reg_base.ld;
  213. void __iomem *hwb = inst->reg_base.hwb;
  214. void __iomem *hwd = inst->reg_base.hwd;
  215. writel(0x1, sys + VP8_RW_CKEN_SET);
  216. writel(0x101, ld + VP8_WO_VLD_SRST);
  217. writel(0x101, hwb + VP8_WO_VLD_SRST);
  218. writel(1, sys);
  219. val = readl(misc + VP8_RW_MISC_SRST);
  220. writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST);
  221. writel(0x1, misc + VP8_RW_MISC_SYS_SEL);
  222. writel(0x17F, misc + VP8_RW_MISC_SPEC_CON);
  223. writel(0x71201100, misc + VP8_RW_MISC_FUNC_CON);
  224. writel(0x0, ld + VP8_WO_VLD_SRST);
  225. writel(0x0, hwb + VP8_WO_VLD_SRST);
  226. writel(0x1, sys + VP8_RW_DCM_CON);
  227. writel(0x1, misc + VP8_RW_MISC_DCM_CON);
  228. writel(0x1, hwd + VP8_RW_VP8_CTRL);
  229. }
  230. static void store_dec_table(struct vdec_vp8_inst *inst)
  231. {
  232. int i, j;
  233. u32 addr = 0, val = 0;
  234. void __iomem *hwd = inst->reg_base.hwd;
  235. u32 *p = &inst->vsi->dec_table[VP8_DEC_TABLE_OFFSET];
  236. for (i = 0; i < VP8_DEC_TABLE_PROC_LOOP; i++) {
  237. writel(addr, hwd + VP8_BSASET);
  238. for (j = 0; j < VP8_DEC_TABLE_UNIT ; j++) {
  239. val = *p++;
  240. writel(val, hwd + VP8_BSDSET);
  241. }
  242. addr += VP8_DEC_TABLE_RW_UNIT;
  243. }
  244. }
  245. static void load_dec_table(struct vdec_vp8_inst *inst)
  246. {
  247. int i;
  248. u32 addr = 0;
  249. u32 *p = &inst->vsi->dec_table[VP8_DEC_TABLE_OFFSET];
  250. void __iomem *hwd = inst->reg_base.hwd;
  251. for (i = 0; i < VP8_DEC_TABLE_PROC_LOOP; i++) {
  252. writel(addr, hwd + VP8_BSASET);
  253. /* read total 11 bytes */
  254. *p++ = readl(hwd + VP8_BSDSET);
  255. *p++ = readl(hwd + VP8_BSDSET);
  256. *p++ = readl(hwd + VP8_BSDSET) & 0xFFFFFF;
  257. addr += VP8_DEC_TABLE_RW_UNIT;
  258. }
  259. }
  260. static void get_pic_info(struct vdec_vp8_inst *inst, struct vdec_pic_info *pic)
  261. {
  262. *pic = inst->vsi->pic;
  263. mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)",
  264. pic->pic_w, pic->pic_h, pic->buf_w, pic->buf_h);
  265. mtk_vcodec_debug(inst, "Y(%d, %d), C(%d, %d)", pic->y_bs_sz,
  266. pic->y_len_sz, pic->c_bs_sz, pic->c_len_sz);
  267. }
  268. static void vp8_dec_finish(struct vdec_vp8_inst *inst)
  269. {
  270. struct vdec_fb_node *node;
  271. uint64_t prev_y_dma = inst->vsi->dec.prev_y_dma;
  272. mtk_vcodec_debug(inst, "prev fb base dma=%llx", prev_y_dma);
  273. /* put last decode ok frame to fb_free_list */
  274. if (prev_y_dma != 0) {
  275. list_for_each_entry(node, &inst->fb_use_list, list) {
  276. struct vdec_fb *fb = (struct vdec_fb *)node->fb;
  277. if (prev_y_dma == (uint64_t)fb->base_y.dma_addr) {
  278. list_move_tail(&node->list,
  279. &inst->fb_free_list);
  280. break;
  281. }
  282. }
  283. }
  284. /* available_fb_node_list -> fb_use_list */
  285. node = list_first_entry(&inst->available_fb_node_list,
  286. struct vdec_fb_node, list);
  287. node->fb = inst->cur_fb;
  288. list_move_tail(&node->list, &inst->fb_use_list);
  289. /* available_fb_node_list -> fb_disp_list */
  290. if (inst->vsi->dec.show_frame) {
  291. node = list_first_entry(&inst->available_fb_node_list,
  292. struct vdec_fb_node, list);
  293. node->fb = inst->cur_fb;
  294. list_move_tail(&node->list, &inst->fb_disp_list);
  295. }
  296. }
  297. static void move_fb_list_use_to_free(struct vdec_vp8_inst *inst)
  298. {
  299. struct vdec_fb_node *node, *tmp;
  300. list_for_each_entry_safe(node, tmp, &inst->fb_use_list, list)
  301. list_move_tail(&node->list, &inst->fb_free_list);
  302. }
  303. static void init_list(struct vdec_vp8_inst *inst)
  304. {
  305. int i;
  306. INIT_LIST_HEAD(&inst->available_fb_node_list);
  307. INIT_LIST_HEAD(&inst->fb_use_list);
  308. INIT_LIST_HEAD(&inst->fb_free_list);
  309. INIT_LIST_HEAD(&inst->fb_disp_list);
  310. for (i = 0; i < ARRAY_SIZE(inst->dec_fb); i++) {
  311. INIT_LIST_HEAD(&inst->dec_fb[i].list);
  312. inst->dec_fb[i].fb = NULL;
  313. list_add_tail(&inst->dec_fb[i].list,
  314. &inst->available_fb_node_list);
  315. }
  316. }
  317. static void add_fb_to_free_list(struct vdec_vp8_inst *inst, void *fb)
  318. {
  319. struct vdec_fb_node *node;
  320. if (fb) {
  321. node = list_first_entry(&inst->available_fb_node_list,
  322. struct vdec_fb_node, list);
  323. node->fb = fb;
  324. list_move_tail(&node->list, &inst->fb_free_list);
  325. }
  326. }
  327. static int alloc_working_buf(struct vdec_vp8_inst *inst)
  328. {
  329. int err;
  330. struct mtk_vcodec_mem *mem = &inst->working_buf;
  331. mem->size = VP8_WORKING_BUF_SZ;
  332. err = mtk_vcodec_mem_alloc(inst->ctx, mem);
  333. if (err) {
  334. mtk_vcodec_err(inst, "Cannot allocate working buffer");
  335. return err;
  336. }
  337. inst->vsi->dec.working_buf_dma = (uint64_t)mem->dma_addr;
  338. return 0;
  339. }
  340. static void free_working_buf(struct vdec_vp8_inst *inst)
  341. {
  342. struct mtk_vcodec_mem *mem = &inst->working_buf;
  343. if (mem->va)
  344. mtk_vcodec_mem_free(inst->ctx, mem);
  345. inst->vsi->dec.working_buf_dma = 0;
  346. }
  347. static int vdec_vp8_init(struct mtk_vcodec_ctx *ctx, unsigned long *h_vdec)
  348. {
  349. struct vdec_vp8_inst *inst;
  350. int err;
  351. inst = kzalloc(sizeof(*inst), GFP_KERNEL);
  352. if (!inst)
  353. return -ENOMEM;
  354. inst->ctx = ctx;
  355. inst->vpu.id = IPI_VDEC_VP8;
  356. inst->vpu.dev = ctx->dev->vpu_plat_dev;
  357. inst->vpu.ctx = ctx;
  358. inst->vpu.handler = vpu_dec_ipi_handler;
  359. err = vpu_dec_init(&inst->vpu);
  360. if (err) {
  361. mtk_vcodec_err(inst, "vdec_vp8 init err=%d", err);
  362. goto error_free_inst;
  363. }
  364. inst->vsi = (struct vdec_vp8_vsi *)inst->vpu.vsi;
  365. init_list(inst);
  366. err = alloc_working_buf(inst);
  367. if (err)
  368. goto error_deinit;
  369. get_hw_reg_base(inst);
  370. mtk_vcodec_debug(inst, "VP8 Instance >> %p", inst);
  371. *h_vdec = (unsigned long)inst;
  372. return 0;
  373. error_deinit:
  374. vpu_dec_deinit(&inst->vpu);
  375. error_free_inst:
  376. kfree(inst);
  377. return err;
  378. }
  379. static int vdec_vp8_decode(unsigned long h_vdec, struct mtk_vcodec_mem *bs,
  380. struct vdec_fb *fb, bool *res_chg)
  381. {
  382. struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec;
  383. struct vdec_vp8_dec_info *dec = &inst->vsi->dec;
  384. struct vdec_vpu_inst *vpu = &inst->vpu;
  385. unsigned char *bs_va;
  386. unsigned int data;
  387. int err = 0;
  388. uint64_t y_fb_dma;
  389. uint64_t c_fb_dma;
  390. /* bs NULL means flush decoder */
  391. if (bs == NULL) {
  392. move_fb_list_use_to_free(inst);
  393. return vpu_dec_reset(vpu);
  394. }
  395. y_fb_dma = fb ? (u64)fb->base_y.dma_addr : 0;
  396. c_fb_dma = fb ? (u64)fb->base_c.dma_addr : 0;
  397. mtk_vcodec_debug(inst, "+ [%d] FB y_dma=%llx c_dma=%llx fb=%p",
  398. inst->frm_cnt, y_fb_dma, c_fb_dma, fb);
  399. inst->cur_fb = fb;
  400. dec->bs_dma = (unsigned long)bs->dma_addr;
  401. dec->bs_sz = bs->size;
  402. dec->cur_y_fb_dma = y_fb_dma;
  403. dec->cur_c_fb_dma = c_fb_dma;
  404. mtk_vcodec_debug(inst, "\n + FRAME[%d] +\n", inst->frm_cnt);
  405. write_hw_segmentation_data(inst);
  406. enable_hw_rw_function(inst);
  407. store_dec_table(inst);
  408. bs_va = (unsigned char *)bs->va;
  409. /* retrieve width/hight and scale info from header */
  410. data = (*(bs_va + 9) << 24) | (*(bs_va + 8) << 16) |
  411. (*(bs_va + 7) << 8) | *(bs_va + 6);
  412. err = vpu_dec_start(vpu, &data, 1);
  413. if (err) {
  414. add_fb_to_free_list(inst, fb);
  415. if (dec->wait_key_frame) {
  416. mtk_vcodec_debug(inst, "wait key frame !");
  417. return 0;
  418. }
  419. goto error;
  420. }
  421. if (dec->resolution_changed) {
  422. mtk_vcodec_debug(inst, "- resolution_changed -");
  423. *res_chg = true;
  424. add_fb_to_free_list(inst, fb);
  425. return 0;
  426. }
  427. /* wait decoder done interrupt */
  428. mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
  429. WAIT_INTR_TIMEOUT_MS);
  430. if (inst->vsi->load_data)
  431. load_dec_table(inst);
  432. vp8_dec_finish(inst);
  433. read_hw_segmentation_data(inst);
  434. err = vpu_dec_end(vpu);
  435. if (err)
  436. goto error;
  437. mtk_vcodec_debug(inst, "\n - FRAME[%d] - show=%d\n", inst->frm_cnt,
  438. dec->show_frame);
  439. inst->frm_cnt++;
  440. *res_chg = false;
  441. return 0;
  442. error:
  443. mtk_vcodec_err(inst, "\n - FRAME[%d] - err=%d\n", inst->frm_cnt, err);
  444. return err;
  445. }
  446. static void get_disp_fb(struct vdec_vp8_inst *inst, struct vdec_fb **out_fb)
  447. {
  448. struct vdec_fb_node *node;
  449. struct vdec_fb *fb;
  450. node = list_first_entry_or_null(&inst->fb_disp_list,
  451. struct vdec_fb_node, list);
  452. if (node) {
  453. list_move_tail(&node->list, &inst->available_fb_node_list);
  454. fb = (struct vdec_fb *)node->fb;
  455. fb->status |= FB_ST_DISPLAY;
  456. mtk_vcodec_debug(inst, "[FB] get disp fb %p st=%d",
  457. node->fb, fb->status);
  458. } else {
  459. fb = NULL;
  460. mtk_vcodec_debug(inst, "[FB] there is no disp fb");
  461. }
  462. *out_fb = fb;
  463. }
  464. static void get_free_fb(struct vdec_vp8_inst *inst, struct vdec_fb **out_fb)
  465. {
  466. struct vdec_fb_node *node;
  467. struct vdec_fb *fb;
  468. node = list_first_entry_or_null(&inst->fb_free_list,
  469. struct vdec_fb_node, list);
  470. if (node) {
  471. list_move_tail(&node->list, &inst->available_fb_node_list);
  472. fb = (struct vdec_fb *)node->fb;
  473. fb->status |= FB_ST_FREE;
  474. mtk_vcodec_debug(inst, "[FB] get free fb %p st=%d",
  475. node->fb, fb->status);
  476. } else {
  477. fb = NULL;
  478. mtk_vcodec_debug(inst, "[FB] there is no free fb");
  479. }
  480. *out_fb = fb;
  481. }
  482. static void get_crop_info(struct vdec_vp8_inst *inst, struct v4l2_rect *cr)
  483. {
  484. cr->left = 0;
  485. cr->top = 0;
  486. cr->width = inst->vsi->pic.pic_w;
  487. cr->height = inst->vsi->pic.pic_h;
  488. mtk_vcodec_debug(inst, "get crop info l=%d, t=%d, w=%d, h=%d",
  489. cr->left, cr->top, cr->width, cr->height);
  490. }
  491. static int vdec_vp8_get_param(unsigned long h_vdec,
  492. enum vdec_get_param_type type, void *out)
  493. {
  494. struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec;
  495. switch (type) {
  496. case GET_PARAM_DISP_FRAME_BUFFER:
  497. get_disp_fb(inst, out);
  498. break;
  499. case GET_PARAM_FREE_FRAME_BUFFER:
  500. get_free_fb(inst, out);
  501. break;
  502. case GET_PARAM_PIC_INFO:
  503. get_pic_info(inst, out);
  504. break;
  505. case GET_PARAM_CROP_INFO:
  506. get_crop_info(inst, out);
  507. break;
  508. case GET_PARAM_DPB_SIZE:
  509. *((unsigned int *)out) = VP8_DPB_SIZE;
  510. break;
  511. default:
  512. mtk_vcodec_err(inst, "invalid get parameter type=%d", type);
  513. return -EINVAL;
  514. }
  515. return 0;
  516. }
  517. static void vdec_vp8_deinit(unsigned long h_vdec)
  518. {
  519. struct vdec_vp8_inst *inst = (struct vdec_vp8_inst *)h_vdec;
  520. mtk_vcodec_debug_enter(inst);
  521. vpu_dec_deinit(&inst->vpu);
  522. free_working_buf(inst);
  523. kfree(inst);
  524. }
  525. static struct vdec_common_if vdec_vp8_if = {
  526. .init = vdec_vp8_init,
  527. .decode = vdec_vp8_decode,
  528. .get_param = vdec_vp8_get_param,
  529. .deinit = vdec_vp8_deinit,
  530. };
  531. struct vdec_common_if *get_vp8_dec_comm_if(void);
  532. struct vdec_common_if *get_vp8_dec_comm_if(void)
  533. {
  534. return &vdec_vp8_if;
  535. }