pt1.c 30 KB

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  1. /*
  2. * driver for Earthsoft PT1/PT2
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/sched.h>
  21. #include <linux/sched/signal.h>
  22. #include <linux/hrtimer.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/pci.h>
  28. #include <linux/kthread.h>
  29. #include <linux/freezer.h>
  30. #include <linux/ratelimit.h>
  31. #include <linux/string.h>
  32. #include <linux/i2c.h>
  33. #include <media/dvbdev.h>
  34. #include <media/dvb_demux.h>
  35. #include <media/dmxdev.h>
  36. #include <media/dvb_net.h>
  37. #include <media/dvb_frontend.h>
  38. #include "tc90522.h"
  39. #include "qm1d1b0004.h"
  40. #include "dvb-pll.h"
  41. #define DRIVER_NAME "earth-pt1"
  42. #define PT1_PAGE_SHIFT 12
  43. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  44. #define PT1_NR_UPACKETS 1024
  45. #define PT1_NR_BUFS 511
  46. struct pt1_buffer_page {
  47. __le32 upackets[PT1_NR_UPACKETS];
  48. };
  49. struct pt1_table_page {
  50. __le32 next_pfn;
  51. __le32 buf_pfns[PT1_NR_BUFS];
  52. };
  53. struct pt1_buffer {
  54. struct pt1_buffer_page *page;
  55. dma_addr_t addr;
  56. };
  57. struct pt1_table {
  58. struct pt1_table_page *page;
  59. dma_addr_t addr;
  60. struct pt1_buffer bufs[PT1_NR_BUFS];
  61. };
  62. enum pt1_fe_clk {
  63. PT1_FE_CLK_20MHZ, /* PT1 */
  64. PT1_FE_CLK_25MHZ, /* PT2 */
  65. };
  66. #define PT1_NR_ADAPS 4
  67. struct pt1_adapter;
  68. struct pt1 {
  69. struct pci_dev *pdev;
  70. void __iomem *regs;
  71. struct i2c_adapter i2c_adap;
  72. int i2c_running;
  73. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  74. struct pt1_table *tables;
  75. struct task_struct *kthread;
  76. int table_index;
  77. int buf_index;
  78. struct mutex lock;
  79. int power;
  80. int reset;
  81. enum pt1_fe_clk fe_clk;
  82. };
  83. struct pt1_adapter {
  84. struct pt1 *pt1;
  85. int index;
  86. u8 *buf;
  87. int upacket_count;
  88. int packet_count;
  89. int st_count;
  90. struct dvb_adapter adap;
  91. struct dvb_demux demux;
  92. int users;
  93. struct dmxdev dmxdev;
  94. struct dvb_frontend *fe;
  95. struct i2c_client *demod_i2c_client;
  96. struct i2c_client *tuner_i2c_client;
  97. int (*orig_set_voltage)(struct dvb_frontend *fe,
  98. enum fe_sec_voltage voltage);
  99. int (*orig_sleep)(struct dvb_frontend *fe);
  100. int (*orig_init)(struct dvb_frontend *fe);
  101. enum fe_sec_voltage voltage;
  102. int sleep;
  103. };
  104. union pt1_tuner_config {
  105. struct qm1d1b0004_config qm1d1b0004;
  106. struct dvb_pll_config tda6651;
  107. };
  108. struct pt1_config {
  109. struct i2c_board_info demod_info;
  110. struct tc90522_config demod_cfg;
  111. struct i2c_board_info tuner_info;
  112. union pt1_tuner_config tuner_cfg;
  113. };
  114. static const struct pt1_config pt1_configs[PT1_NR_ADAPS] = {
  115. {
  116. .demod_info = {
  117. I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
  118. },
  119. .tuner_info = {
  120. I2C_BOARD_INFO("qm1d1b0004", 0x60),
  121. },
  122. },
  123. {
  124. .demod_info = {
  125. I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
  126. },
  127. .tuner_info = {
  128. I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
  129. },
  130. },
  131. {
  132. .demod_info = {
  133. I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
  134. },
  135. .tuner_info = {
  136. I2C_BOARD_INFO("qm1d1b0004", 0x60),
  137. },
  138. },
  139. {
  140. .demod_info = {
  141. I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
  142. },
  143. .tuner_info = {
  144. I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
  145. },
  146. },
  147. };
  148. static const u8 va1j5jf8007s_20mhz_configs[][2] = {
  149. {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
  150. {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
  151. {0x52, 0x89}, {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69},
  152. {0x87, 0x04}, {0x8e, 0x02}, {0xa3, 0xf7}, {0xa5, 0xc0},
  153. };
  154. static const u8 va1j5jf8007s_25mhz_configs[][2] = {
  155. {0x04, 0x02}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, {0x1c, 0x0a},
  156. {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, {0x52, 0x89},
  157. {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, {0x87, 0x04},
  158. {0x8e, 0x26}, {0xa3, 0xf7}, {0xa5, 0xc0},
  159. };
  160. static const u8 va1j5jf8007t_20mhz_configs[][2] = {
  161. {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2},
  162. {0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00},
  163. {0x3b, 0x11}, {0x3c, 0x3f},
  164. {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03},
  165. {0xef, 0x01}
  166. };
  167. static const u8 va1j5jf8007t_25mhz_configs[][2] = {
  168. {0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83},
  169. {0x3a, 0x04}, {0x3b, 0x11}, {0x3c, 0x3f}, {0x5c, 0x40}, {0x5f, 0x80},
  170. {0x75, 0x0a}, {0x76, 0x4c}, {0x77, 0x03}, {0xef, 0x01}
  171. };
  172. static int config_demod(struct i2c_client *cl, enum pt1_fe_clk clk)
  173. {
  174. int ret;
  175. u8 buf[2] = {0x01, 0x80};
  176. bool is_sat;
  177. const u8 (*cfg_data)[2];
  178. int i, len;
  179. ret = i2c_master_send(cl, buf, 2);
  180. if (ret < 0)
  181. return ret;
  182. usleep_range(30000, 50000);
  183. is_sat = !strncmp(cl->name, TC90522_I2C_DEV_SAT,
  184. strlen(TC90522_I2C_DEV_SAT));
  185. if (is_sat) {
  186. struct i2c_msg msg[2];
  187. u8 wbuf, rbuf;
  188. wbuf = 0x07;
  189. msg[0].addr = cl->addr;
  190. msg[0].flags = 0;
  191. msg[0].len = 1;
  192. msg[0].buf = &wbuf;
  193. msg[1].addr = cl->addr;
  194. msg[1].flags = I2C_M_RD;
  195. msg[1].len = 1;
  196. msg[1].buf = &rbuf;
  197. ret = i2c_transfer(cl->adapter, msg, 2);
  198. if (ret < 0)
  199. return ret;
  200. if (rbuf != 0x41)
  201. return -EIO;
  202. }
  203. /* frontend init */
  204. if (clk == PT1_FE_CLK_20MHZ) {
  205. if (is_sat) {
  206. cfg_data = va1j5jf8007s_20mhz_configs;
  207. len = ARRAY_SIZE(va1j5jf8007s_20mhz_configs);
  208. } else {
  209. cfg_data = va1j5jf8007t_20mhz_configs;
  210. len = ARRAY_SIZE(va1j5jf8007t_20mhz_configs);
  211. }
  212. } else {
  213. if (is_sat) {
  214. cfg_data = va1j5jf8007s_25mhz_configs;
  215. len = ARRAY_SIZE(va1j5jf8007s_25mhz_configs);
  216. } else {
  217. cfg_data = va1j5jf8007t_25mhz_configs;
  218. len = ARRAY_SIZE(va1j5jf8007t_25mhz_configs);
  219. }
  220. }
  221. for (i = 0; i < len; i++) {
  222. ret = i2c_master_send(cl, cfg_data[i], 2);
  223. if (ret < 0)
  224. return ret;
  225. }
  226. return 0;
  227. }
  228. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  229. {
  230. writel(data, pt1->regs + reg * 4);
  231. }
  232. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  233. {
  234. return readl(pt1->regs + reg * 4);
  235. }
  236. static unsigned int pt1_nr_tables = 8;
  237. module_param_named(nr_tables, pt1_nr_tables, uint, 0);
  238. static void pt1_increment_table_count(struct pt1 *pt1)
  239. {
  240. pt1_write_reg(pt1, 0, 0x00000020);
  241. }
  242. static void pt1_init_table_count(struct pt1 *pt1)
  243. {
  244. pt1_write_reg(pt1, 0, 0x00000010);
  245. }
  246. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  247. {
  248. pt1_write_reg(pt1, 5, first_pfn);
  249. pt1_write_reg(pt1, 0, 0x0c000040);
  250. }
  251. static void pt1_unregister_tables(struct pt1 *pt1)
  252. {
  253. pt1_write_reg(pt1, 0, 0x08080000);
  254. }
  255. static int pt1_sync(struct pt1 *pt1)
  256. {
  257. int i;
  258. for (i = 0; i < 57; i++) {
  259. if (pt1_read_reg(pt1, 0) & 0x20000000)
  260. return 0;
  261. pt1_write_reg(pt1, 0, 0x00000008);
  262. }
  263. dev_err(&pt1->pdev->dev, "could not sync\n");
  264. return -EIO;
  265. }
  266. static u64 pt1_identify(struct pt1 *pt1)
  267. {
  268. int i;
  269. u64 id;
  270. id = 0;
  271. for (i = 0; i < 57; i++) {
  272. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  273. pt1_write_reg(pt1, 0, 0x00000008);
  274. }
  275. return id;
  276. }
  277. static int pt1_unlock(struct pt1 *pt1)
  278. {
  279. int i;
  280. pt1_write_reg(pt1, 0, 0x00000008);
  281. for (i = 0; i < 3; i++) {
  282. if (pt1_read_reg(pt1, 0) & 0x80000000)
  283. return 0;
  284. usleep_range(1000, 2000);
  285. }
  286. dev_err(&pt1->pdev->dev, "could not unlock\n");
  287. return -EIO;
  288. }
  289. static int pt1_reset_pci(struct pt1 *pt1)
  290. {
  291. int i;
  292. pt1_write_reg(pt1, 0, 0x01010000);
  293. pt1_write_reg(pt1, 0, 0x01000000);
  294. for (i = 0; i < 10; i++) {
  295. if (pt1_read_reg(pt1, 0) & 0x00000001)
  296. return 0;
  297. usleep_range(1000, 2000);
  298. }
  299. dev_err(&pt1->pdev->dev, "could not reset PCI\n");
  300. return -EIO;
  301. }
  302. static int pt1_reset_ram(struct pt1 *pt1)
  303. {
  304. int i;
  305. pt1_write_reg(pt1, 0, 0x02020000);
  306. pt1_write_reg(pt1, 0, 0x02000000);
  307. for (i = 0; i < 10; i++) {
  308. if (pt1_read_reg(pt1, 0) & 0x00000002)
  309. return 0;
  310. usleep_range(1000, 2000);
  311. }
  312. dev_err(&pt1->pdev->dev, "could not reset RAM\n");
  313. return -EIO;
  314. }
  315. static int pt1_do_enable_ram(struct pt1 *pt1)
  316. {
  317. int i, j;
  318. u32 status;
  319. status = pt1_read_reg(pt1, 0) & 0x00000004;
  320. pt1_write_reg(pt1, 0, 0x00000002);
  321. for (i = 0; i < 10; i++) {
  322. for (j = 0; j < 1024; j++) {
  323. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  324. return 0;
  325. }
  326. usleep_range(1000, 2000);
  327. }
  328. dev_err(&pt1->pdev->dev, "could not enable RAM\n");
  329. return -EIO;
  330. }
  331. static int pt1_enable_ram(struct pt1 *pt1)
  332. {
  333. int i, ret;
  334. int phase;
  335. usleep_range(1000, 2000);
  336. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  337. for (i = 0; i < phase; i++) {
  338. ret = pt1_do_enable_ram(pt1);
  339. if (ret < 0)
  340. return ret;
  341. }
  342. return 0;
  343. }
  344. static void pt1_disable_ram(struct pt1 *pt1)
  345. {
  346. pt1_write_reg(pt1, 0, 0x0b0b0000);
  347. }
  348. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  349. {
  350. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  351. }
  352. static void pt1_init_streams(struct pt1 *pt1)
  353. {
  354. int i;
  355. for (i = 0; i < PT1_NR_ADAPS; i++)
  356. pt1_set_stream(pt1, i, 0);
  357. }
  358. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  359. {
  360. u32 upacket;
  361. int i;
  362. int index;
  363. struct pt1_adapter *adap;
  364. int offset;
  365. u8 *buf;
  366. int sc;
  367. if (!page->upackets[PT1_NR_UPACKETS - 1])
  368. return 0;
  369. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  370. upacket = le32_to_cpu(page->upackets[i]);
  371. index = (upacket >> 29) - 1;
  372. if (index < 0 || index >= PT1_NR_ADAPS)
  373. continue;
  374. adap = pt1->adaps[index];
  375. if (upacket >> 25 & 1)
  376. adap->upacket_count = 0;
  377. else if (!adap->upacket_count)
  378. continue;
  379. if (upacket >> 24 & 1)
  380. printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n",
  381. pt1->table_index, pt1->buf_index);
  382. sc = upacket >> 26 & 0x7;
  383. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  384. printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n",
  385. index);
  386. adap->st_count = sc;
  387. buf = adap->buf;
  388. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  389. buf[offset] = upacket >> 16;
  390. buf[offset + 1] = upacket >> 8;
  391. if (adap->upacket_count != 62)
  392. buf[offset + 2] = upacket;
  393. if (++adap->upacket_count >= 63) {
  394. adap->upacket_count = 0;
  395. if (++adap->packet_count >= 21) {
  396. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  397. adap->packet_count = 0;
  398. }
  399. }
  400. }
  401. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  402. return 1;
  403. }
  404. static int pt1_thread(void *data)
  405. {
  406. struct pt1 *pt1;
  407. struct pt1_buffer_page *page;
  408. bool was_frozen;
  409. #define PT1_FETCH_DELAY 10
  410. #define PT1_FETCH_DELAY_DELTA 2
  411. pt1 = data;
  412. set_freezable();
  413. while (!kthread_freezable_should_stop(&was_frozen)) {
  414. if (was_frozen) {
  415. int i;
  416. for (i = 0; i < PT1_NR_ADAPS; i++)
  417. pt1_set_stream(pt1, i, !!pt1->adaps[i]->users);
  418. }
  419. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  420. if (!pt1_filter(pt1, page)) {
  421. ktime_t delay;
  422. delay = ktime_set(0, PT1_FETCH_DELAY * NSEC_PER_MSEC);
  423. set_current_state(TASK_INTERRUPTIBLE);
  424. schedule_hrtimeout_range(&delay,
  425. PT1_FETCH_DELAY_DELTA * NSEC_PER_MSEC,
  426. HRTIMER_MODE_REL);
  427. continue;
  428. }
  429. if (++pt1->buf_index >= PT1_NR_BUFS) {
  430. pt1_increment_table_count(pt1);
  431. pt1->buf_index = 0;
  432. if (++pt1->table_index >= pt1_nr_tables)
  433. pt1->table_index = 0;
  434. }
  435. }
  436. return 0;
  437. }
  438. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  439. {
  440. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  441. }
  442. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  443. {
  444. void *page;
  445. dma_addr_t addr;
  446. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  447. GFP_KERNEL);
  448. if (page == NULL)
  449. return NULL;
  450. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  451. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  452. *addrp = addr;
  453. *pfnp = addr >> PT1_PAGE_SHIFT;
  454. return page;
  455. }
  456. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  457. {
  458. pt1_free_page(pt1, buf->page, buf->addr);
  459. }
  460. static int
  461. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  462. {
  463. struct pt1_buffer_page *page;
  464. dma_addr_t addr;
  465. page = pt1_alloc_page(pt1, &addr, pfnp);
  466. if (page == NULL)
  467. return -ENOMEM;
  468. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  469. buf->page = page;
  470. buf->addr = addr;
  471. return 0;
  472. }
  473. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  474. {
  475. int i;
  476. for (i = 0; i < PT1_NR_BUFS; i++)
  477. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  478. pt1_free_page(pt1, table->page, table->addr);
  479. }
  480. static int
  481. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  482. {
  483. struct pt1_table_page *page;
  484. dma_addr_t addr;
  485. int i, ret;
  486. u32 buf_pfn;
  487. page = pt1_alloc_page(pt1, &addr, pfnp);
  488. if (page == NULL)
  489. return -ENOMEM;
  490. for (i = 0; i < PT1_NR_BUFS; i++) {
  491. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  492. if (ret < 0)
  493. goto err;
  494. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  495. }
  496. pt1_increment_table_count(pt1);
  497. table->page = page;
  498. table->addr = addr;
  499. return 0;
  500. err:
  501. while (i--)
  502. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  503. pt1_free_page(pt1, page, addr);
  504. return ret;
  505. }
  506. static void pt1_cleanup_tables(struct pt1 *pt1)
  507. {
  508. struct pt1_table *tables;
  509. int i;
  510. tables = pt1->tables;
  511. pt1_unregister_tables(pt1);
  512. for (i = 0; i < pt1_nr_tables; i++)
  513. pt1_cleanup_table(pt1, &tables[i]);
  514. vfree(tables);
  515. }
  516. static int pt1_init_tables(struct pt1 *pt1)
  517. {
  518. struct pt1_table *tables;
  519. int i, ret;
  520. u32 first_pfn, pfn;
  521. if (!pt1_nr_tables)
  522. return 0;
  523. tables = vmalloc(array_size(pt1_nr_tables, sizeof(struct pt1_table)));
  524. if (tables == NULL)
  525. return -ENOMEM;
  526. pt1_init_table_count(pt1);
  527. i = 0;
  528. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  529. if (ret)
  530. goto err;
  531. i++;
  532. while (i < pt1_nr_tables) {
  533. ret = pt1_init_table(pt1, &tables[i], &pfn);
  534. if (ret)
  535. goto err;
  536. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  537. i++;
  538. }
  539. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  540. pt1_register_tables(pt1, first_pfn);
  541. pt1->tables = tables;
  542. return 0;
  543. err:
  544. while (i--)
  545. pt1_cleanup_table(pt1, &tables[i]);
  546. vfree(tables);
  547. return ret;
  548. }
  549. static int pt1_start_polling(struct pt1 *pt1)
  550. {
  551. int ret = 0;
  552. mutex_lock(&pt1->lock);
  553. if (!pt1->kthread) {
  554. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  555. if (IS_ERR(pt1->kthread)) {
  556. ret = PTR_ERR(pt1->kthread);
  557. pt1->kthread = NULL;
  558. }
  559. }
  560. mutex_unlock(&pt1->lock);
  561. return ret;
  562. }
  563. static int pt1_start_feed(struct dvb_demux_feed *feed)
  564. {
  565. struct pt1_adapter *adap;
  566. adap = container_of(feed->demux, struct pt1_adapter, demux);
  567. if (!adap->users++) {
  568. int ret;
  569. ret = pt1_start_polling(adap->pt1);
  570. if (ret)
  571. return ret;
  572. pt1_set_stream(adap->pt1, adap->index, 1);
  573. }
  574. return 0;
  575. }
  576. static void pt1_stop_polling(struct pt1 *pt1)
  577. {
  578. int i, count;
  579. mutex_lock(&pt1->lock);
  580. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  581. count += pt1->adaps[i]->users;
  582. if (count == 0 && pt1->kthread) {
  583. kthread_stop(pt1->kthread);
  584. pt1->kthread = NULL;
  585. }
  586. mutex_unlock(&pt1->lock);
  587. }
  588. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  589. {
  590. struct pt1_adapter *adap;
  591. adap = container_of(feed->demux, struct pt1_adapter, demux);
  592. if (!--adap->users) {
  593. pt1_set_stream(adap->pt1, adap->index, 0);
  594. pt1_stop_polling(adap->pt1);
  595. }
  596. return 0;
  597. }
  598. static void
  599. pt1_update_power(struct pt1 *pt1)
  600. {
  601. int bits;
  602. int i;
  603. struct pt1_adapter *adap;
  604. static const int sleep_bits[] = {
  605. 1 << 4,
  606. 1 << 6 | 1 << 7,
  607. 1 << 5,
  608. 1 << 6 | 1 << 8,
  609. };
  610. bits = pt1->power | !pt1->reset << 3;
  611. mutex_lock(&pt1->lock);
  612. for (i = 0; i < PT1_NR_ADAPS; i++) {
  613. adap = pt1->adaps[i];
  614. switch (adap->voltage) {
  615. case SEC_VOLTAGE_13: /* actually 11V */
  616. bits |= 1 << 2;
  617. break;
  618. case SEC_VOLTAGE_18: /* actually 15V */
  619. bits |= 1 << 1 | 1 << 2;
  620. break;
  621. default:
  622. break;
  623. }
  624. /* XXX: The bits should be changed depending on adap->sleep. */
  625. bits |= sleep_bits[i];
  626. }
  627. pt1_write_reg(pt1, 1, bits);
  628. mutex_unlock(&pt1->lock);
  629. }
  630. static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
  631. {
  632. struct pt1_adapter *adap;
  633. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  634. adap->voltage = voltage;
  635. pt1_update_power(adap->pt1);
  636. if (adap->orig_set_voltage)
  637. return adap->orig_set_voltage(fe, voltage);
  638. else
  639. return 0;
  640. }
  641. static int pt1_sleep(struct dvb_frontend *fe)
  642. {
  643. struct pt1_adapter *adap;
  644. int ret;
  645. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  646. ret = 0;
  647. if (adap->orig_sleep)
  648. ret = adap->orig_sleep(fe);
  649. adap->sleep = 1;
  650. pt1_update_power(adap->pt1);
  651. return ret;
  652. }
  653. static int pt1_wakeup(struct dvb_frontend *fe)
  654. {
  655. struct pt1_adapter *adap;
  656. int ret;
  657. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  658. adap->sleep = 0;
  659. pt1_update_power(adap->pt1);
  660. usleep_range(1000, 2000);
  661. ret = config_demod(adap->demod_i2c_client, adap->pt1->fe_clk);
  662. if (ret == 0 && adap->orig_init)
  663. ret = adap->orig_init(fe);
  664. return ret;
  665. }
  666. static void pt1_free_adapter(struct pt1_adapter *adap)
  667. {
  668. adap->demux.dmx.close(&adap->demux.dmx);
  669. dvb_dmxdev_release(&adap->dmxdev);
  670. dvb_dmx_release(&adap->demux);
  671. dvb_unregister_adapter(&adap->adap);
  672. free_page((unsigned long)adap->buf);
  673. kfree(adap);
  674. }
  675. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  676. static struct pt1_adapter *
  677. pt1_alloc_adapter(struct pt1 *pt1)
  678. {
  679. struct pt1_adapter *adap;
  680. void *buf;
  681. struct dvb_adapter *dvb_adap;
  682. struct dvb_demux *demux;
  683. struct dmxdev *dmxdev;
  684. int ret;
  685. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  686. if (!adap) {
  687. ret = -ENOMEM;
  688. goto err;
  689. }
  690. adap->pt1 = pt1;
  691. adap->voltage = SEC_VOLTAGE_OFF;
  692. adap->sleep = 1;
  693. buf = (u8 *)__get_free_page(GFP_KERNEL);
  694. if (!buf) {
  695. ret = -ENOMEM;
  696. goto err_kfree;
  697. }
  698. adap->buf = buf;
  699. adap->upacket_count = 0;
  700. adap->packet_count = 0;
  701. adap->st_count = -1;
  702. dvb_adap = &adap->adap;
  703. dvb_adap->priv = adap;
  704. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  705. &pt1->pdev->dev, adapter_nr);
  706. if (ret < 0)
  707. goto err_free_page;
  708. demux = &adap->demux;
  709. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  710. demux->priv = adap;
  711. demux->feednum = 256;
  712. demux->filternum = 256;
  713. demux->start_feed = pt1_start_feed;
  714. demux->stop_feed = pt1_stop_feed;
  715. demux->write_to_decoder = NULL;
  716. ret = dvb_dmx_init(demux);
  717. if (ret < 0)
  718. goto err_unregister_adapter;
  719. dmxdev = &adap->dmxdev;
  720. dmxdev->filternum = 256;
  721. dmxdev->demux = &demux->dmx;
  722. dmxdev->capabilities = 0;
  723. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  724. if (ret < 0)
  725. goto err_dmx_release;
  726. return adap;
  727. err_dmx_release:
  728. dvb_dmx_release(demux);
  729. err_unregister_adapter:
  730. dvb_unregister_adapter(dvb_adap);
  731. err_free_page:
  732. free_page((unsigned long)buf);
  733. err_kfree:
  734. kfree(adap);
  735. err:
  736. return ERR_PTR(ret);
  737. }
  738. static void pt1_cleanup_adapters(struct pt1 *pt1)
  739. {
  740. int i;
  741. for (i = 0; i < PT1_NR_ADAPS; i++)
  742. pt1_free_adapter(pt1->adaps[i]);
  743. }
  744. static int pt1_init_adapters(struct pt1 *pt1)
  745. {
  746. int i;
  747. struct pt1_adapter *adap;
  748. int ret;
  749. for (i = 0; i < PT1_NR_ADAPS; i++) {
  750. adap = pt1_alloc_adapter(pt1);
  751. if (IS_ERR(adap)) {
  752. ret = PTR_ERR(adap);
  753. goto err;
  754. }
  755. adap->index = i;
  756. pt1->adaps[i] = adap;
  757. }
  758. return 0;
  759. err:
  760. while (i--)
  761. pt1_free_adapter(pt1->adaps[i]);
  762. return ret;
  763. }
  764. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  765. {
  766. dvb_unregister_frontend(adap->fe);
  767. dvb_module_release(adap->tuner_i2c_client);
  768. dvb_module_release(adap->demod_i2c_client);
  769. }
  770. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  771. {
  772. int ret;
  773. adap->orig_set_voltage = fe->ops.set_voltage;
  774. adap->orig_sleep = fe->ops.sleep;
  775. adap->orig_init = fe->ops.init;
  776. fe->ops.set_voltage = pt1_set_voltage;
  777. fe->ops.sleep = pt1_sleep;
  778. fe->ops.init = pt1_wakeup;
  779. ret = dvb_register_frontend(&adap->adap, fe);
  780. if (ret < 0)
  781. return ret;
  782. adap->fe = fe;
  783. return 0;
  784. }
  785. static void pt1_cleanup_frontends(struct pt1 *pt1)
  786. {
  787. int i;
  788. for (i = 0; i < PT1_NR_ADAPS; i++)
  789. pt1_cleanup_frontend(pt1->adaps[i]);
  790. }
  791. static int pt1_init_frontends(struct pt1 *pt1)
  792. {
  793. int i;
  794. int ret;
  795. for (i = 0; i < ARRAY_SIZE(pt1_configs); i++) {
  796. const struct i2c_board_info *info;
  797. struct tc90522_config dcfg;
  798. struct i2c_client *cl;
  799. info = &pt1_configs[i].demod_info;
  800. dcfg = pt1_configs[i].demod_cfg;
  801. dcfg.tuner_i2c = NULL;
  802. ret = -ENODEV;
  803. cl = dvb_module_probe("tc90522", info->type, &pt1->i2c_adap,
  804. info->addr, &dcfg);
  805. if (!cl)
  806. goto fe_unregister;
  807. pt1->adaps[i]->demod_i2c_client = cl;
  808. if (!strncmp(cl->name, TC90522_I2C_DEV_SAT,
  809. strlen(TC90522_I2C_DEV_SAT))) {
  810. struct qm1d1b0004_config tcfg;
  811. info = &pt1_configs[i].tuner_info;
  812. tcfg = pt1_configs[i].tuner_cfg.qm1d1b0004;
  813. tcfg.fe = dcfg.fe;
  814. cl = dvb_module_probe("qm1d1b0004",
  815. info->type, dcfg.tuner_i2c,
  816. info->addr, &tcfg);
  817. } else {
  818. struct dvb_pll_config tcfg;
  819. info = &pt1_configs[i].tuner_info;
  820. tcfg = pt1_configs[i].tuner_cfg.tda6651;
  821. tcfg.fe = dcfg.fe;
  822. cl = dvb_module_probe("dvb_pll",
  823. info->type, dcfg.tuner_i2c,
  824. info->addr, &tcfg);
  825. }
  826. if (!cl)
  827. goto demod_release;
  828. pt1->adaps[i]->tuner_i2c_client = cl;
  829. ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe);
  830. if (ret < 0)
  831. goto tuner_release;
  832. }
  833. return 0;
  834. tuner_release:
  835. dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
  836. demod_release:
  837. dvb_module_release(pt1->adaps[i]->demod_i2c_client);
  838. fe_unregister:
  839. dev_warn(&pt1->pdev->dev, "failed to init FE(%d).\n", i);
  840. i--;
  841. for (; i >= 0; i--) {
  842. dvb_unregister_frontend(pt1->adaps[i]->fe);
  843. dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
  844. dvb_module_release(pt1->adaps[i]->demod_i2c_client);
  845. }
  846. return ret;
  847. }
  848. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  849. int clock, int data, int next_addr)
  850. {
  851. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  852. !clock << 11 | !data << 10 | next_addr);
  853. }
  854. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  855. {
  856. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  857. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  858. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  859. *addrp = addr + 3;
  860. }
  861. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  862. {
  863. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  864. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  865. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  866. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  867. *addrp = addr + 4;
  868. }
  869. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  870. {
  871. int i;
  872. for (i = 0; i < 8; i++)
  873. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  874. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  875. *addrp = addr;
  876. }
  877. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  878. {
  879. int i;
  880. for (i = 0; i < 8; i++)
  881. pt1_i2c_read_bit(pt1, addr, &addr);
  882. pt1_i2c_write_bit(pt1, addr, &addr, last);
  883. *addrp = addr;
  884. }
  885. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  886. {
  887. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  888. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  889. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  890. *addrp = addr + 3;
  891. }
  892. static void
  893. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  894. {
  895. int i;
  896. pt1_i2c_prepare(pt1, addr, &addr);
  897. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  898. for (i = 0; i < msg->len; i++)
  899. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  900. *addrp = addr;
  901. }
  902. static void
  903. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  904. {
  905. int i;
  906. pt1_i2c_prepare(pt1, addr, &addr);
  907. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  908. for (i = 0; i < msg->len; i++)
  909. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  910. *addrp = addr;
  911. }
  912. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  913. {
  914. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  915. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  916. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  917. pt1_write_reg(pt1, 0, 0x00000004);
  918. do {
  919. if (signal_pending(current))
  920. return -EINTR;
  921. usleep_range(1000, 2000);
  922. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  923. return 0;
  924. }
  925. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  926. {
  927. int addr;
  928. addr = 0;
  929. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  930. addr = addr + 1;
  931. if (!pt1->i2c_running) {
  932. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  933. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  934. addr = addr + 2;
  935. pt1->i2c_running = 1;
  936. }
  937. *addrp = addr;
  938. }
  939. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  940. {
  941. struct pt1 *pt1;
  942. int i;
  943. struct i2c_msg *msg, *next_msg;
  944. int addr, ret;
  945. u16 len;
  946. u32 word;
  947. pt1 = i2c_get_adapdata(adap);
  948. for (i = 0; i < num; i++) {
  949. msg = &msgs[i];
  950. if (msg->flags & I2C_M_RD)
  951. return -ENOTSUPP;
  952. if (i + 1 < num)
  953. next_msg = &msgs[i + 1];
  954. else
  955. next_msg = NULL;
  956. if (next_msg && next_msg->flags & I2C_M_RD) {
  957. i++;
  958. len = next_msg->len;
  959. if (len > 4)
  960. return -ENOTSUPP;
  961. pt1_i2c_begin(pt1, &addr);
  962. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  963. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  964. ret = pt1_i2c_end(pt1, addr);
  965. if (ret < 0)
  966. return ret;
  967. word = pt1_read_reg(pt1, 2);
  968. while (len--) {
  969. next_msg->buf[len] = word;
  970. word >>= 8;
  971. }
  972. } else {
  973. pt1_i2c_begin(pt1, &addr);
  974. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  975. ret = pt1_i2c_end(pt1, addr);
  976. if (ret < 0)
  977. return ret;
  978. }
  979. }
  980. return num;
  981. }
  982. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  983. {
  984. return I2C_FUNC_I2C;
  985. }
  986. static const struct i2c_algorithm pt1_i2c_algo = {
  987. .master_xfer = pt1_i2c_xfer,
  988. .functionality = pt1_i2c_func,
  989. };
  990. static void pt1_i2c_wait(struct pt1 *pt1)
  991. {
  992. int i;
  993. for (i = 0; i < 128; i++)
  994. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  995. }
  996. static void pt1_i2c_init(struct pt1 *pt1)
  997. {
  998. int i;
  999. for (i = 0; i < 1024; i++)
  1000. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  1001. }
  1002. #ifdef CONFIG_PM_SLEEP
  1003. static int pt1_suspend(struct device *dev)
  1004. {
  1005. struct pci_dev *pdev = to_pci_dev(dev);
  1006. struct pt1 *pt1 = pci_get_drvdata(pdev);
  1007. pt1_init_streams(pt1);
  1008. pt1_disable_ram(pt1);
  1009. pt1->power = 0;
  1010. pt1->reset = 1;
  1011. pt1_update_power(pt1);
  1012. return 0;
  1013. }
  1014. static int pt1_resume(struct device *dev)
  1015. {
  1016. struct pci_dev *pdev = to_pci_dev(dev);
  1017. struct pt1 *pt1 = pci_get_drvdata(pdev);
  1018. int ret;
  1019. int i;
  1020. pt1->power = 0;
  1021. pt1->reset = 1;
  1022. pt1_update_power(pt1);
  1023. pt1_i2c_init(pt1);
  1024. pt1_i2c_wait(pt1);
  1025. ret = pt1_sync(pt1);
  1026. if (ret < 0)
  1027. goto resume_err;
  1028. pt1_identify(pt1);
  1029. ret = pt1_unlock(pt1);
  1030. if (ret < 0)
  1031. goto resume_err;
  1032. ret = pt1_reset_pci(pt1);
  1033. if (ret < 0)
  1034. goto resume_err;
  1035. ret = pt1_reset_ram(pt1);
  1036. if (ret < 0)
  1037. goto resume_err;
  1038. ret = pt1_enable_ram(pt1);
  1039. if (ret < 0)
  1040. goto resume_err;
  1041. pt1_init_streams(pt1);
  1042. pt1->power = 1;
  1043. pt1_update_power(pt1);
  1044. msleep(20);
  1045. pt1->reset = 0;
  1046. pt1_update_power(pt1);
  1047. usleep_range(1000, 2000);
  1048. for (i = 0; i < PT1_NR_ADAPS; i++)
  1049. dvb_frontend_reinitialise(pt1->adaps[i]->fe);
  1050. pt1_init_table_count(pt1);
  1051. for (i = 0; i < pt1_nr_tables; i++) {
  1052. int j;
  1053. for (j = 0; j < PT1_NR_BUFS; j++)
  1054. pt1->tables[i].bufs[j].page->upackets[PT1_NR_UPACKETS-1]
  1055. = 0;
  1056. pt1_increment_table_count(pt1);
  1057. }
  1058. pt1_register_tables(pt1, pt1->tables[0].addr >> PT1_PAGE_SHIFT);
  1059. pt1->table_index = 0;
  1060. pt1->buf_index = 0;
  1061. for (i = 0; i < PT1_NR_ADAPS; i++) {
  1062. pt1->adaps[i]->upacket_count = 0;
  1063. pt1->adaps[i]->packet_count = 0;
  1064. pt1->adaps[i]->st_count = -1;
  1065. }
  1066. return 0;
  1067. resume_err:
  1068. dev_info(&pt1->pdev->dev, "failed to resume PT1/PT2.");
  1069. return 0; /* resume anyway */
  1070. }
  1071. #endif /* CONFIG_PM_SLEEP */
  1072. static void pt1_remove(struct pci_dev *pdev)
  1073. {
  1074. struct pt1 *pt1;
  1075. void __iomem *regs;
  1076. pt1 = pci_get_drvdata(pdev);
  1077. regs = pt1->regs;
  1078. if (pt1->kthread)
  1079. kthread_stop(pt1->kthread);
  1080. pt1_cleanup_tables(pt1);
  1081. pt1_cleanup_frontends(pt1);
  1082. pt1_disable_ram(pt1);
  1083. pt1->power = 0;
  1084. pt1->reset = 1;
  1085. pt1_update_power(pt1);
  1086. pt1_cleanup_adapters(pt1);
  1087. i2c_del_adapter(&pt1->i2c_adap);
  1088. kfree(pt1);
  1089. pci_iounmap(pdev, regs);
  1090. pci_release_regions(pdev);
  1091. pci_disable_device(pdev);
  1092. }
  1093. static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1094. {
  1095. int ret;
  1096. void __iomem *regs;
  1097. struct pt1 *pt1;
  1098. struct i2c_adapter *i2c_adap;
  1099. ret = pci_enable_device(pdev);
  1100. if (ret < 0)
  1101. goto err;
  1102. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  1103. if (ret < 0)
  1104. goto err_pci_disable_device;
  1105. pci_set_master(pdev);
  1106. ret = pci_request_regions(pdev, DRIVER_NAME);
  1107. if (ret < 0)
  1108. goto err_pci_disable_device;
  1109. regs = pci_iomap(pdev, 0, 0);
  1110. if (!regs) {
  1111. ret = -EIO;
  1112. goto err_pci_release_regions;
  1113. }
  1114. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  1115. if (!pt1) {
  1116. ret = -ENOMEM;
  1117. goto err_pci_iounmap;
  1118. }
  1119. mutex_init(&pt1->lock);
  1120. pt1->pdev = pdev;
  1121. pt1->regs = regs;
  1122. pt1->fe_clk = (pdev->device == 0x211a) ?
  1123. PT1_FE_CLK_20MHZ : PT1_FE_CLK_25MHZ;
  1124. pci_set_drvdata(pdev, pt1);
  1125. ret = pt1_init_adapters(pt1);
  1126. if (ret < 0)
  1127. goto err_kfree;
  1128. mutex_init(&pt1->lock);
  1129. pt1->power = 0;
  1130. pt1->reset = 1;
  1131. pt1_update_power(pt1);
  1132. i2c_adap = &pt1->i2c_adap;
  1133. i2c_adap->algo = &pt1_i2c_algo;
  1134. i2c_adap->algo_data = NULL;
  1135. i2c_adap->dev.parent = &pdev->dev;
  1136. strcpy(i2c_adap->name, DRIVER_NAME);
  1137. i2c_set_adapdata(i2c_adap, pt1);
  1138. ret = i2c_add_adapter(i2c_adap);
  1139. if (ret < 0)
  1140. goto err_pt1_cleanup_adapters;
  1141. pt1_i2c_init(pt1);
  1142. pt1_i2c_wait(pt1);
  1143. ret = pt1_sync(pt1);
  1144. if (ret < 0)
  1145. goto err_i2c_del_adapter;
  1146. pt1_identify(pt1);
  1147. ret = pt1_unlock(pt1);
  1148. if (ret < 0)
  1149. goto err_i2c_del_adapter;
  1150. ret = pt1_reset_pci(pt1);
  1151. if (ret < 0)
  1152. goto err_i2c_del_adapter;
  1153. ret = pt1_reset_ram(pt1);
  1154. if (ret < 0)
  1155. goto err_i2c_del_adapter;
  1156. ret = pt1_enable_ram(pt1);
  1157. if (ret < 0)
  1158. goto err_i2c_del_adapter;
  1159. pt1_init_streams(pt1);
  1160. pt1->power = 1;
  1161. pt1_update_power(pt1);
  1162. msleep(20);
  1163. pt1->reset = 0;
  1164. pt1_update_power(pt1);
  1165. usleep_range(1000, 2000);
  1166. ret = pt1_init_frontends(pt1);
  1167. if (ret < 0)
  1168. goto err_pt1_disable_ram;
  1169. ret = pt1_init_tables(pt1);
  1170. if (ret < 0)
  1171. goto err_pt1_cleanup_frontends;
  1172. return 0;
  1173. err_pt1_cleanup_frontends:
  1174. pt1_cleanup_frontends(pt1);
  1175. err_pt1_disable_ram:
  1176. pt1_disable_ram(pt1);
  1177. pt1->power = 0;
  1178. pt1->reset = 1;
  1179. pt1_update_power(pt1);
  1180. err_i2c_del_adapter:
  1181. i2c_del_adapter(i2c_adap);
  1182. err_pt1_cleanup_adapters:
  1183. pt1_cleanup_adapters(pt1);
  1184. err_kfree:
  1185. kfree(pt1);
  1186. err_pci_iounmap:
  1187. pci_iounmap(pdev, regs);
  1188. err_pci_release_regions:
  1189. pci_release_regions(pdev);
  1190. err_pci_disable_device:
  1191. pci_disable_device(pdev);
  1192. err:
  1193. return ret;
  1194. }
  1195. static const struct pci_device_id pt1_id_table[] = {
  1196. { PCI_DEVICE(0x10ee, 0x211a) },
  1197. { PCI_DEVICE(0x10ee, 0x222a) },
  1198. { },
  1199. };
  1200. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1201. static SIMPLE_DEV_PM_OPS(pt1_pm_ops, pt1_suspend, pt1_resume);
  1202. static struct pci_driver pt1_driver = {
  1203. .name = DRIVER_NAME,
  1204. .probe = pt1_probe,
  1205. .remove = pt1_remove,
  1206. .id_table = pt1_id_table,
  1207. .driver.pm = &pt1_pm_ops,
  1208. };
  1209. module_pci_driver(pt1_driver);
  1210. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  1211. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1212. MODULE_LICENSE("GPL");