m5mols_controls.c 17 KB

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  1. /*
  2. * Controls for M-5MOLS 8M Pixel camera sensor with ISP
  3. *
  4. * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  5. * Author: HeungJun Kim <riverful.kim@samsung.com>
  6. *
  7. * Copyright (C) 2009 Samsung Electronics Co., Ltd.
  8. * Author: Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. #include <linux/i2c.h>
  16. #include <linux/delay.h>
  17. #include <linux/videodev2.h>
  18. #include <media/v4l2-ctrls.h>
  19. #include "m5mols.h"
  20. #include "m5mols_reg.h"
  21. static struct m5mols_scenemode m5mols_default_scenemode[] = {
  22. [REG_SCENE_NORMAL] = {
  23. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  24. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  25. REG_AF_NORMAL, REG_FD_OFF,
  26. REG_MCC_NORMAL, REG_LIGHT_OFF, REG_FLASH_OFF,
  27. 5, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  28. },
  29. [REG_SCENE_PORTRAIT] = {
  30. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  31. REG_CHROMA_ON, 3, REG_EDGE_ON, 4,
  32. REG_AF_NORMAL, BIT_FD_EN | BIT_FD_DRAW_FACE_FRAME,
  33. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  34. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  35. },
  36. [REG_SCENE_LANDSCAPE] = {
  37. REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  38. REG_CHROMA_ON, 4, REG_EDGE_ON, 6,
  39. REG_AF_NORMAL, REG_FD_OFF,
  40. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  41. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  42. },
  43. [REG_SCENE_SPORTS] = {
  44. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  45. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  46. REG_AF_NORMAL, REG_FD_OFF,
  47. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  48. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  49. },
  50. [REG_SCENE_PARTY_INDOOR] = {
  51. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  52. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  53. REG_AF_NORMAL, REG_FD_OFF,
  54. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  55. 6, REG_ISO_200, REG_CAP_NONE, REG_WDR_OFF,
  56. },
  57. [REG_SCENE_BEACH_SNOW] = {
  58. REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
  59. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  60. REG_AF_NORMAL, REG_FD_OFF,
  61. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  62. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  63. },
  64. [REG_SCENE_SUNSET] = {
  65. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  66. REG_AWB_DAYLIGHT,
  67. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  68. REG_AF_NORMAL, REG_FD_OFF,
  69. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  70. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  71. },
  72. [REG_SCENE_DAWN_DUSK] = {
  73. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  74. REG_AWB_FLUORESCENT_1,
  75. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  76. REG_AF_NORMAL, REG_FD_OFF,
  77. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  78. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  79. },
  80. [REG_SCENE_FALL] = {
  81. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  82. REG_CHROMA_ON, 5, REG_EDGE_ON, 5,
  83. REG_AF_NORMAL, REG_FD_OFF,
  84. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  85. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  86. },
  87. [REG_SCENE_NIGHT] = {
  88. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  89. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  90. REG_AF_NORMAL, REG_FD_OFF,
  91. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  92. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  93. },
  94. [REG_SCENE_AGAINST_LIGHT] = {
  95. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  96. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  97. REG_AF_NORMAL, REG_FD_OFF,
  98. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  99. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  100. },
  101. [REG_SCENE_FIRE] = {
  102. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  103. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  104. REG_AF_NORMAL, REG_FD_OFF,
  105. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  106. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  107. },
  108. [REG_SCENE_TEXT] = {
  109. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  110. REG_CHROMA_ON, 3, REG_EDGE_ON, 7,
  111. REG_AF_MACRO, REG_FD_OFF,
  112. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  113. 6, REG_ISO_AUTO, REG_CAP_ANTI_SHAKE, REG_WDR_ON,
  114. },
  115. [REG_SCENE_CANDLE] = {
  116. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  117. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  118. REG_AF_NORMAL, REG_FD_OFF,
  119. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  120. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  121. },
  122. };
  123. /**
  124. * m5mols_do_scenemode() - Change current scenemode
  125. * @info: M-5MOLS driver data structure
  126. * @mode: Desired mode of the scenemode
  127. *
  128. * WARNING: The execution order is important. Do not change the order.
  129. */
  130. int m5mols_do_scenemode(struct m5mols_info *info, u8 mode)
  131. {
  132. struct v4l2_subdev *sd = &info->sd;
  133. struct m5mols_scenemode scenemode = m5mols_default_scenemode[mode];
  134. int ret;
  135. if (mode > REG_SCENE_CANDLE)
  136. return -EINVAL;
  137. ret = v4l2_ctrl_s_ctrl(info->lock_3a, 0);
  138. if (!ret)
  139. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, mode);
  140. if (!ret)
  141. ret = m5mols_write(sd, AE_EV_PRESET_CAPTURE, mode);
  142. if (!ret)
  143. ret = m5mols_write(sd, AE_MODE, scenemode.metering);
  144. if (!ret)
  145. ret = m5mols_write(sd, AE_INDEX, scenemode.ev_bias);
  146. if (!ret)
  147. ret = m5mols_write(sd, AWB_MODE, scenemode.wb_mode);
  148. if (!ret)
  149. ret = m5mols_write(sd, AWB_MANUAL, scenemode.wb_preset);
  150. if (!ret)
  151. ret = m5mols_write(sd, MON_CHROMA_EN, scenemode.chroma_en);
  152. if (!ret)
  153. ret = m5mols_write(sd, MON_CHROMA_LVL, scenemode.chroma_lvl);
  154. if (!ret)
  155. ret = m5mols_write(sd, MON_EDGE_EN, scenemode.edge_en);
  156. if (!ret)
  157. ret = m5mols_write(sd, MON_EDGE_LVL, scenemode.edge_lvl);
  158. if (!ret && is_available_af(info))
  159. ret = m5mols_write(sd, AF_MODE, scenemode.af_range);
  160. if (!ret && is_available_af(info))
  161. ret = m5mols_write(sd, FD_CTL, scenemode.fd_mode);
  162. if (!ret)
  163. ret = m5mols_write(sd, MON_TONE_CTL, scenemode.tone);
  164. if (!ret)
  165. ret = m5mols_write(sd, AE_ISO, scenemode.iso);
  166. if (!ret)
  167. ret = m5mols_set_mode(info, REG_CAPTURE);
  168. if (!ret)
  169. ret = m5mols_write(sd, CAPP_WDR_EN, scenemode.wdr);
  170. if (!ret)
  171. ret = m5mols_write(sd, CAPP_MCC_MODE, scenemode.mcc);
  172. if (!ret)
  173. ret = m5mols_write(sd, CAPP_LIGHT_CTRL, scenemode.light);
  174. if (!ret)
  175. ret = m5mols_write(sd, CAPP_FLASH_CTRL, scenemode.flash);
  176. if (!ret)
  177. ret = m5mols_write(sd, CAPC_MODE, scenemode.capt_mode);
  178. if (!ret)
  179. ret = m5mols_set_mode(info, REG_MONITOR);
  180. return ret;
  181. }
  182. static int m5mols_3a_lock(struct m5mols_info *info, struct v4l2_ctrl *ctrl)
  183. {
  184. bool af_lock = ctrl->val & V4L2_LOCK_FOCUS;
  185. int ret = 0;
  186. if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) {
  187. bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
  188. ret = m5mols_write(&info->sd, AE_LOCK, ae_lock ?
  189. REG_AE_LOCK : REG_AE_UNLOCK);
  190. if (ret)
  191. return ret;
  192. }
  193. if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
  194. && info->auto_wb->val) {
  195. bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
  196. ret = m5mols_write(&info->sd, AWB_LOCK, awb_lock ?
  197. REG_AWB_LOCK : REG_AWB_UNLOCK);
  198. if (ret)
  199. return ret;
  200. }
  201. if (!info->ver.af || !af_lock)
  202. return ret;
  203. if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS)
  204. ret = m5mols_write(&info->sd, AF_EXECUTE, REG_AF_STOP);
  205. return ret;
  206. }
  207. static int m5mols_set_metering_mode(struct m5mols_info *info, int mode)
  208. {
  209. unsigned int metering;
  210. switch (mode) {
  211. case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
  212. metering = REG_AE_CENTER;
  213. break;
  214. case V4L2_EXPOSURE_METERING_SPOT:
  215. metering = REG_AE_SPOT;
  216. break;
  217. default:
  218. metering = REG_AE_ALL;
  219. break;
  220. }
  221. return m5mols_write(&info->sd, AE_MODE, metering);
  222. }
  223. static int m5mols_set_exposure(struct m5mols_info *info, int exposure)
  224. {
  225. struct v4l2_subdev *sd = &info->sd;
  226. int ret = 0;
  227. if (exposure == V4L2_EXPOSURE_AUTO) {
  228. /* Unlock auto exposure */
  229. info->lock_3a->val &= ~V4L2_LOCK_EXPOSURE;
  230. m5mols_3a_lock(info, info->lock_3a);
  231. ret = m5mols_set_metering_mode(info, info->metering->val);
  232. if (ret < 0)
  233. return ret;
  234. v4l2_dbg(1, m5mols_debug, sd,
  235. "%s: exposure bias: %#x, metering: %#x\n",
  236. __func__, info->exposure_bias->val,
  237. info->metering->val);
  238. return m5mols_write(sd, AE_INDEX, info->exposure_bias->val);
  239. }
  240. if (exposure == V4L2_EXPOSURE_MANUAL) {
  241. ret = m5mols_write(sd, AE_MODE, REG_AE_OFF);
  242. if (ret == 0)
  243. ret = m5mols_write(sd, AE_MAN_GAIN_MON,
  244. info->exposure->val);
  245. if (ret == 0)
  246. ret = m5mols_write(sd, AE_MAN_GAIN_CAP,
  247. info->exposure->val);
  248. v4l2_dbg(1, m5mols_debug, sd, "%s: exposure: %#x\n",
  249. __func__, info->exposure->val);
  250. }
  251. return ret;
  252. }
  253. static int m5mols_set_white_balance(struct m5mols_info *info, int val)
  254. {
  255. static const unsigned short wb[][2] = {
  256. { V4L2_WHITE_BALANCE_INCANDESCENT, REG_AWB_INCANDESCENT },
  257. { V4L2_WHITE_BALANCE_FLUORESCENT, REG_AWB_FLUORESCENT_1 },
  258. { V4L2_WHITE_BALANCE_FLUORESCENT_H, REG_AWB_FLUORESCENT_2 },
  259. { V4L2_WHITE_BALANCE_HORIZON, REG_AWB_HORIZON },
  260. { V4L2_WHITE_BALANCE_DAYLIGHT, REG_AWB_DAYLIGHT },
  261. { V4L2_WHITE_BALANCE_FLASH, REG_AWB_LEDLIGHT },
  262. { V4L2_WHITE_BALANCE_CLOUDY, REG_AWB_CLOUDY },
  263. { V4L2_WHITE_BALANCE_SHADE, REG_AWB_SHADE },
  264. { V4L2_WHITE_BALANCE_AUTO, REG_AWB_AUTO },
  265. };
  266. int i;
  267. struct v4l2_subdev *sd = &info->sd;
  268. int ret = -EINVAL;
  269. for (i = 0; i < ARRAY_SIZE(wb); i++) {
  270. int awb;
  271. if (wb[i][0] != val)
  272. continue;
  273. v4l2_dbg(1, m5mols_debug, sd,
  274. "Setting white balance to: %#x\n", wb[i][0]);
  275. awb = wb[i][0] == V4L2_WHITE_BALANCE_AUTO;
  276. ret = m5mols_write(sd, AWB_MODE, awb ? REG_AWB_AUTO :
  277. REG_AWB_PRESET);
  278. if (ret < 0)
  279. return ret;
  280. if (!awb)
  281. ret = m5mols_write(sd, AWB_MANUAL, wb[i][1]);
  282. }
  283. return ret;
  284. }
  285. static int m5mols_set_saturation(struct m5mols_info *info, int val)
  286. {
  287. int ret = m5mols_write(&info->sd, MON_CHROMA_LVL, val);
  288. if (ret < 0)
  289. return ret;
  290. return m5mols_write(&info->sd, MON_CHROMA_EN, REG_CHROMA_ON);
  291. }
  292. static int m5mols_set_color_effect(struct m5mols_info *info, int val)
  293. {
  294. unsigned int m_effect = REG_COLOR_EFFECT_OFF;
  295. unsigned int p_effect = REG_EFFECT_OFF;
  296. unsigned int cfix_r = 0, cfix_b = 0;
  297. struct v4l2_subdev *sd = &info->sd;
  298. int ret = 0;
  299. switch (val) {
  300. case V4L2_COLORFX_BW:
  301. m_effect = REG_COLOR_EFFECT_ON;
  302. break;
  303. case V4L2_COLORFX_NEGATIVE:
  304. p_effect = REG_EFFECT_NEGA;
  305. break;
  306. case V4L2_COLORFX_EMBOSS:
  307. p_effect = REG_EFFECT_EMBOSS;
  308. break;
  309. case V4L2_COLORFX_SEPIA:
  310. m_effect = REG_COLOR_EFFECT_ON;
  311. cfix_r = REG_CFIXR_SEPIA;
  312. cfix_b = REG_CFIXB_SEPIA;
  313. break;
  314. }
  315. ret = m5mols_write(sd, PARM_EFFECT, p_effect);
  316. if (!ret)
  317. ret = m5mols_write(sd, MON_EFFECT, m_effect);
  318. if (ret == 0 && m_effect == REG_COLOR_EFFECT_ON) {
  319. ret = m5mols_write(sd, MON_CFIXR, cfix_r);
  320. if (!ret)
  321. ret = m5mols_write(sd, MON_CFIXB, cfix_b);
  322. }
  323. v4l2_dbg(1, m5mols_debug, sd,
  324. "p_effect: %#x, m_effect: %#x, r: %#x, b: %#x (%d)\n",
  325. p_effect, m_effect, cfix_r, cfix_b, ret);
  326. return ret;
  327. }
  328. static int m5mols_set_iso(struct m5mols_info *info, int auto_iso)
  329. {
  330. u32 iso = auto_iso ? 0 : info->iso->val + 1;
  331. return m5mols_write(&info->sd, AE_ISO, iso);
  332. }
  333. static int m5mols_set_wdr(struct m5mols_info *info, int wdr)
  334. {
  335. int ret;
  336. ret = m5mols_write(&info->sd, MON_TONE_CTL, wdr ? 9 : 5);
  337. if (ret < 0)
  338. return ret;
  339. ret = m5mols_set_mode(info, REG_CAPTURE);
  340. if (ret < 0)
  341. return ret;
  342. return m5mols_write(&info->sd, CAPP_WDR_EN, wdr);
  343. }
  344. static int m5mols_set_stabilization(struct m5mols_info *info, int val)
  345. {
  346. struct v4l2_subdev *sd = &info->sd;
  347. unsigned int evp = val ? 0xe : 0x0;
  348. int ret;
  349. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, evp);
  350. if (ret < 0)
  351. return ret;
  352. return m5mols_write(sd, AE_EV_PRESET_CAPTURE, evp);
  353. }
  354. static int m5mols_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
  355. {
  356. struct v4l2_subdev *sd = to_sd(ctrl);
  357. struct m5mols_info *info = to_m5mols(sd);
  358. int ret = 0;
  359. u8 status = REG_ISO_AUTO;
  360. v4l2_dbg(1, m5mols_debug, sd, "%s: ctrl: %s (%d)\n",
  361. __func__, ctrl->name, info->isp_ready);
  362. if (!info->isp_ready)
  363. return -EBUSY;
  364. switch (ctrl->id) {
  365. case V4L2_CID_ISO_SENSITIVITY_AUTO:
  366. ret = m5mols_read_u8(sd, AE_ISO, &status);
  367. if (ret == 0)
  368. ctrl->val = !status;
  369. if (status != REG_ISO_AUTO)
  370. info->iso->val = status - 1;
  371. break;
  372. case V4L2_CID_3A_LOCK:
  373. ctrl->val &= ~0x7;
  374. ret = m5mols_read_u8(sd, AE_LOCK, &status);
  375. if (ret)
  376. return ret;
  377. if (status)
  378. info->lock_3a->val |= V4L2_LOCK_EXPOSURE;
  379. ret = m5mols_read_u8(sd, AWB_LOCK, &status);
  380. if (ret)
  381. return ret;
  382. if (status)
  383. info->lock_3a->val |= V4L2_LOCK_EXPOSURE;
  384. ret = m5mols_read_u8(sd, AF_EXECUTE, &status);
  385. if (!status)
  386. info->lock_3a->val |= V4L2_LOCK_EXPOSURE;
  387. break;
  388. }
  389. return ret;
  390. }
  391. static int m5mols_s_ctrl(struct v4l2_ctrl *ctrl)
  392. {
  393. unsigned int ctrl_mode = m5mols_get_ctrl_mode(ctrl);
  394. struct v4l2_subdev *sd = to_sd(ctrl);
  395. struct m5mols_info *info = to_m5mols(sd);
  396. int last_mode = info->mode;
  397. int ret = 0;
  398. /*
  399. * If needed, defer restoring the controls until
  400. * the device is fully initialized.
  401. */
  402. if (!info->isp_ready) {
  403. info->ctrl_sync = 0;
  404. return 0;
  405. }
  406. v4l2_dbg(1, m5mols_debug, sd, "%s: %s, val: %d, priv: %p\n",
  407. __func__, ctrl->name, ctrl->val, ctrl->priv);
  408. if (ctrl_mode && ctrl_mode != info->mode) {
  409. ret = m5mols_set_mode(info, ctrl_mode);
  410. if (ret < 0)
  411. return ret;
  412. }
  413. switch (ctrl->id) {
  414. case V4L2_CID_3A_LOCK:
  415. ret = m5mols_3a_lock(info, ctrl);
  416. break;
  417. case V4L2_CID_ZOOM_ABSOLUTE:
  418. ret = m5mols_write(sd, MON_ZOOM, ctrl->val);
  419. break;
  420. case V4L2_CID_EXPOSURE_AUTO:
  421. ret = m5mols_set_exposure(info, ctrl->val);
  422. break;
  423. case V4L2_CID_ISO_SENSITIVITY:
  424. ret = m5mols_set_iso(info, ctrl->val);
  425. break;
  426. case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
  427. ret = m5mols_set_white_balance(info, ctrl->val);
  428. break;
  429. case V4L2_CID_SATURATION:
  430. ret = m5mols_set_saturation(info, ctrl->val);
  431. break;
  432. case V4L2_CID_COLORFX:
  433. ret = m5mols_set_color_effect(info, ctrl->val);
  434. break;
  435. case V4L2_CID_WIDE_DYNAMIC_RANGE:
  436. ret = m5mols_set_wdr(info, ctrl->val);
  437. break;
  438. case V4L2_CID_IMAGE_STABILIZATION:
  439. ret = m5mols_set_stabilization(info, ctrl->val);
  440. break;
  441. case V4L2_CID_JPEG_COMPRESSION_QUALITY:
  442. ret = m5mols_write(sd, CAPP_JPEG_RATIO, ctrl->val);
  443. break;
  444. }
  445. if (ret == 0 && info->mode != last_mode)
  446. ret = m5mols_set_mode(info, last_mode);
  447. return ret;
  448. }
  449. static const struct v4l2_ctrl_ops m5mols_ctrl_ops = {
  450. .g_volatile_ctrl = m5mols_g_volatile_ctrl,
  451. .s_ctrl = m5mols_s_ctrl,
  452. };
  453. /* Supported manual ISO values */
  454. static const s64 iso_qmenu[] = {
  455. /* AE_ISO: 0x01...0x07 (ISO: 50...3200) */
  456. 50000, 100000, 200000, 400000, 800000, 1600000, 3200000
  457. };
  458. /* Supported Exposure Bias values, -2.0EV...+2.0EV */
  459. static const s64 ev_bias_qmenu[] = {
  460. /* AE_INDEX: 0x00...0x08 */
  461. -2000, -1500, -1000, -500, 0, 500, 1000, 1500, 2000
  462. };
  463. int m5mols_init_controls(struct v4l2_subdev *sd)
  464. {
  465. struct m5mols_info *info = to_m5mols(sd);
  466. u16 exposure_max;
  467. u16 zoom_step;
  468. int ret;
  469. /* Determine the firmware dependent control range and step values */
  470. ret = m5mols_read_u16(sd, AE_MAX_GAIN_MON, &exposure_max);
  471. if (ret < 0)
  472. return ret;
  473. zoom_step = is_manufacturer(info, REG_SAMSUNG_OPTICS) ? 31 : 1;
  474. v4l2_ctrl_handler_init(&info->handle, 20);
  475. info->auto_wb = v4l2_ctrl_new_std_menu(&info->handle,
  476. &m5mols_ctrl_ops, V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
  477. 9, ~0x3fe, V4L2_WHITE_BALANCE_AUTO);
  478. /* Exposure control cluster */
  479. info->auto_exposure = v4l2_ctrl_new_std_menu(&info->handle,
  480. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
  481. 1, ~0x03, V4L2_EXPOSURE_AUTO);
  482. info->exposure = v4l2_ctrl_new_std(&info->handle,
  483. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE,
  484. 0, exposure_max, 1, exposure_max / 2);
  485. info->exposure_bias = v4l2_ctrl_new_int_menu(&info->handle,
  486. &m5mols_ctrl_ops, V4L2_CID_AUTO_EXPOSURE_BIAS,
  487. ARRAY_SIZE(ev_bias_qmenu) - 1,
  488. ARRAY_SIZE(ev_bias_qmenu)/2 - 1,
  489. ev_bias_qmenu);
  490. info->metering = v4l2_ctrl_new_std_menu(&info->handle,
  491. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE_METERING,
  492. 2, ~0x7, V4L2_EXPOSURE_METERING_AVERAGE);
  493. /* ISO control cluster */
  494. info->auto_iso = v4l2_ctrl_new_std_menu(&info->handle, &m5mols_ctrl_ops,
  495. V4L2_CID_ISO_SENSITIVITY_AUTO, 1, ~0x03, 1);
  496. info->iso = v4l2_ctrl_new_int_menu(&info->handle, &m5mols_ctrl_ops,
  497. V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
  498. ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
  499. info->saturation = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  500. V4L2_CID_SATURATION, 1, 5, 1, 3);
  501. info->zoom = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  502. V4L2_CID_ZOOM_ABSOLUTE, 1, 70, zoom_step, 1);
  503. info->colorfx = v4l2_ctrl_new_std_menu(&info->handle, &m5mols_ctrl_ops,
  504. V4L2_CID_COLORFX, 4, 0, V4L2_COLORFX_NONE);
  505. info->wdr = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  506. V4L2_CID_WIDE_DYNAMIC_RANGE, 0, 1, 1, 0);
  507. info->stabilization = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  508. V4L2_CID_IMAGE_STABILIZATION, 0, 1, 1, 0);
  509. info->jpeg_quality = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  510. V4L2_CID_JPEG_COMPRESSION_QUALITY, 1, 100, 1, 80);
  511. info->lock_3a = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  512. V4L2_CID_3A_LOCK, 0, 0x7, 0, 0);
  513. if (info->handle.error) {
  514. int ret = info->handle.error;
  515. v4l2_err(sd, "Failed to initialize controls: %d\n", ret);
  516. v4l2_ctrl_handler_free(&info->handle);
  517. return ret;
  518. }
  519. v4l2_ctrl_auto_cluster(4, &info->auto_exposure, 1, false);
  520. info->auto_iso->flags |= V4L2_CTRL_FLAG_VOLATILE |
  521. V4L2_CTRL_FLAG_UPDATE;
  522. v4l2_ctrl_auto_cluster(2, &info->auto_iso, 0, false);
  523. info->lock_3a->flags |= V4L2_CTRL_FLAG_VOLATILE;
  524. m5mols_set_ctrl_mode(info->auto_exposure, REG_PARAMETER);
  525. m5mols_set_ctrl_mode(info->auto_wb, REG_PARAMETER);
  526. m5mols_set_ctrl_mode(info->colorfx, REG_MONITOR);
  527. sd->ctrl_handler = &info->handle;
  528. return 0;
  529. }