hideep.c 25 KB

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  1. /*
  2. * Copyright (C) 2012-2017 Hideep, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License version 2
  6. * as published by the Free Software Foudation.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/firmware.h>
  11. #include <linux/delay.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/i2c.h>
  14. #include <linux/acpi.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/regmap.h>
  17. #include <linux/sysfs.h>
  18. #include <linux/input.h>
  19. #include <linux/input/mt.h>
  20. #include <linux/input/touchscreen.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <asm/unaligned.h>
  23. #define HIDEEP_TS_NAME "HiDeep Touchscreen"
  24. #define HIDEEP_I2C_NAME "hideep_ts"
  25. #define HIDEEP_MT_MAX 10
  26. #define HIDEEP_KEY_MAX 3
  27. /* count(2) + touch data(100) + key data(6) */
  28. #define HIDEEP_MAX_EVENT 108UL
  29. #define HIDEEP_TOUCH_EVENT_INDEX 2
  30. #define HIDEEP_KEY_EVENT_INDEX 102
  31. /* Touch & key event */
  32. #define HIDEEP_EVENT_ADDR 0x240
  33. /* command list */
  34. #define HIDEEP_RESET_CMD 0x9800
  35. /* event bit */
  36. #define HIDEEP_MT_RELEASED BIT(4)
  37. #define HIDEEP_KEY_PRESSED BIT(7)
  38. #define HIDEEP_KEY_FIRST_PRESSED BIT(8)
  39. #define HIDEEP_KEY_PRESSED_MASK (HIDEEP_KEY_PRESSED | \
  40. HIDEEP_KEY_FIRST_PRESSED)
  41. #define HIDEEP_KEY_IDX_MASK 0x0f
  42. /* For NVM */
  43. #define HIDEEP_YRAM_BASE 0x40000000
  44. #define HIDEEP_PERIPHERAL_BASE 0x50000000
  45. #define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000)
  46. #define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000)
  47. #define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000)
  48. #define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000)
  49. #define HIDEEP_SYSCON_SPC_CON (HIDEEP_SYSCON_BASE + 0x0004)
  50. #define HIDEEP_SYSCON_CLK_CON (HIDEEP_SYSCON_BASE + 0x0008)
  51. #define HIDEEP_SYSCON_CLK_ENA (HIDEEP_SYSCON_BASE + 0x000C)
  52. #define HIDEEP_SYSCON_RST_CON (HIDEEP_SYSCON_BASE + 0x0010)
  53. #define HIDEEP_SYSCON_WDT_CON (HIDEEP_SYSCON_BASE + 0x0014)
  54. #define HIDEEP_SYSCON_WDT_CNT (HIDEEP_SYSCON_BASE + 0x0018)
  55. #define HIDEEP_SYSCON_PWR_CON (HIDEEP_SYSCON_BASE + 0x0020)
  56. #define HIDEEP_SYSCON_PGM_ID (HIDEEP_SYSCON_BASE + 0x00F4)
  57. #define HIDEEP_FLASH_CON (HIDEEP_FLASH_BASE + 0x0000)
  58. #define HIDEEP_FLASH_STA (HIDEEP_FLASH_BASE + 0x0004)
  59. #define HIDEEP_FLASH_CFG (HIDEEP_FLASH_BASE + 0x0008)
  60. #define HIDEEP_FLASH_TIM (HIDEEP_FLASH_BASE + 0x000C)
  61. #define HIDEEP_FLASH_CACHE_CFG (HIDEEP_FLASH_BASE + 0x0010)
  62. #define HIDEEP_FLASH_PIO_SIG (HIDEEP_FLASH_BASE + 0x400000)
  63. #define HIDEEP_ESI_TX_INVALID (HIDEEP_ESI_BASE + 0x0008)
  64. #define HIDEEP_PERASE 0x00040000
  65. #define HIDEEP_WRONLY 0x00100000
  66. #define HIDEEP_NVM_MASK_OFS 0x0000000C
  67. #define HIDEEP_NVM_DEFAULT_PAGE 0
  68. #define HIDEEP_NVM_SFR_WPAGE 1
  69. #define HIDEEP_NVM_SFR_RPAGE 2
  70. #define HIDEEP_PIO_SIG 0x00400000
  71. #define HIDEEP_PROT_MODE 0x03400000
  72. #define HIDEEP_NVM_PAGE_SIZE 128
  73. #define HIDEEP_DWZ_INFO 0x000002C0
  74. struct hideep_event {
  75. __le16 x;
  76. __le16 y;
  77. __le16 z;
  78. u8 w;
  79. u8 flag;
  80. u8 type;
  81. u8 index;
  82. };
  83. struct dwz_info {
  84. __be32 code_start;
  85. u8 code_crc[12];
  86. __be32 c_code_start;
  87. __be16 gen_ver;
  88. __be16 c_code_len;
  89. __be32 vr_start;
  90. __be16 rsv0;
  91. __be16 vr_len;
  92. __be32 ft_start;
  93. __be16 vr_version;
  94. __be16 ft_len;
  95. __be16 core_ver;
  96. __be16 boot_ver;
  97. __be16 release_ver;
  98. __be16 custom_ver;
  99. u8 factory_id;
  100. u8 panel_type;
  101. u8 model_name[6];
  102. __be16 extra_option;
  103. __be16 product_code;
  104. __be16 vendor_id;
  105. __be16 product_id;
  106. };
  107. struct pgm_packet {
  108. struct {
  109. u8 unused[3];
  110. u8 len;
  111. __be32 addr;
  112. } header;
  113. __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
  114. };
  115. #define HIDEEP_XFER_BUF_SIZE sizeof(struct pgm_packet)
  116. struct hideep_ts {
  117. struct i2c_client *client;
  118. struct input_dev *input_dev;
  119. struct regmap *reg;
  120. struct touchscreen_properties prop;
  121. struct gpio_desc *reset_gpio;
  122. struct regulator *vcc_vdd;
  123. struct regulator *vcc_vid;
  124. struct mutex dev_mutex;
  125. u32 tch_count;
  126. u32 lpm_count;
  127. /*
  128. * Data buffer to read packet from the device (contacts and key
  129. * states). We align it on double-word boundary to keep word-sized
  130. * fields in contact data and double-word-sized fields in program
  131. * packet aligned.
  132. */
  133. u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
  134. int key_num;
  135. u32 key_codes[HIDEEP_KEY_MAX];
  136. struct dwz_info dwz_info;
  137. unsigned int fw_size;
  138. u32 nvm_mask;
  139. };
  140. static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
  141. const __be32 *data, size_t count)
  142. {
  143. struct pgm_packet *packet = (void *)ts->xfer_buf;
  144. size_t len = count * sizeof(*data);
  145. struct i2c_msg msg = {
  146. .addr = ts->client->addr,
  147. .len = len + sizeof(packet->header.len) +
  148. sizeof(packet->header.addr),
  149. .buf = &packet->header.len,
  150. };
  151. int ret;
  152. if (len > HIDEEP_NVM_PAGE_SIZE)
  153. return -EINVAL;
  154. packet->header.len = 0x80 | (count - 1);
  155. packet->header.addr = cpu_to_be32(addr);
  156. memcpy(packet->payload, data, len);
  157. ret = i2c_transfer(ts->client->adapter, &msg, 1);
  158. if (ret != 1)
  159. return ret < 0 ? ret : -EIO;
  160. return 0;
  161. }
  162. static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
  163. __be32 *data, size_t count)
  164. {
  165. struct pgm_packet *packet = (void *)ts->xfer_buf;
  166. size_t len = count * sizeof(*data);
  167. struct i2c_msg msg[] = {
  168. {
  169. .addr = ts->client->addr,
  170. .len = sizeof(packet->header.len) +
  171. sizeof(packet->header.addr),
  172. .buf = &packet->header.len,
  173. },
  174. {
  175. .addr = ts->client->addr,
  176. .flags = I2C_M_RD,
  177. .len = len,
  178. .buf = (u8 *)data,
  179. },
  180. };
  181. int ret;
  182. if (len > HIDEEP_NVM_PAGE_SIZE)
  183. return -EINVAL;
  184. packet->header.len = count - 1;
  185. packet->header.addr = cpu_to_be32(addr);
  186. ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
  187. if (ret != ARRAY_SIZE(msg))
  188. return ret < 0 ? ret : -EIO;
  189. return 0;
  190. }
  191. static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
  192. {
  193. __be32 data;
  194. int error;
  195. error = hideep_pgm_r_mem(ts, addr, &data, 1);
  196. if (error) {
  197. dev_err(&ts->client->dev,
  198. "read of register %#08x failed: %d\n",
  199. addr, error);
  200. return error;
  201. }
  202. *val = be32_to_cpu(data);
  203. return 0;
  204. }
  205. static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
  206. {
  207. __be32 data = cpu_to_be32(val);
  208. int error;
  209. error = hideep_pgm_w_mem(ts, addr, &data, 1);
  210. if (error) {
  211. dev_err(&ts->client->dev,
  212. "write to register %#08x (%#08x) failed: %d\n",
  213. addr, val, error);
  214. return error;
  215. }
  216. return 0;
  217. }
  218. #define SW_RESET_IN_PGM(clk) \
  219. { \
  220. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \
  221. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \
  222. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01); \
  223. }
  224. #define SET_FLASH_PIO(ce) \
  225. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \
  226. 0x01 | ((ce) << 1))
  227. #define SET_PIO_SIG(x, y) \
  228. hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
  229. #define SET_FLASH_HWCONTROL() \
  230. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
  231. #define NVM_W_SFR(x, y) \
  232. { \
  233. SET_FLASH_PIO(1); \
  234. SET_PIO_SIG(x, y); \
  235. SET_FLASH_PIO(0); \
  236. }
  237. static void hideep_pgm_set(struct hideep_ts *ts)
  238. {
  239. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
  240. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
  241. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
  242. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
  243. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
  244. hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
  245. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
  246. }
  247. static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
  248. {
  249. u16 p1 = 0xAF39;
  250. u16 p2 = 0xDF9D;
  251. int error;
  252. error = regmap_bulk_write(ts->reg, p1, &p2, 1);
  253. if (error) {
  254. dev_err(&ts->client->dev,
  255. "%s: regmap_bulk_write() failed with %d\n",
  256. __func__, error);
  257. return error;
  258. }
  259. usleep_range(1000, 1100);
  260. /* flush invalid Tx load register */
  261. error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
  262. if (error)
  263. return error;
  264. error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
  265. if (error)
  266. return error;
  267. return 0;
  268. }
  269. static int hideep_enter_pgm(struct hideep_ts *ts)
  270. {
  271. int retry_count = 10;
  272. u32 pattern;
  273. int error;
  274. while (retry_count--) {
  275. error = hideep_pgm_get_pattern(ts, &pattern);
  276. if (error) {
  277. dev_err(&ts->client->dev,
  278. "hideep_pgm_get_pattern failed: %d\n", error);
  279. } else if (pattern != 0x39AF9DDF) {
  280. dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
  281. __func__, pattern);
  282. } else {
  283. dev_dbg(&ts->client->dev, "found magic code");
  284. hideep_pgm_set(ts);
  285. usleep_range(1000, 1100);
  286. return 0;
  287. }
  288. }
  289. dev_err(&ts->client->dev, "failed to enter pgm mode\n");
  290. SW_RESET_IN_PGM(1000);
  291. return -EIO;
  292. }
  293. static void hideep_nvm_unlock(struct hideep_ts *ts)
  294. {
  295. u32 unmask_code;
  296. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
  297. hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
  298. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
  299. /* make it unprotected code */
  300. unmask_code &= ~HIDEEP_PROT_MODE;
  301. /* compare unmask code */
  302. if (unmask_code != ts->nvm_mask)
  303. dev_warn(&ts->client->dev,
  304. "read mask code different %#08x vs %#08x",
  305. unmask_code, ts->nvm_mask);
  306. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
  307. SET_FLASH_PIO(0);
  308. NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
  309. SET_FLASH_HWCONTROL();
  310. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
  311. }
  312. static int hideep_check_status(struct hideep_ts *ts)
  313. {
  314. int time_out = 100;
  315. int status;
  316. int error;
  317. while (time_out--) {
  318. error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
  319. if (!error && status)
  320. return 0;
  321. usleep_range(1000, 1100);
  322. }
  323. return -ETIMEDOUT;
  324. }
  325. static int hideep_program_page(struct hideep_ts *ts, u32 addr,
  326. const __be32 *ucode, size_t xfer_count)
  327. {
  328. u32 val;
  329. int error;
  330. error = hideep_check_status(ts);
  331. if (error)
  332. return -EBUSY;
  333. addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
  334. SET_FLASH_PIO(0);
  335. SET_FLASH_PIO(1);
  336. /* erase page */
  337. SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
  338. SET_FLASH_PIO(0);
  339. error = hideep_check_status(ts);
  340. if (error)
  341. return -EBUSY;
  342. /* write page */
  343. SET_FLASH_PIO(1);
  344. val = be32_to_cpu(ucode[0]);
  345. SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
  346. hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
  347. ucode, xfer_count);
  348. val = be32_to_cpu(ucode[xfer_count - 1]);
  349. SET_PIO_SIG(124, val);
  350. SET_FLASH_PIO(0);
  351. usleep_range(1000, 1100);
  352. error = hideep_check_status(ts);
  353. if (error)
  354. return -EBUSY;
  355. SET_FLASH_HWCONTROL();
  356. return 0;
  357. }
  358. static int hideep_program_nvm(struct hideep_ts *ts,
  359. const __be32 *ucode, size_t ucode_len)
  360. {
  361. struct pgm_packet *packet_r = (void *)ts->xfer_buf;
  362. __be32 *current_ucode = packet_r->payload;
  363. size_t xfer_len;
  364. size_t xfer_count;
  365. u32 addr = 0;
  366. int error;
  367. hideep_nvm_unlock(ts);
  368. while (ucode_len > 0) {
  369. xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
  370. xfer_count = xfer_len / sizeof(*ucode);
  371. error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
  372. current_ucode, xfer_count);
  373. if (error) {
  374. dev_err(&ts->client->dev,
  375. "%s: failed to read page at offset %#08x: %d\n",
  376. __func__, addr, error);
  377. return error;
  378. }
  379. /* See if the page needs updating */
  380. if (memcmp(ucode, current_ucode, xfer_len)) {
  381. error = hideep_program_page(ts, addr,
  382. ucode, xfer_count);
  383. if (error) {
  384. dev_err(&ts->client->dev,
  385. "%s: iwrite failure @%#08x: %d\n",
  386. __func__, addr, error);
  387. return error;
  388. }
  389. usleep_range(1000, 1100);
  390. }
  391. ucode += xfer_count;
  392. addr += xfer_len;
  393. ucode_len -= xfer_len;
  394. }
  395. return 0;
  396. }
  397. static int hideep_verify_nvm(struct hideep_ts *ts,
  398. const __be32 *ucode, size_t ucode_len)
  399. {
  400. struct pgm_packet *packet_r = (void *)ts->xfer_buf;
  401. __be32 *current_ucode = packet_r->payload;
  402. size_t xfer_len;
  403. size_t xfer_count;
  404. u32 addr = 0;
  405. int i;
  406. int error;
  407. while (ucode_len > 0) {
  408. xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
  409. xfer_count = xfer_len / sizeof(*ucode);
  410. error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
  411. current_ucode, xfer_count);
  412. if (error) {
  413. dev_err(&ts->client->dev,
  414. "%s: failed to read page at offset %#08x: %d\n",
  415. __func__, addr, error);
  416. return error;
  417. }
  418. if (memcmp(ucode, current_ucode, xfer_len)) {
  419. const u8 *ucode_bytes = (const u8 *)ucode;
  420. const u8 *current_bytes = (const u8 *)current_ucode;
  421. for (i = 0; i < xfer_len; i++)
  422. if (ucode_bytes[i] != current_bytes[i])
  423. dev_err(&ts->client->dev,
  424. "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
  425. __func__, addr + i,
  426. ucode_bytes[i],
  427. current_bytes[i]);
  428. return -EIO;
  429. }
  430. ucode += xfer_count;
  431. addr += xfer_len;
  432. ucode_len -= xfer_len;
  433. }
  434. return 0;
  435. }
  436. static int hideep_load_dwz(struct hideep_ts *ts)
  437. {
  438. u16 product_code;
  439. int error;
  440. error = hideep_enter_pgm(ts);
  441. if (error)
  442. return error;
  443. msleep(50);
  444. error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
  445. (void *)&ts->dwz_info,
  446. sizeof(ts->dwz_info) / sizeof(__be32));
  447. SW_RESET_IN_PGM(10);
  448. msleep(50);
  449. if (error) {
  450. dev_err(&ts->client->dev,
  451. "failed to fetch DWZ data: %d\n", error);
  452. return error;
  453. }
  454. product_code = be16_to_cpu(ts->dwz_info.product_code);
  455. switch (product_code & 0xF0) {
  456. case 0x40:
  457. dev_dbg(&ts->client->dev, "used crimson IC");
  458. ts->fw_size = 1024 * 48;
  459. ts->nvm_mask = 0x00310000;
  460. break;
  461. case 0x60:
  462. dev_dbg(&ts->client->dev, "used lime IC");
  463. ts->fw_size = 1024 * 64;
  464. ts->nvm_mask = 0x0030027B;
  465. break;
  466. default:
  467. dev_err(&ts->client->dev, "product code is wrong: %#04x",
  468. product_code);
  469. return -EINVAL;
  470. }
  471. dev_dbg(&ts->client->dev, "firmware release version: %#04x",
  472. be16_to_cpu(ts->dwz_info.release_ver));
  473. return 0;
  474. }
  475. static int hideep_flash_firmware(struct hideep_ts *ts,
  476. const __be32 *ucode, size_t ucode_len)
  477. {
  478. int retry_cnt = 3;
  479. int error;
  480. while (retry_cnt--) {
  481. error = hideep_program_nvm(ts, ucode, ucode_len);
  482. if (!error) {
  483. error = hideep_verify_nvm(ts, ucode, ucode_len);
  484. if (!error)
  485. return 0;
  486. }
  487. }
  488. return error;
  489. }
  490. static int hideep_update_firmware(struct hideep_ts *ts,
  491. const __be32 *ucode, size_t ucode_len)
  492. {
  493. int error, error2;
  494. dev_dbg(&ts->client->dev, "starting firmware update");
  495. /* enter program mode */
  496. error = hideep_enter_pgm(ts);
  497. if (error)
  498. return error;
  499. error = hideep_flash_firmware(ts, ucode, ucode_len);
  500. if (error)
  501. dev_err(&ts->client->dev,
  502. "firmware update failed: %d\n", error);
  503. else
  504. dev_dbg(&ts->client->dev, "firmware updated successfully\n");
  505. SW_RESET_IN_PGM(1000);
  506. error2 = hideep_load_dwz(ts);
  507. if (error2)
  508. dev_err(&ts->client->dev,
  509. "failed to load dwz after firmware update: %d\n",
  510. error2);
  511. return error ?: error2;
  512. }
  513. static int hideep_power_on(struct hideep_ts *ts)
  514. {
  515. int error = 0;
  516. error = regulator_enable(ts->vcc_vdd);
  517. if (error)
  518. dev_err(&ts->client->dev,
  519. "failed to enable 'vdd' regulator: %d", error);
  520. usleep_range(999, 1000);
  521. error = regulator_enable(ts->vcc_vid);
  522. if (error)
  523. dev_err(&ts->client->dev,
  524. "failed to enable 'vcc_vid' regulator: %d",
  525. error);
  526. msleep(30);
  527. if (ts->reset_gpio) {
  528. gpiod_set_value_cansleep(ts->reset_gpio, 0);
  529. } else {
  530. error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
  531. if (error)
  532. dev_err(&ts->client->dev,
  533. "failed to send 'reset' command: %d\n", error);
  534. }
  535. msleep(50);
  536. return error;
  537. }
  538. static void hideep_power_off(void *data)
  539. {
  540. struct hideep_ts *ts = data;
  541. if (ts->reset_gpio)
  542. gpiod_set_value(ts->reset_gpio, 1);
  543. regulator_disable(ts->vcc_vid);
  544. regulator_disable(ts->vcc_vdd);
  545. }
  546. #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
  547. static void hideep_report_slot(struct input_dev *input,
  548. const struct hideep_event *event)
  549. {
  550. input_mt_slot(input, event->index & 0x0f);
  551. input_mt_report_slot_state(input,
  552. __GET_MT_TOOL_TYPE(event->type),
  553. !(event->flag & HIDEEP_MT_RELEASED));
  554. if (!(event->flag & HIDEEP_MT_RELEASED)) {
  555. input_report_abs(input, ABS_MT_POSITION_X,
  556. le16_to_cpup(&event->x));
  557. input_report_abs(input, ABS_MT_POSITION_Y,
  558. le16_to_cpup(&event->y));
  559. input_report_abs(input, ABS_MT_PRESSURE,
  560. le16_to_cpup(&event->z));
  561. input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
  562. }
  563. }
  564. static void hideep_parse_and_report(struct hideep_ts *ts)
  565. {
  566. const struct hideep_event *events =
  567. (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
  568. const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
  569. int touch_count = ts->xfer_buf[0];
  570. int key_count = ts->xfer_buf[1] & 0x0f;
  571. int lpm_count = ts->xfer_buf[1] & 0xf0;
  572. int i;
  573. /* get touch event count */
  574. dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
  575. touch_count, key_count, lpm_count);
  576. touch_count = min(touch_count, HIDEEP_MT_MAX);
  577. for (i = 0; i < touch_count; i++)
  578. hideep_report_slot(ts->input_dev, events + i);
  579. key_count = min(key_count, HIDEEP_KEY_MAX);
  580. for (i = 0; i < key_count; i++) {
  581. u8 key_data = keys[i * 2];
  582. input_report_key(ts->input_dev,
  583. ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
  584. key_data & HIDEEP_KEY_PRESSED_MASK);
  585. }
  586. input_mt_sync_frame(ts->input_dev);
  587. input_sync(ts->input_dev);
  588. }
  589. static irqreturn_t hideep_irq(int irq, void *handle)
  590. {
  591. struct hideep_ts *ts = handle;
  592. int error;
  593. BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
  594. error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
  595. ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
  596. if (error) {
  597. dev_err(&ts->client->dev, "failed to read events: %d\n", error);
  598. goto out;
  599. }
  600. hideep_parse_and_report(ts);
  601. out:
  602. return IRQ_HANDLED;
  603. }
  604. static int hideep_get_axis_info(struct hideep_ts *ts)
  605. {
  606. __le16 val[2];
  607. int error;
  608. error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
  609. if (error)
  610. return error;
  611. ts->prop.max_x = le16_to_cpup(val);
  612. ts->prop.max_y = le16_to_cpup(val + 1);
  613. dev_dbg(&ts->client->dev, "X: %d, Y: %d",
  614. ts->prop.max_x, ts->prop.max_y);
  615. return 0;
  616. }
  617. static int hideep_init_input(struct hideep_ts *ts)
  618. {
  619. struct device *dev = &ts->client->dev;
  620. int i;
  621. int error;
  622. ts->input_dev = devm_input_allocate_device(dev);
  623. if (!ts->input_dev) {
  624. dev_err(dev, "failed to allocate input device\n");
  625. return -ENOMEM;
  626. }
  627. ts->input_dev->name = HIDEEP_TS_NAME;
  628. ts->input_dev->id.bustype = BUS_I2C;
  629. input_set_drvdata(ts->input_dev, ts);
  630. input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
  631. input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
  632. input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
  633. input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
  634. input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
  635. 0, MT_TOOL_MAX, 0, 0);
  636. touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
  637. if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
  638. error = hideep_get_axis_info(ts);
  639. if (error)
  640. return error;
  641. }
  642. error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
  643. INPUT_MT_DIRECT);
  644. if (error)
  645. return error;
  646. ts->key_num = device_property_read_u32_array(dev, "linux,keycodes",
  647. NULL, 0);
  648. if (ts->key_num > HIDEEP_KEY_MAX) {
  649. dev_err(dev, "too many keys defined: %d\n",
  650. ts->key_num);
  651. return -EINVAL;
  652. }
  653. if (ts->key_num <= 0) {
  654. dev_dbg(dev,
  655. "missing or malformed 'linux,keycodes' property\n");
  656. } else {
  657. error = device_property_read_u32_array(dev, "linux,keycodes",
  658. ts->key_codes,
  659. ts->key_num);
  660. if (error) {
  661. dev_dbg(dev, "failed to read keymap: %d", error);
  662. return error;
  663. }
  664. if (ts->key_num) {
  665. ts->input_dev->keycode = ts->key_codes;
  666. ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
  667. ts->input_dev->keycodemax = ts->key_num;
  668. for (i = 0; i < ts->key_num; i++)
  669. input_set_capability(ts->input_dev, EV_KEY,
  670. ts->key_codes[i]);
  671. }
  672. }
  673. error = input_register_device(ts->input_dev);
  674. if (error) {
  675. dev_err(dev, "failed to register input device: %d", error);
  676. return error;
  677. }
  678. return 0;
  679. }
  680. static ssize_t hideep_update_fw(struct device *dev,
  681. struct device_attribute *attr,
  682. const char *buf, size_t count)
  683. {
  684. struct i2c_client *client = to_i2c_client(dev);
  685. struct hideep_ts *ts = i2c_get_clientdata(client);
  686. const struct firmware *fw_entry;
  687. char *fw_name;
  688. int mode;
  689. int error;
  690. error = kstrtoint(buf, 0, &mode);
  691. if (error)
  692. return error;
  693. fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin",
  694. be16_to_cpu(ts->dwz_info.product_id));
  695. if (!fw_name)
  696. return -ENOMEM;
  697. error = request_firmware(&fw_entry, fw_name, dev);
  698. if (error) {
  699. dev_err(dev, "failed to request firmware %s: %d",
  700. fw_name, error);
  701. goto out_free_fw_name;
  702. }
  703. if (fw_entry->size % sizeof(__be32)) {
  704. dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
  705. error = -EINVAL;
  706. goto out_release_fw;
  707. }
  708. if (fw_entry->size > ts->fw_size) {
  709. dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
  710. fw_entry->size, ts->fw_size);
  711. error = -EFBIG;
  712. goto out_release_fw;
  713. }
  714. mutex_lock(&ts->dev_mutex);
  715. disable_irq(client->irq);
  716. error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
  717. fw_entry->size);
  718. enable_irq(client->irq);
  719. mutex_unlock(&ts->dev_mutex);
  720. out_release_fw:
  721. release_firmware(fw_entry);
  722. out_free_fw_name:
  723. kfree(fw_name);
  724. return error ?: count;
  725. }
  726. static ssize_t hideep_fw_version_show(struct device *dev,
  727. struct device_attribute *attr, char *buf)
  728. {
  729. struct i2c_client *client = to_i2c_client(dev);
  730. struct hideep_ts *ts = i2c_get_clientdata(client);
  731. ssize_t len;
  732. mutex_lock(&ts->dev_mutex);
  733. len = scnprintf(buf, PAGE_SIZE, "%04x\n",
  734. be16_to_cpu(ts->dwz_info.release_ver));
  735. mutex_unlock(&ts->dev_mutex);
  736. return len;
  737. }
  738. static ssize_t hideep_product_id_show(struct device *dev,
  739. struct device_attribute *attr, char *buf)
  740. {
  741. struct i2c_client *client = to_i2c_client(dev);
  742. struct hideep_ts *ts = i2c_get_clientdata(client);
  743. ssize_t len;
  744. mutex_lock(&ts->dev_mutex);
  745. len = scnprintf(buf, PAGE_SIZE, "%04x\n",
  746. be16_to_cpu(ts->dwz_info.product_id));
  747. mutex_unlock(&ts->dev_mutex);
  748. return len;
  749. }
  750. static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
  751. static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
  752. static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
  753. static struct attribute *hideep_ts_sysfs_entries[] = {
  754. &dev_attr_version.attr,
  755. &dev_attr_product_id.attr,
  756. &dev_attr_update_fw.attr,
  757. NULL,
  758. };
  759. static const struct attribute_group hideep_ts_attr_group = {
  760. .attrs = hideep_ts_sysfs_entries,
  761. };
  762. static int __maybe_unused hideep_suspend(struct device *dev)
  763. {
  764. struct i2c_client *client = to_i2c_client(dev);
  765. struct hideep_ts *ts = i2c_get_clientdata(client);
  766. disable_irq(client->irq);
  767. hideep_power_off(ts);
  768. return 0;
  769. }
  770. static int __maybe_unused hideep_resume(struct device *dev)
  771. {
  772. struct i2c_client *client = to_i2c_client(dev);
  773. struct hideep_ts *ts = i2c_get_clientdata(client);
  774. int error;
  775. error = hideep_power_on(ts);
  776. if (error) {
  777. dev_err(&client->dev, "power on failed");
  778. return error;
  779. }
  780. enable_irq(client->irq);
  781. return 0;
  782. }
  783. static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
  784. static const struct regmap_config hideep_regmap_config = {
  785. .reg_bits = 16,
  786. .reg_format_endian = REGMAP_ENDIAN_LITTLE,
  787. .val_bits = 16,
  788. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  789. .max_register = 0xffff,
  790. };
  791. static int hideep_probe(struct i2c_client *client,
  792. const struct i2c_device_id *id)
  793. {
  794. struct hideep_ts *ts;
  795. int error;
  796. /* check i2c bus */
  797. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  798. dev_err(&client->dev, "check i2c device error");
  799. return -ENODEV;
  800. }
  801. if (client->irq <= 0) {
  802. dev_err(&client->dev, "missing irq: %d\n", client->irq);
  803. return -EINVAL;
  804. }
  805. ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
  806. if (!ts)
  807. return -ENOMEM;
  808. ts->client = client;
  809. i2c_set_clientdata(client, ts);
  810. mutex_init(&ts->dev_mutex);
  811. ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
  812. if (IS_ERR(ts->reg)) {
  813. error = PTR_ERR(ts->reg);
  814. dev_err(&client->dev,
  815. "failed to initialize regmap: %d\n", error);
  816. return error;
  817. }
  818. ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
  819. if (IS_ERR(ts->vcc_vdd))
  820. return PTR_ERR(ts->vcc_vdd);
  821. ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
  822. if (IS_ERR(ts->vcc_vid))
  823. return PTR_ERR(ts->vcc_vid);
  824. ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
  825. "reset", GPIOD_OUT_HIGH);
  826. if (IS_ERR(ts->reset_gpio))
  827. return PTR_ERR(ts->reset_gpio);
  828. error = hideep_power_on(ts);
  829. if (error) {
  830. dev_err(&client->dev, "power on failed: %d\n", error);
  831. return error;
  832. }
  833. error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
  834. if (error)
  835. return error;
  836. error = hideep_load_dwz(ts);
  837. if (error) {
  838. dev_err(&client->dev, "failed to load dwz: %d", error);
  839. return error;
  840. }
  841. error = hideep_init_input(ts);
  842. if (error)
  843. return error;
  844. error = devm_request_threaded_irq(&client->dev, client->irq,
  845. NULL, hideep_irq, IRQF_ONESHOT,
  846. client->name, ts);
  847. if (error) {
  848. dev_err(&client->dev, "failed to request irq %d: %d\n",
  849. client->irq, error);
  850. return error;
  851. }
  852. error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
  853. if (error) {
  854. dev_err(&client->dev,
  855. "failed to add sysfs attributes: %d\n", error);
  856. return error;
  857. }
  858. return 0;
  859. }
  860. static const struct i2c_device_id hideep_i2c_id[] = {
  861. { HIDEEP_I2C_NAME, 0 },
  862. { }
  863. };
  864. MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
  865. #ifdef CONFIG_ACPI
  866. static const struct acpi_device_id hideep_acpi_id[] = {
  867. { "HIDP0001", 0 },
  868. { }
  869. };
  870. MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
  871. #endif
  872. #ifdef CONFIG_OF
  873. static const struct of_device_id hideep_match_table[] = {
  874. { .compatible = "hideep,hideep-ts" },
  875. { }
  876. };
  877. MODULE_DEVICE_TABLE(of, hideep_match_table);
  878. #endif
  879. static struct i2c_driver hideep_driver = {
  880. .driver = {
  881. .name = HIDEEP_I2C_NAME,
  882. .of_match_table = of_match_ptr(hideep_match_table),
  883. .acpi_match_table = ACPI_PTR(hideep_acpi_id),
  884. .pm = &hideep_pm_ops,
  885. },
  886. .id_table = hideep_i2c_id,
  887. .probe = hideep_probe,
  888. };
  889. module_i2c_driver(hideep_driver);
  890. MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
  891. MODULE_AUTHOR("anthony.kim@hideep.com");
  892. MODULE_LICENSE("GPL v2");