hns_roce_qp.c 30 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/platform_device.h>
  34. #include <rdma/ib_addr.h>
  35. #include <rdma/ib_umem.h>
  36. #include "hns_roce_common.h"
  37. #include "hns_roce_device.h"
  38. #include "hns_roce_hem.h"
  39. #include <rdma/hns-abi.h>
  40. #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS)
  41. void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
  42. {
  43. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  44. struct device *dev = hr_dev->dev;
  45. struct hns_roce_qp *qp;
  46. spin_lock(&qp_table->lock);
  47. qp = __hns_roce_qp_lookup(hr_dev, qpn);
  48. if (qp)
  49. atomic_inc(&qp->refcount);
  50. spin_unlock(&qp_table->lock);
  51. if (!qp) {
  52. dev_warn(dev, "Async event for bogus QP %08x\n", qpn);
  53. return;
  54. }
  55. qp->event(qp, (enum hns_roce_event)event_type);
  56. if (atomic_dec_and_test(&qp->refcount))
  57. complete(&qp->free);
  58. }
  59. EXPORT_SYMBOL_GPL(hns_roce_qp_event);
  60. static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
  61. enum hns_roce_event type)
  62. {
  63. struct ib_event event;
  64. struct ib_qp *ibqp = &hr_qp->ibqp;
  65. if (ibqp->event_handler) {
  66. event.device = ibqp->device;
  67. event.element.qp = ibqp;
  68. switch (type) {
  69. case HNS_ROCE_EVENT_TYPE_PATH_MIG:
  70. event.event = IB_EVENT_PATH_MIG;
  71. break;
  72. case HNS_ROCE_EVENT_TYPE_COMM_EST:
  73. event.event = IB_EVENT_COMM_EST;
  74. break;
  75. case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
  76. event.event = IB_EVENT_SQ_DRAINED;
  77. break;
  78. case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
  79. event.event = IB_EVENT_QP_LAST_WQE_REACHED;
  80. break;
  81. case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
  82. event.event = IB_EVENT_QP_FATAL;
  83. break;
  84. case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
  85. event.event = IB_EVENT_PATH_MIG_ERR;
  86. break;
  87. case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
  88. event.event = IB_EVENT_QP_REQ_ERR;
  89. break;
  90. case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
  91. event.event = IB_EVENT_QP_ACCESS_ERR;
  92. break;
  93. default:
  94. dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
  95. type, hr_qp->qpn);
  96. return;
  97. }
  98. ibqp->event_handler(&event, ibqp->qp_context);
  99. }
  100. }
  101. static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt,
  102. int align, unsigned long *base)
  103. {
  104. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  105. return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align,
  106. base) ?
  107. -ENOMEM :
  108. 0;
  109. }
  110. enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
  111. {
  112. switch (state) {
  113. case IB_QPS_RESET:
  114. return HNS_ROCE_QP_STATE_RST;
  115. case IB_QPS_INIT:
  116. return HNS_ROCE_QP_STATE_INIT;
  117. case IB_QPS_RTR:
  118. return HNS_ROCE_QP_STATE_RTR;
  119. case IB_QPS_RTS:
  120. return HNS_ROCE_QP_STATE_RTS;
  121. case IB_QPS_SQD:
  122. return HNS_ROCE_QP_STATE_SQD;
  123. case IB_QPS_ERR:
  124. return HNS_ROCE_QP_STATE_ERR;
  125. default:
  126. return HNS_ROCE_QP_NUM_STATE;
  127. }
  128. }
  129. EXPORT_SYMBOL_GPL(to_hns_roce_state);
  130. static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
  131. struct hns_roce_qp *hr_qp)
  132. {
  133. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  134. int ret;
  135. if (!qpn)
  136. return -EINVAL;
  137. hr_qp->qpn = qpn;
  138. spin_lock_irq(&qp_table->lock);
  139. ret = radix_tree_insert(&hr_dev->qp_table_tree,
  140. hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
  141. spin_unlock_irq(&qp_table->lock);
  142. if (ret) {
  143. dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n");
  144. goto err_put_irrl;
  145. }
  146. atomic_set(&hr_qp->refcount, 1);
  147. init_completion(&hr_qp->free);
  148. return 0;
  149. err_put_irrl:
  150. return ret;
  151. }
  152. static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
  153. struct hns_roce_qp *hr_qp)
  154. {
  155. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  156. struct device *dev = hr_dev->dev;
  157. int ret;
  158. if (!qpn)
  159. return -EINVAL;
  160. hr_qp->qpn = qpn;
  161. /* Alloc memory for QPC */
  162. ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  163. if (ret) {
  164. dev_err(dev, "QPC table get failed\n");
  165. goto err_out;
  166. }
  167. /* Alloc memory for IRRL */
  168. ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  169. if (ret) {
  170. dev_err(dev, "IRRL table get failed\n");
  171. goto err_put_qp;
  172. }
  173. if (hr_dev->caps.trrl_entry_sz) {
  174. /* Alloc memory for TRRL */
  175. ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
  176. hr_qp->qpn);
  177. if (ret) {
  178. dev_err(dev, "TRRL table get failed\n");
  179. goto err_put_irrl;
  180. }
  181. }
  182. spin_lock_irq(&qp_table->lock);
  183. ret = radix_tree_insert(&hr_dev->qp_table_tree,
  184. hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
  185. spin_unlock_irq(&qp_table->lock);
  186. if (ret) {
  187. dev_err(dev, "QPC radix_tree_insert failed\n");
  188. goto err_put_trrl;
  189. }
  190. atomic_set(&hr_qp->refcount, 1);
  191. init_completion(&hr_qp->free);
  192. return 0;
  193. err_put_trrl:
  194. if (hr_dev->caps.trrl_entry_sz)
  195. hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
  196. err_put_irrl:
  197. hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  198. err_put_qp:
  199. hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  200. err_out:
  201. return ret;
  202. }
  203. void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  204. {
  205. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  206. unsigned long flags;
  207. spin_lock_irqsave(&qp_table->lock, flags);
  208. radix_tree_delete(&hr_dev->qp_table_tree,
  209. hr_qp->qpn & (hr_dev->caps.num_qps - 1));
  210. spin_unlock_irqrestore(&qp_table->lock, flags);
  211. }
  212. EXPORT_SYMBOL_GPL(hns_roce_qp_remove);
  213. void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
  214. {
  215. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  216. if (atomic_dec_and_test(&hr_qp->refcount))
  217. complete(&hr_qp->free);
  218. wait_for_completion(&hr_qp->free);
  219. if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) {
  220. if (hr_dev->caps.trrl_entry_sz)
  221. hns_roce_table_put(hr_dev, &qp_table->trrl_table,
  222. hr_qp->qpn);
  223. hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
  224. hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
  225. }
  226. }
  227. EXPORT_SYMBOL_GPL(hns_roce_qp_free);
  228. void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
  229. int cnt)
  230. {
  231. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  232. if (base_qpn < SQP_NUM)
  233. return;
  234. hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR);
  235. }
  236. EXPORT_SYMBOL_GPL(hns_roce_release_range_qp);
  237. static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
  238. struct ib_qp_cap *cap, int is_user, int has_srq,
  239. struct hns_roce_qp *hr_qp)
  240. {
  241. struct device *dev = hr_dev->dev;
  242. u32 max_cnt;
  243. /* Check the validity of QP support capacity */
  244. if (cap->max_recv_wr > hr_dev->caps.max_wqes ||
  245. cap->max_recv_sge > hr_dev->caps.max_rq_sg) {
  246. dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n",
  247. cap->max_recv_wr, cap->max_recv_sge);
  248. return -EINVAL;
  249. }
  250. /* If srq exit, set zero for relative number of rq */
  251. if (has_srq) {
  252. if (cap->max_recv_wr) {
  253. dev_dbg(dev, "srq no need config max_recv_wr\n");
  254. return -EINVAL;
  255. }
  256. hr_qp->rq.wqe_cnt = hr_qp->rq.max_gs = 0;
  257. } else {
  258. if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) {
  259. dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n");
  260. return -EINVAL;
  261. }
  262. if (hr_dev->caps.min_wqes)
  263. max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes);
  264. else
  265. max_cnt = cap->max_recv_wr;
  266. hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
  267. if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
  268. dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n");
  269. return -EINVAL;
  270. }
  271. max_cnt = max(1U, cap->max_recv_sge);
  272. hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
  273. if (hr_dev->caps.max_rq_sg <= 2)
  274. hr_qp->rq.wqe_shift =
  275. ilog2(hr_dev->caps.max_rq_desc_sz);
  276. else
  277. hr_qp->rq.wqe_shift =
  278. ilog2(hr_dev->caps.max_rq_desc_sz
  279. * hr_qp->rq.max_gs);
  280. }
  281. cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt;
  282. cap->max_recv_sge = hr_qp->rq.max_gs;
  283. return 0;
  284. }
  285. static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
  286. struct ib_qp_cap *cap,
  287. struct hns_roce_qp *hr_qp,
  288. struct hns_roce_ib_create_qp *ucmd)
  289. {
  290. u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
  291. u8 max_sq_stride = ilog2(roundup_sq_stride);
  292. u32 page_size;
  293. u32 max_cnt;
  294. /* Sanity check SQ size before proceeding */
  295. if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
  296. ucmd->log_sq_stride > max_sq_stride ||
  297. ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
  298. dev_err(hr_dev->dev, "check SQ size error!\n");
  299. return -EINVAL;
  300. }
  301. if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
  302. dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n",
  303. cap->max_send_sge);
  304. return -EINVAL;
  305. }
  306. hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
  307. hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
  308. max_cnt = max(1U, cap->max_send_sge);
  309. if (hr_dev->caps.max_sq_sg <= 2)
  310. hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
  311. else
  312. hr_qp->sq.max_gs = max_cnt;
  313. if (hr_qp->sq.max_gs > 2)
  314. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  315. (hr_qp->sq.max_gs - 2));
  316. hr_qp->sge.sge_shift = 4;
  317. /* Get buf size, SQ and RQ are aligned to page_szie */
  318. if (hr_dev->caps.max_sq_sg <= 2) {
  319. hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
  320. hr_qp->rq.wqe_shift), PAGE_SIZE) +
  321. HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  322. hr_qp->sq.wqe_shift), PAGE_SIZE);
  323. hr_qp->sq.offset = 0;
  324. hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  325. hr_qp->sq.wqe_shift), PAGE_SIZE);
  326. } else {
  327. page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
  328. hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
  329. hr_qp->rq.wqe_shift), page_size) +
  330. HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
  331. hr_qp->sge.sge_shift), page_size) +
  332. HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
  333. hr_qp->sq.wqe_shift), page_size);
  334. hr_qp->sq.offset = 0;
  335. if (hr_qp->sge.sge_cnt) {
  336. hr_qp->sge.offset = HNS_ROCE_ALOGN_UP(
  337. (hr_qp->sq.wqe_cnt <<
  338. hr_qp->sq.wqe_shift),
  339. page_size);
  340. hr_qp->rq.offset = hr_qp->sge.offset +
  341. HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
  342. hr_qp->sge.sge_shift),
  343. page_size);
  344. } else {
  345. hr_qp->rq.offset = HNS_ROCE_ALOGN_UP(
  346. (hr_qp->sq.wqe_cnt <<
  347. hr_qp->sq.wqe_shift),
  348. page_size);
  349. }
  350. }
  351. return 0;
  352. }
  353. static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
  354. struct ib_qp_cap *cap,
  355. struct hns_roce_qp *hr_qp)
  356. {
  357. struct device *dev = hr_dev->dev;
  358. u32 page_size;
  359. u32 max_cnt;
  360. int size;
  361. if (cap->max_send_wr > hr_dev->caps.max_wqes ||
  362. cap->max_send_sge > hr_dev->caps.max_sq_sg ||
  363. cap->max_inline_data > hr_dev->caps.max_sq_inline) {
  364. dev_err(dev, "SQ WR or sge or inline data error!\n");
  365. return -EINVAL;
  366. }
  367. hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
  368. hr_qp->sq_max_wqes_per_wr = 1;
  369. hr_qp->sq_spare_wqes = 0;
  370. if (hr_dev->caps.min_wqes)
  371. max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes);
  372. else
  373. max_cnt = cap->max_send_wr;
  374. hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt);
  375. if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) {
  376. dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n");
  377. return -EINVAL;
  378. }
  379. /* Get data_seg numbers */
  380. max_cnt = max(1U, cap->max_send_sge);
  381. if (hr_dev->caps.max_sq_sg <= 2)
  382. hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
  383. else
  384. hr_qp->sq.max_gs = max_cnt;
  385. if (hr_qp->sq.max_gs > 2) {
  386. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  387. (hr_qp->sq.max_gs - 2));
  388. hr_qp->sge.sge_shift = 4;
  389. }
  390. /* ud sqwqe's sge use extend sge */
  391. if (hr_dev->caps.max_sq_sg > 2 && hr_qp->ibqp.qp_type == IB_QPT_GSI) {
  392. hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
  393. hr_qp->sq.max_gs);
  394. hr_qp->sge.sge_shift = 4;
  395. }
  396. /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */
  397. page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
  398. hr_qp->sq.offset = 0;
  399. size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift,
  400. page_size);
  401. if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) {
  402. hr_qp->sge.offset = size;
  403. size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt <<
  404. hr_qp->sge.sge_shift, page_size);
  405. }
  406. hr_qp->rq.offset = size;
  407. size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift),
  408. page_size);
  409. hr_qp->buff_size = size;
  410. /* Get wr and sge number which send */
  411. cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt;
  412. cap->max_send_sge = hr_qp->sq.max_gs;
  413. /* We don't support inline sends for kernel QPs (yet) */
  414. cap->max_inline_data = 0;
  415. return 0;
  416. }
  417. static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr)
  418. {
  419. if (attr->qp_type == IB_QPT_XRC_TGT)
  420. return 0;
  421. return 1;
  422. }
  423. static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
  424. {
  425. if (attr->qp_type == IB_QPT_XRC_INI ||
  426. attr->qp_type == IB_QPT_XRC_TGT || attr->srq)
  427. return 0;
  428. return 1;
  429. }
  430. static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
  431. struct ib_pd *ib_pd,
  432. struct ib_qp_init_attr *init_attr,
  433. struct ib_udata *udata, unsigned long sqpn,
  434. struct hns_roce_qp *hr_qp)
  435. {
  436. struct device *dev = hr_dev->dev;
  437. struct hns_roce_ib_create_qp ucmd;
  438. struct hns_roce_ib_create_qp_resp resp = {};
  439. unsigned long qpn = 0;
  440. int ret = 0;
  441. u32 page_shift;
  442. u32 npages;
  443. int i;
  444. mutex_init(&hr_qp->mutex);
  445. spin_lock_init(&hr_qp->sq.lock);
  446. spin_lock_init(&hr_qp->rq.lock);
  447. hr_qp->state = IB_QPS_RESET;
  448. hr_qp->ibqp.qp_type = init_attr->qp_type;
  449. if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
  450. hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_ALL_WR);
  451. else
  452. hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_REQ_WR);
  453. ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, !!ib_pd->uobject,
  454. !!init_attr->srq, hr_qp);
  455. if (ret) {
  456. dev_err(dev, "hns_roce_set_rq_size failed\n");
  457. goto err_out;
  458. }
  459. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
  460. /* allocate recv inline buf */
  461. hr_qp->rq_inl_buf.wqe_list = kcalloc(hr_qp->rq.wqe_cnt,
  462. sizeof(struct hns_roce_rinl_wqe),
  463. GFP_KERNEL);
  464. if (!hr_qp->rq_inl_buf.wqe_list) {
  465. ret = -ENOMEM;
  466. goto err_out;
  467. }
  468. hr_qp->rq_inl_buf.wqe_cnt = hr_qp->rq.wqe_cnt;
  469. /* Firstly, allocate a list of sge space buffer */
  470. hr_qp->rq_inl_buf.wqe_list[0].sg_list =
  471. kcalloc(hr_qp->rq_inl_buf.wqe_cnt,
  472. init_attr->cap.max_recv_sge *
  473. sizeof(struct hns_roce_rinl_sge),
  474. GFP_KERNEL);
  475. if (!hr_qp->rq_inl_buf.wqe_list[0].sg_list) {
  476. ret = -ENOMEM;
  477. goto err_wqe_list;
  478. }
  479. for (i = 1; i < hr_qp->rq_inl_buf.wqe_cnt; i++)
  480. /* Secondly, reallocate the buffer */
  481. hr_qp->rq_inl_buf.wqe_list[i].sg_list =
  482. &hr_qp->rq_inl_buf.wqe_list[0].sg_list[i *
  483. init_attr->cap.max_recv_sge];
  484. }
  485. if (ib_pd->uobject) {
  486. if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
  487. dev_err(dev, "ib_copy_from_udata error for create qp\n");
  488. ret = -EFAULT;
  489. goto err_rq_sge_list;
  490. }
  491. ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp,
  492. &ucmd);
  493. if (ret) {
  494. dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n");
  495. goto err_rq_sge_list;
  496. }
  497. hr_qp->umem = ib_umem_get(ib_pd->uobject->context,
  498. ucmd.buf_addr, hr_qp->buff_size, 0,
  499. 0);
  500. if (IS_ERR(hr_qp->umem)) {
  501. dev_err(dev, "ib_umem_get error for create qp\n");
  502. ret = PTR_ERR(hr_qp->umem);
  503. goto err_rq_sge_list;
  504. }
  505. hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
  506. if (hr_dev->caps.mtt_buf_pg_sz) {
  507. npages = (ib_umem_page_count(hr_qp->umem) +
  508. (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) /
  509. (1 << hr_dev->caps.mtt_buf_pg_sz);
  510. page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
  511. ret = hns_roce_mtt_init(hr_dev, npages,
  512. page_shift,
  513. &hr_qp->mtt);
  514. } else {
  515. ret = hns_roce_mtt_init(hr_dev,
  516. ib_umem_page_count(hr_qp->umem),
  517. hr_qp->umem->page_shift,
  518. &hr_qp->mtt);
  519. }
  520. if (ret) {
  521. dev_err(dev, "hns_roce_mtt_init error for create qp\n");
  522. goto err_buf;
  523. }
  524. ret = hns_roce_ib_umem_write_mtt(hr_dev, &hr_qp->mtt,
  525. hr_qp->umem);
  526. if (ret) {
  527. dev_err(dev, "hns_roce_ib_umem_write_mtt error for create qp\n");
  528. goto err_mtt;
  529. }
  530. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
  531. (udata->inlen >= sizeof(ucmd)) &&
  532. (udata->outlen >= sizeof(resp)) &&
  533. hns_roce_qp_has_sq(init_attr)) {
  534. ret = hns_roce_db_map_user(
  535. to_hr_ucontext(ib_pd->uobject->context),
  536. ucmd.sdb_addr, &hr_qp->sdb);
  537. if (ret) {
  538. dev_err(dev, "sq record doorbell map failed!\n");
  539. goto err_mtt;
  540. }
  541. /* indicate kernel supports sq record db */
  542. resp.cap_flags |= HNS_ROCE_SUPPORT_SQ_RECORD_DB;
  543. hr_qp->sdb_en = 1;
  544. }
  545. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  546. (udata->outlen >= sizeof(resp)) &&
  547. hns_roce_qp_has_rq(init_attr)) {
  548. ret = hns_roce_db_map_user(
  549. to_hr_ucontext(ib_pd->uobject->context),
  550. ucmd.db_addr, &hr_qp->rdb);
  551. if (ret) {
  552. dev_err(dev, "rq record doorbell map failed!\n");
  553. goto err_sq_dbmap;
  554. }
  555. }
  556. } else {
  557. if (init_attr->create_flags &
  558. IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
  559. dev_err(dev, "init_attr->create_flags error!\n");
  560. ret = -EINVAL;
  561. goto err_rq_sge_list;
  562. }
  563. if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) {
  564. dev_err(dev, "init_attr->create_flags error!\n");
  565. ret = -EINVAL;
  566. goto err_rq_sge_list;
  567. }
  568. /* Set SQ size */
  569. ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap,
  570. hr_qp);
  571. if (ret) {
  572. dev_err(dev, "hns_roce_set_kernel_sq_size error!\n");
  573. goto err_rq_sge_list;
  574. }
  575. /* QP doorbell register address */
  576. hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset +
  577. DB_REG_OFFSET * hr_dev->priv_uar.index;
  578. hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset +
  579. DB_REG_OFFSET * hr_dev->priv_uar.index;
  580. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  581. hns_roce_qp_has_rq(init_attr)) {
  582. ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
  583. if (ret) {
  584. dev_err(dev, "rq record doorbell alloc failed!\n");
  585. goto err_rq_sge_list;
  586. }
  587. *hr_qp->rdb.db_record = 0;
  588. hr_qp->rdb_en = 1;
  589. }
  590. /* Allocate QP buf */
  591. page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
  592. if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size,
  593. (1 << page_shift) * 2,
  594. &hr_qp->hr_buf, page_shift)) {
  595. dev_err(dev, "hns_roce_buf_alloc error!\n");
  596. ret = -ENOMEM;
  597. goto err_db;
  598. }
  599. hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
  600. /* Write MTT */
  601. ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages,
  602. hr_qp->hr_buf.page_shift, &hr_qp->mtt);
  603. if (ret) {
  604. dev_err(dev, "hns_roce_mtt_init error for kernel create qp\n");
  605. goto err_buf;
  606. }
  607. ret = hns_roce_buf_write_mtt(hr_dev, &hr_qp->mtt,
  608. &hr_qp->hr_buf);
  609. if (ret) {
  610. dev_err(dev, "hns_roce_buf_write_mtt error for kernel create qp\n");
  611. goto err_mtt;
  612. }
  613. hr_qp->sq.wrid = kmalloc_array(hr_qp->sq.wqe_cnt, sizeof(u64),
  614. GFP_KERNEL);
  615. hr_qp->rq.wrid = kmalloc_array(hr_qp->rq.wqe_cnt, sizeof(u64),
  616. GFP_KERNEL);
  617. if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) {
  618. ret = -ENOMEM;
  619. goto err_wrid;
  620. }
  621. }
  622. if (sqpn) {
  623. qpn = sqpn;
  624. } else {
  625. /* Get QPN */
  626. ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn);
  627. if (ret) {
  628. dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n");
  629. goto err_wrid;
  630. }
  631. }
  632. if (init_attr->qp_type == IB_QPT_GSI &&
  633. hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
  634. /* In v1 engine, GSI QP context in RoCE engine's register */
  635. ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp);
  636. if (ret) {
  637. dev_err(dev, "hns_roce_qp_alloc failed!\n");
  638. goto err_qpn;
  639. }
  640. } else {
  641. ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp);
  642. if (ret) {
  643. dev_err(dev, "hns_roce_qp_alloc failed!\n");
  644. goto err_qpn;
  645. }
  646. }
  647. if (sqpn)
  648. hr_qp->doorbell_qpn = 1;
  649. else
  650. hr_qp->doorbell_qpn = cpu_to_le64(hr_qp->qpn);
  651. if (ib_pd->uobject && (udata->outlen >= sizeof(resp)) &&
  652. (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) {
  653. /* indicate kernel supports rq record db */
  654. resp.cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB;
  655. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  656. if (ret)
  657. goto err_qp;
  658. hr_qp->rdb_en = 1;
  659. }
  660. hr_qp->event = hns_roce_ib_qp_event;
  661. return 0;
  662. err_qp:
  663. if (init_attr->qp_type == IB_QPT_GSI &&
  664. hr_dev->hw_rev == HNS_ROCE_HW_VER1)
  665. hns_roce_qp_remove(hr_dev, hr_qp);
  666. else
  667. hns_roce_qp_free(hr_dev, hr_qp);
  668. err_qpn:
  669. if (!sqpn)
  670. hns_roce_release_range_qp(hr_dev, qpn, 1);
  671. err_wrid:
  672. if (ib_pd->uobject) {
  673. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
  674. (udata->outlen >= sizeof(resp)) &&
  675. hns_roce_qp_has_rq(init_attr))
  676. hns_roce_db_unmap_user(
  677. to_hr_ucontext(ib_pd->uobject->context),
  678. &hr_qp->rdb);
  679. } else {
  680. kfree(hr_qp->sq.wrid);
  681. kfree(hr_qp->rq.wrid);
  682. }
  683. err_sq_dbmap:
  684. if (ib_pd->uobject)
  685. if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
  686. (udata->inlen >= sizeof(ucmd)) &&
  687. (udata->outlen >= sizeof(resp)) &&
  688. hns_roce_qp_has_sq(init_attr))
  689. hns_roce_db_unmap_user(
  690. to_hr_ucontext(ib_pd->uobject->context),
  691. &hr_qp->sdb);
  692. err_mtt:
  693. hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
  694. err_buf:
  695. if (ib_pd->uobject)
  696. ib_umem_release(hr_qp->umem);
  697. else
  698. hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
  699. err_db:
  700. if (!ib_pd->uobject && hns_roce_qp_has_rq(init_attr) &&
  701. (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB))
  702. hns_roce_free_db(hr_dev, &hr_qp->rdb);
  703. err_rq_sge_list:
  704. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
  705. kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
  706. err_wqe_list:
  707. if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
  708. kfree(hr_qp->rq_inl_buf.wqe_list);
  709. err_out:
  710. return ret;
  711. }
  712. struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
  713. struct ib_qp_init_attr *init_attr,
  714. struct ib_udata *udata)
  715. {
  716. struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
  717. struct device *dev = hr_dev->dev;
  718. struct hns_roce_sqp *hr_sqp;
  719. struct hns_roce_qp *hr_qp;
  720. int ret;
  721. switch (init_attr->qp_type) {
  722. case IB_QPT_RC: {
  723. hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
  724. if (!hr_qp)
  725. return ERR_PTR(-ENOMEM);
  726. ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0,
  727. hr_qp);
  728. if (ret) {
  729. dev_err(dev, "Create RC QP failed\n");
  730. kfree(hr_qp);
  731. return ERR_PTR(ret);
  732. }
  733. hr_qp->ibqp.qp_num = hr_qp->qpn;
  734. break;
  735. }
  736. case IB_QPT_GSI: {
  737. /* Userspace is not allowed to create special QPs: */
  738. if (pd->uobject) {
  739. dev_err(dev, "not support usr space GSI\n");
  740. return ERR_PTR(-EINVAL);
  741. }
  742. hr_sqp = kzalloc(sizeof(*hr_sqp), GFP_KERNEL);
  743. if (!hr_sqp)
  744. return ERR_PTR(-ENOMEM);
  745. hr_qp = &hr_sqp->hr_qp;
  746. hr_qp->port = init_attr->port_num - 1;
  747. hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
  748. /* when hw version is v1, the sqpn is allocated */
  749. if (hr_dev->caps.max_sq_sg <= 2)
  750. hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS +
  751. hr_dev->iboe.phy_port[hr_qp->port];
  752. else
  753. hr_qp->ibqp.qp_num = 1;
  754. ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
  755. hr_qp->ibqp.qp_num, hr_qp);
  756. if (ret) {
  757. dev_err(dev, "Create GSI QP failed!\n");
  758. kfree(hr_sqp);
  759. return ERR_PTR(ret);
  760. }
  761. break;
  762. }
  763. default:{
  764. dev_err(dev, "not support QP type %d\n", init_attr->qp_type);
  765. return ERR_PTR(-EINVAL);
  766. }
  767. }
  768. return &hr_qp->ibqp;
  769. }
  770. EXPORT_SYMBOL_GPL(hns_roce_create_qp);
  771. int to_hr_qp_type(int qp_type)
  772. {
  773. int transport_type;
  774. if (qp_type == IB_QPT_RC)
  775. transport_type = SERV_TYPE_RC;
  776. else if (qp_type == IB_QPT_UC)
  777. transport_type = SERV_TYPE_UC;
  778. else if (qp_type == IB_QPT_UD)
  779. transport_type = SERV_TYPE_UD;
  780. else if (qp_type == IB_QPT_GSI)
  781. transport_type = SERV_TYPE_UD;
  782. else
  783. transport_type = -1;
  784. return transport_type;
  785. }
  786. EXPORT_SYMBOL_GPL(to_hr_qp_type);
  787. int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  788. int attr_mask, struct ib_udata *udata)
  789. {
  790. struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
  791. struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
  792. enum ib_qp_state cur_state, new_state;
  793. struct device *dev = hr_dev->dev;
  794. int ret = -EINVAL;
  795. int p;
  796. enum ib_mtu active_mtu;
  797. mutex_lock(&hr_qp->mutex);
  798. cur_state = attr_mask & IB_QP_CUR_STATE ?
  799. attr->cur_qp_state : (enum ib_qp_state)hr_qp->state;
  800. new_state = attr_mask & IB_QP_STATE ?
  801. attr->qp_state : cur_state;
  802. if (ibqp->uobject &&
  803. (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
  804. if (hr_qp->sdb_en == 1) {
  805. hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
  806. hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
  807. } else {
  808. dev_warn(dev, "flush cqe is not supported in userspace!\n");
  809. goto out;
  810. }
  811. }
  812. if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
  813. IB_LINK_LAYER_ETHERNET)) {
  814. dev_err(dev, "ib_modify_qp_is_ok failed\n");
  815. goto out;
  816. }
  817. if ((attr_mask & IB_QP_PORT) &&
  818. (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
  819. dev_err(dev, "attr port_num invalid.attr->port_num=%d\n",
  820. attr->port_num);
  821. goto out;
  822. }
  823. if (attr_mask & IB_QP_PKEY_INDEX) {
  824. p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
  825. if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
  826. dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n",
  827. attr->pkey_index);
  828. goto out;
  829. }
  830. }
  831. if (attr_mask & IB_QP_PATH_MTU) {
  832. p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
  833. active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
  834. if ((hr_dev->caps.max_mtu == IB_MTU_4096 &&
  835. attr->path_mtu > IB_MTU_4096) ||
  836. (hr_dev->caps.max_mtu == IB_MTU_2048 &&
  837. attr->path_mtu > IB_MTU_2048) ||
  838. attr->path_mtu < IB_MTU_256 ||
  839. attr->path_mtu > active_mtu) {
  840. dev_err(dev, "attr path_mtu(%d)invalid while modify qp",
  841. attr->path_mtu);
  842. goto out;
  843. }
  844. }
  845. if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
  846. attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
  847. dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n",
  848. attr->max_rd_atomic);
  849. goto out;
  850. }
  851. if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
  852. attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
  853. dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n",
  854. attr->max_dest_rd_atomic);
  855. goto out;
  856. }
  857. if (cur_state == new_state && cur_state == IB_QPS_RESET) {
  858. if (hr_dev->caps.min_wqes) {
  859. ret = -EPERM;
  860. dev_err(dev, "cur_state=%d new_state=%d\n", cur_state,
  861. new_state);
  862. } else {
  863. ret = 0;
  864. }
  865. goto out;
  866. }
  867. ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
  868. new_state);
  869. out:
  870. mutex_unlock(&hr_qp->mutex);
  871. return ret;
  872. }
  873. void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
  874. __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
  875. {
  876. if (send_cq == recv_cq) {
  877. spin_lock_irq(&send_cq->lock);
  878. __acquire(&recv_cq->lock);
  879. } else if (send_cq->cqn < recv_cq->cqn) {
  880. spin_lock_irq(&send_cq->lock);
  881. spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
  882. } else {
  883. spin_lock_irq(&recv_cq->lock);
  884. spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
  885. }
  886. }
  887. EXPORT_SYMBOL_GPL(hns_roce_lock_cqs);
  888. void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
  889. struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
  890. __releases(&recv_cq->lock)
  891. {
  892. if (send_cq == recv_cq) {
  893. __release(&recv_cq->lock);
  894. spin_unlock_irq(&send_cq->lock);
  895. } else if (send_cq->cqn < recv_cq->cqn) {
  896. spin_unlock(&recv_cq->lock);
  897. spin_unlock_irq(&send_cq->lock);
  898. } else {
  899. spin_unlock(&send_cq->lock);
  900. spin_unlock_irq(&recv_cq->lock);
  901. }
  902. }
  903. EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs);
  904. static void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
  905. {
  906. return hns_roce_buf_offset(&hr_qp->hr_buf, offset);
  907. }
  908. void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
  909. {
  910. return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
  911. }
  912. EXPORT_SYMBOL_GPL(get_recv_wqe);
  913. void *get_send_wqe(struct hns_roce_qp *hr_qp, int n)
  914. {
  915. return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
  916. }
  917. EXPORT_SYMBOL_GPL(get_send_wqe);
  918. void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n)
  919. {
  920. return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset +
  921. (n << hr_qp->sge.sge_shift));
  922. }
  923. EXPORT_SYMBOL_GPL(get_send_extend_sge);
  924. bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
  925. struct ib_cq *ib_cq)
  926. {
  927. struct hns_roce_cq *hr_cq;
  928. u32 cur;
  929. cur = hr_wq->head - hr_wq->tail;
  930. if (likely(cur + nreq < hr_wq->max_post))
  931. return false;
  932. hr_cq = to_hr_cq(ib_cq);
  933. spin_lock(&hr_cq->lock);
  934. cur = hr_wq->head - hr_wq->tail;
  935. spin_unlock(&hr_cq->lock);
  936. return cur + nreq >= hr_wq->max_post;
  937. }
  938. EXPORT_SYMBOL_GPL(hns_roce_wq_overflow);
  939. int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
  940. {
  941. struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
  942. int reserved_from_top = 0;
  943. int ret;
  944. spin_lock_init(&qp_table->lock);
  945. INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC);
  946. /* A port include two SQP, six port total 12 */
  947. ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps,
  948. hr_dev->caps.num_qps - 1, SQP_NUM,
  949. reserved_from_top);
  950. if (ret) {
  951. dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n",
  952. ret);
  953. return ret;
  954. }
  955. return 0;
  956. }
  957. void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
  958. {
  959. hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap);
  960. }