user_sdma.h 8.0 KB

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  1. #ifndef _HFI1_USER_SDMA_H
  2. #define _HFI1_USER_SDMA_H
  3. /*
  4. * Copyright(c) 2015 - 2018 Intel Corporation.
  5. *
  6. * This file is provided under a dual BSD/GPLv2 license. When using or
  7. * redistributing this file, you may do so under either license.
  8. *
  9. * GPL LICENSE SUMMARY
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * BSD LICENSE
  21. *
  22. * Redistribution and use in source and binary forms, with or without
  23. * modification, are permitted provided that the following conditions
  24. * are met:
  25. *
  26. * - Redistributions of source code must retain the above copyright
  27. * notice, this list of conditions and the following disclaimer.
  28. * - Redistributions in binary form must reproduce the above copyright
  29. * notice, this list of conditions and the following disclaimer in
  30. * the documentation and/or other materials provided with the
  31. * distribution.
  32. * - Neither the name of Intel Corporation nor the names of its
  33. * contributors may be used to endorse or promote products derived
  34. * from this software without specific prior written permission.
  35. *
  36. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  37. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  38. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  39. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  40. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  41. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  42. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  43. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  44. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  45. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  46. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  47. *
  48. */
  49. #include <linux/device.h>
  50. #include <linux/wait.h>
  51. #include "common.h"
  52. #include "iowait.h"
  53. #include "user_exp_rcv.h"
  54. /* The maximum number of Data io vectors per message/request */
  55. #define MAX_VECTORS_PER_REQ 8
  56. /*
  57. * Maximum number of packet to send from each message/request
  58. * before moving to the next one.
  59. */
  60. #define MAX_PKTS_PER_QUEUE 16
  61. #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
  62. #define req_opcode(x) \
  63. (((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
  64. #define req_version(x) \
  65. (((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
  66. #define req_iovcnt(x) \
  67. (((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK)
  68. /* Number of BTH.PSN bits used for sequence number in expected rcvs */
  69. #define BTH_SEQ_MASK 0x7ffull
  70. #define AHG_KDETH_INTR_SHIFT 12
  71. #define AHG_KDETH_SH_SHIFT 13
  72. #define AHG_KDETH_ARRAY_SIZE 9
  73. #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
  74. #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
  75. /**
  76. * Build an SDMA AHG header update descriptor and save it to an array.
  77. * @arr - Array to save the descriptor to.
  78. * @idx - Index of the array at which the descriptor will be saved.
  79. * @array_size - Size of the array arr.
  80. * @dw - Update index into the header in DWs.
  81. * @bit - Start bit.
  82. * @width - Field width.
  83. * @value - 16 bits of immediate data to write into the field.
  84. * Returns -ERANGE if idx is invalid. If successful, returns the next index
  85. * (idx + 1) of the array to be used for the next descriptor.
  86. */
  87. static inline int ahg_header_set(u32 *arr, int idx, size_t array_size,
  88. u8 dw, u8 bit, u8 width, u16 value)
  89. {
  90. if ((size_t)idx >= array_size)
  91. return -ERANGE;
  92. arr[idx++] = sdma_build_ahg_descriptor(value, dw, bit, width);
  93. return idx;
  94. }
  95. /* Tx request flag bits */
  96. #define TXREQ_FLAGS_REQ_ACK BIT(0) /* Set the ACK bit in the header */
  97. #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */
  98. #define SDMA_PKT_Q_INACTIVE BIT(0)
  99. #define SDMA_PKT_Q_ACTIVE BIT(1)
  100. #define SDMA_PKT_Q_DEFERRED BIT(2)
  101. /*
  102. * Maximum retry attempts to submit a TX request
  103. * before putting the process to sleep.
  104. */
  105. #define MAX_DEFER_RETRY_COUNT 1
  106. #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */
  107. #define SDMA_DBG(req, fmt, ...) \
  108. hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
  109. (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \
  110. ##__VA_ARGS__)
  111. struct hfi1_user_sdma_pkt_q {
  112. u16 ctxt;
  113. u16 subctxt;
  114. u16 n_max_reqs;
  115. atomic_t n_reqs;
  116. u16 reqidx;
  117. struct hfi1_devdata *dd;
  118. struct kmem_cache *txreq_cache;
  119. struct user_sdma_request *reqs;
  120. unsigned long *req_in_use;
  121. struct iowait busy;
  122. unsigned state;
  123. wait_queue_head_t wait;
  124. unsigned long unpinned;
  125. struct mmu_rb_handler *handler;
  126. atomic_t n_locked;
  127. struct mm_struct *mm;
  128. };
  129. struct hfi1_user_sdma_comp_q {
  130. u16 nentries;
  131. struct hfi1_sdma_comp_entry *comps;
  132. };
  133. struct sdma_mmu_node {
  134. struct mmu_rb_node rb;
  135. struct hfi1_user_sdma_pkt_q *pq;
  136. atomic_t refcount;
  137. struct page **pages;
  138. unsigned int npages;
  139. };
  140. struct user_sdma_iovec {
  141. struct list_head list;
  142. struct iovec iov;
  143. /* number of pages in this vector */
  144. unsigned int npages;
  145. /* array of pinned pages for this vector */
  146. struct page **pages;
  147. /*
  148. * offset into the virtual address space of the vector at
  149. * which we last left off.
  150. */
  151. u64 offset;
  152. struct sdma_mmu_node *node;
  153. };
  154. /* evict operation argument */
  155. struct evict_data {
  156. u32 cleared; /* count evicted so far */
  157. u32 target; /* target count to evict */
  158. };
  159. struct user_sdma_request {
  160. /* This is the original header from user space */
  161. struct hfi1_pkt_header hdr;
  162. /* Read mostly fields */
  163. struct hfi1_user_sdma_pkt_q *pq ____cacheline_aligned_in_smp;
  164. struct hfi1_user_sdma_comp_q *cq;
  165. /*
  166. * Pointer to the SDMA engine for this request.
  167. * Since different request could be on different VLs,
  168. * each request will need it's own engine pointer.
  169. */
  170. struct sdma_engine *sde;
  171. struct sdma_req_info info;
  172. /* TID array values copied from the tid_iov vector */
  173. u32 *tids;
  174. /* total length of the data in the request */
  175. u32 data_len;
  176. /* number of elements copied to the tids array */
  177. u16 n_tids;
  178. /*
  179. * We copy the iovs for this request (based on
  180. * info.iovcnt). These are only the data vectors
  181. */
  182. u8 data_iovs;
  183. s8 ahg_idx;
  184. /* Writeable fields shared with interrupt */
  185. u64 seqcomp ____cacheline_aligned_in_smp;
  186. u64 seqsubmitted;
  187. /* status of the last txreq completed */
  188. int status;
  189. /* Send side fields */
  190. struct list_head txps ____cacheline_aligned_in_smp;
  191. u64 seqnum;
  192. /*
  193. * KDETH.OFFSET (TID) field
  194. * The offset can cover multiple packets, depending on the
  195. * size of the TID entry.
  196. */
  197. u32 tidoffset;
  198. /*
  199. * KDETH.Offset (Eager) field
  200. * We need to remember the initial value so the headers
  201. * can be updated properly.
  202. */
  203. u32 koffset;
  204. u32 sent;
  205. /* TID index copied from the tid_iov vector */
  206. u16 tididx;
  207. /* progress index moving along the iovs array */
  208. u8 iov_idx;
  209. u8 done;
  210. u8 has_error;
  211. struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ];
  212. } ____cacheline_aligned_in_smp;
  213. /*
  214. * A single txreq could span up to 3 physical pages when the MTU
  215. * is sufficiently large (> 4K). Each of the IOV pointers also
  216. * needs it's own set of flags so the vector has been handled
  217. * independently of each other.
  218. */
  219. struct user_sdma_txreq {
  220. /* Packet header for the txreq */
  221. struct hfi1_pkt_header hdr;
  222. struct sdma_txreq txreq;
  223. struct list_head list;
  224. struct user_sdma_request *req;
  225. u16 flags;
  226. unsigned int busycount;
  227. u64 seqnum;
  228. };
  229. int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt,
  230. struct hfi1_filedata *fd);
  231. int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd,
  232. struct hfi1_ctxtdata *uctxt);
  233. int hfi1_user_sdma_process_request(struct hfi1_filedata *fd,
  234. struct iovec *iovec, unsigned long dim,
  235. unsigned long *count);
  236. #endif /* _HFI1_USER_SDMA_H */