ti-ads7950.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Texas Instruments ADS7950 SPI ADC driver
  4. *
  5. * Copyright 2016 David Lechner <david@lechnology.com>
  6. *
  7. * Based on iio/ad7923.c:
  8. * Copyright 2011 Analog Devices Inc
  9. * Copyright 2012 CS Systemes d'Information
  10. *
  11. * And also on hwmon/ads79xx.c
  12. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  13. * Nishanth Menon
  14. */
  15. #include <linux/acpi.h>
  16. #include <linux/bitops.h>
  17. #include <linux/device.h>
  18. #include <linux/err.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kernel.h>
  21. #include <linux/module.h>
  22. #include <linux/regulator/consumer.h>
  23. #include <linux/slab.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/iio/buffer.h>
  26. #include <linux/iio/iio.h>
  27. #include <linux/iio/sysfs.h>
  28. #include <linux/iio/trigger_consumer.h>
  29. #include <linux/iio/triggered_buffer.h>
  30. /*
  31. * In case of ACPI, we use the 5000 mV as default for the reference pin.
  32. * Device tree users encode that via the vref-supply regulator.
  33. */
  34. #define TI_ADS7950_VA_MV_ACPI_DEFAULT 5000
  35. #define TI_ADS7950_CR_MANUAL BIT(12)
  36. #define TI_ADS7950_CR_WRITE BIT(11)
  37. #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)
  38. #define TI_ADS7950_CR_RANGE_5V BIT(6)
  39. #define TI_ADS7950_MAX_CHAN 16
  40. #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
  41. /* val = value, dec = left shift, bits = number of bits of the mask */
  42. #define TI_ADS7950_EXTRACT(val, dec, bits) \
  43. (((val) >> (dec)) & ((1 << (bits)) - 1))
  44. struct ti_ads7950_state {
  45. struct spi_device *spi;
  46. struct spi_transfer ring_xfer[TI_ADS7950_MAX_CHAN + 2];
  47. struct spi_transfer scan_single_xfer[3];
  48. struct spi_message ring_msg;
  49. struct spi_message scan_single_msg;
  50. struct regulator *reg;
  51. unsigned int vref_mv;
  52. unsigned int settings;
  53. /*
  54. * DMA (thus cache coherency maintenance) requires the
  55. * transfer buffers to live in their own cache lines.
  56. */
  57. __be16 rx_buf[TI_ADS7950_MAX_CHAN + TI_ADS7950_TIMESTAMP_SIZE]
  58. ____cacheline_aligned;
  59. __be16 tx_buf[TI_ADS7950_MAX_CHAN];
  60. __be16 single_tx;
  61. __be16 single_rx;
  62. };
  63. struct ti_ads7950_chip_info {
  64. const struct iio_chan_spec *channels;
  65. unsigned int num_channels;
  66. };
  67. enum ti_ads7950_id {
  68. TI_ADS7950,
  69. TI_ADS7951,
  70. TI_ADS7952,
  71. TI_ADS7953,
  72. TI_ADS7954,
  73. TI_ADS7955,
  74. TI_ADS7956,
  75. TI_ADS7957,
  76. TI_ADS7958,
  77. TI_ADS7959,
  78. TI_ADS7960,
  79. TI_ADS7961,
  80. };
  81. #define TI_ADS7950_V_CHAN(index, bits) \
  82. { \
  83. .type = IIO_VOLTAGE, \
  84. .indexed = 1, \
  85. .channel = index, \
  86. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  87. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  88. .address = index, \
  89. .datasheet_name = "CH##index", \
  90. .scan_index = index, \
  91. .scan_type = { \
  92. .sign = 'u', \
  93. .realbits = bits, \
  94. .storagebits = 16, \
  95. .shift = 12 - (bits), \
  96. .endianness = IIO_BE, \
  97. }, \
  98. }
  99. #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
  100. const struct iio_chan_spec name ## _channels[] = { \
  101. TI_ADS7950_V_CHAN(0, bits), \
  102. TI_ADS7950_V_CHAN(1, bits), \
  103. TI_ADS7950_V_CHAN(2, bits), \
  104. TI_ADS7950_V_CHAN(3, bits), \
  105. IIO_CHAN_SOFT_TIMESTAMP(4), \
  106. }
  107. #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
  108. const struct iio_chan_spec name ## _channels[] = { \
  109. TI_ADS7950_V_CHAN(0, bits), \
  110. TI_ADS7950_V_CHAN(1, bits), \
  111. TI_ADS7950_V_CHAN(2, bits), \
  112. TI_ADS7950_V_CHAN(3, bits), \
  113. TI_ADS7950_V_CHAN(4, bits), \
  114. TI_ADS7950_V_CHAN(5, bits), \
  115. TI_ADS7950_V_CHAN(6, bits), \
  116. TI_ADS7950_V_CHAN(7, bits), \
  117. IIO_CHAN_SOFT_TIMESTAMP(8), \
  118. }
  119. #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
  120. const struct iio_chan_spec name ## _channels[] = { \
  121. TI_ADS7950_V_CHAN(0, bits), \
  122. TI_ADS7950_V_CHAN(1, bits), \
  123. TI_ADS7950_V_CHAN(2, bits), \
  124. TI_ADS7950_V_CHAN(3, bits), \
  125. TI_ADS7950_V_CHAN(4, bits), \
  126. TI_ADS7950_V_CHAN(5, bits), \
  127. TI_ADS7950_V_CHAN(6, bits), \
  128. TI_ADS7950_V_CHAN(7, bits), \
  129. TI_ADS7950_V_CHAN(8, bits), \
  130. TI_ADS7950_V_CHAN(9, bits), \
  131. TI_ADS7950_V_CHAN(10, bits), \
  132. TI_ADS7950_V_CHAN(11, bits), \
  133. IIO_CHAN_SOFT_TIMESTAMP(12), \
  134. }
  135. #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
  136. const struct iio_chan_spec name ## _channels[] = { \
  137. TI_ADS7950_V_CHAN(0, bits), \
  138. TI_ADS7950_V_CHAN(1, bits), \
  139. TI_ADS7950_V_CHAN(2, bits), \
  140. TI_ADS7950_V_CHAN(3, bits), \
  141. TI_ADS7950_V_CHAN(4, bits), \
  142. TI_ADS7950_V_CHAN(5, bits), \
  143. TI_ADS7950_V_CHAN(6, bits), \
  144. TI_ADS7950_V_CHAN(7, bits), \
  145. TI_ADS7950_V_CHAN(8, bits), \
  146. TI_ADS7950_V_CHAN(9, bits), \
  147. TI_ADS7950_V_CHAN(10, bits), \
  148. TI_ADS7950_V_CHAN(11, bits), \
  149. TI_ADS7950_V_CHAN(12, bits), \
  150. TI_ADS7950_V_CHAN(13, bits), \
  151. TI_ADS7950_V_CHAN(14, bits), \
  152. TI_ADS7950_V_CHAN(15, bits), \
  153. IIO_CHAN_SOFT_TIMESTAMP(16), \
  154. }
  155. static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
  156. static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
  157. static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
  158. static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
  159. static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
  160. static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
  161. static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
  162. static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
  163. static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
  164. static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
  165. static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
  166. static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
  167. static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
  168. [TI_ADS7950] = {
  169. .channels = ti_ads7950_channels,
  170. .num_channels = ARRAY_SIZE(ti_ads7950_channels),
  171. },
  172. [TI_ADS7951] = {
  173. .channels = ti_ads7951_channels,
  174. .num_channels = ARRAY_SIZE(ti_ads7951_channels),
  175. },
  176. [TI_ADS7952] = {
  177. .channels = ti_ads7952_channels,
  178. .num_channels = ARRAY_SIZE(ti_ads7952_channels),
  179. },
  180. [TI_ADS7953] = {
  181. .channels = ti_ads7953_channels,
  182. .num_channels = ARRAY_SIZE(ti_ads7953_channels),
  183. },
  184. [TI_ADS7954] = {
  185. .channels = ti_ads7954_channels,
  186. .num_channels = ARRAY_SIZE(ti_ads7954_channels),
  187. },
  188. [TI_ADS7955] = {
  189. .channels = ti_ads7955_channels,
  190. .num_channels = ARRAY_SIZE(ti_ads7955_channels),
  191. },
  192. [TI_ADS7956] = {
  193. .channels = ti_ads7956_channels,
  194. .num_channels = ARRAY_SIZE(ti_ads7956_channels),
  195. },
  196. [TI_ADS7957] = {
  197. .channels = ti_ads7957_channels,
  198. .num_channels = ARRAY_SIZE(ti_ads7957_channels),
  199. },
  200. [TI_ADS7958] = {
  201. .channels = ti_ads7958_channels,
  202. .num_channels = ARRAY_SIZE(ti_ads7958_channels),
  203. },
  204. [TI_ADS7959] = {
  205. .channels = ti_ads7959_channels,
  206. .num_channels = ARRAY_SIZE(ti_ads7959_channels),
  207. },
  208. [TI_ADS7960] = {
  209. .channels = ti_ads7960_channels,
  210. .num_channels = ARRAY_SIZE(ti_ads7960_channels),
  211. },
  212. [TI_ADS7961] = {
  213. .channels = ti_ads7961_channels,
  214. .num_channels = ARRAY_SIZE(ti_ads7961_channels),
  215. },
  216. };
  217. /*
  218. * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
  219. * scan mask
  220. */
  221. static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
  222. const unsigned long *active_scan_mask)
  223. {
  224. struct ti_ads7950_state *st = iio_priv(indio_dev);
  225. int i, cmd, len;
  226. len = 0;
  227. for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
  228. cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(i) | st->settings;
  229. st->tx_buf[len++] = cpu_to_be16(cmd);
  230. }
  231. /* Data for the 1st channel is not returned until the 3rd transfer */
  232. len += 2;
  233. for (i = 0; i < len; i++) {
  234. if ((i + 2) < len)
  235. st->ring_xfer[i].tx_buf = &st->tx_buf[i];
  236. if (i >= 2)
  237. st->ring_xfer[i].rx_buf = &st->rx_buf[i - 2];
  238. st->ring_xfer[i].len = 2;
  239. st->ring_xfer[i].cs_change = 1;
  240. }
  241. /* make sure last transfer's cs_change is not set */
  242. st->ring_xfer[len - 1].cs_change = 0;
  243. spi_message_init_with_transfers(&st->ring_msg, st->ring_xfer, len);
  244. return 0;
  245. }
  246. static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
  247. {
  248. struct iio_poll_func *pf = p;
  249. struct iio_dev *indio_dev = pf->indio_dev;
  250. struct ti_ads7950_state *st = iio_priv(indio_dev);
  251. int ret;
  252. ret = spi_sync(st->spi, &st->ring_msg);
  253. if (ret < 0)
  254. goto out;
  255. iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
  256. iio_get_time_ns(indio_dev));
  257. out:
  258. iio_trigger_notify_done(indio_dev->trig);
  259. return IRQ_HANDLED;
  260. }
  261. static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
  262. {
  263. struct ti_ads7950_state *st = iio_priv(indio_dev);
  264. int ret, cmd;
  265. mutex_lock(&indio_dev->mlock);
  266. cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(ch) | st->settings;
  267. st->single_tx = cpu_to_be16(cmd);
  268. ret = spi_sync(st->spi, &st->scan_single_msg);
  269. if (ret)
  270. goto out;
  271. ret = be16_to_cpu(st->single_rx);
  272. out:
  273. mutex_unlock(&indio_dev->mlock);
  274. return ret;
  275. }
  276. static int ti_ads7950_get_range(struct ti_ads7950_state *st)
  277. {
  278. int vref;
  279. if (st->vref_mv) {
  280. vref = st->vref_mv;
  281. } else {
  282. vref = regulator_get_voltage(st->reg);
  283. if (vref < 0)
  284. return vref;
  285. vref /= 1000;
  286. }
  287. if (st->settings & TI_ADS7950_CR_RANGE_5V)
  288. vref *= 2;
  289. return vref;
  290. }
  291. static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
  292. struct iio_chan_spec const *chan,
  293. int *val, int *val2, long m)
  294. {
  295. struct ti_ads7950_state *st = iio_priv(indio_dev);
  296. int ret;
  297. switch (m) {
  298. case IIO_CHAN_INFO_RAW:
  299. ret = ti_ads7950_scan_direct(indio_dev, chan->address);
  300. if (ret < 0)
  301. return ret;
  302. if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
  303. return -EIO;
  304. *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
  305. chan->scan_type.realbits);
  306. return IIO_VAL_INT;
  307. case IIO_CHAN_INFO_SCALE:
  308. ret = ti_ads7950_get_range(st);
  309. if (ret < 0)
  310. return ret;
  311. *val = ret;
  312. *val2 = (1 << chan->scan_type.realbits) - 1;
  313. return IIO_VAL_FRACTIONAL;
  314. }
  315. return -EINVAL;
  316. }
  317. static const struct iio_info ti_ads7950_info = {
  318. .read_raw = &ti_ads7950_read_raw,
  319. .update_scan_mode = ti_ads7950_update_scan_mode,
  320. };
  321. static int ti_ads7950_probe(struct spi_device *spi)
  322. {
  323. struct ti_ads7950_state *st;
  324. struct iio_dev *indio_dev;
  325. const struct ti_ads7950_chip_info *info;
  326. int ret;
  327. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  328. if (!indio_dev)
  329. return -ENOMEM;
  330. st = iio_priv(indio_dev);
  331. spi_set_drvdata(spi, indio_dev);
  332. st->spi = spi;
  333. st->settings = TI_ADS7950_CR_MANUAL | TI_ADS7950_CR_RANGE_5V;
  334. info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
  335. indio_dev->name = spi_get_device_id(spi)->name;
  336. indio_dev->dev.parent = &spi->dev;
  337. indio_dev->modes = INDIO_DIRECT_MODE;
  338. indio_dev->channels = info->channels;
  339. indio_dev->num_channels = info->num_channels;
  340. indio_dev->info = &ti_ads7950_info;
  341. /*
  342. * Setup default message. The sample is read at the end of the first
  343. * transfer, then it takes one full cycle to convert the sample and one
  344. * more cycle to send the value. The conversion process is driven by
  345. * the SPI clock, which is why we have 3 transfers. The middle one is
  346. * just dummy data sent while the chip is converting the sample that
  347. * was read at the end of the first transfer.
  348. */
  349. st->scan_single_xfer[0].tx_buf = &st->single_tx;
  350. st->scan_single_xfer[0].len = 2;
  351. st->scan_single_xfer[0].cs_change = 1;
  352. st->scan_single_xfer[1].tx_buf = &st->single_tx;
  353. st->scan_single_xfer[1].len = 2;
  354. st->scan_single_xfer[1].cs_change = 1;
  355. st->scan_single_xfer[2].rx_buf = &st->single_rx;
  356. st->scan_single_xfer[2].len = 2;
  357. spi_message_init_with_transfers(&st->scan_single_msg,
  358. st->scan_single_xfer, 3);
  359. /* Use hard coded value for reference voltage in ACPI case */
  360. if (ACPI_COMPANION(&spi->dev))
  361. st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
  362. st->reg = devm_regulator_get(&spi->dev, "vref");
  363. if (IS_ERR(st->reg)) {
  364. dev_err(&spi->dev, "Failed get get regulator \"vref\"\n");
  365. return PTR_ERR(st->reg);
  366. }
  367. ret = regulator_enable(st->reg);
  368. if (ret) {
  369. dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
  370. return ret;
  371. }
  372. ret = iio_triggered_buffer_setup(indio_dev, NULL,
  373. &ti_ads7950_trigger_handler, NULL);
  374. if (ret) {
  375. dev_err(&spi->dev, "Failed to setup triggered buffer\n");
  376. goto error_disable_reg;
  377. }
  378. ret = iio_device_register(indio_dev);
  379. if (ret) {
  380. dev_err(&spi->dev, "Failed to register iio device\n");
  381. goto error_cleanup_ring;
  382. }
  383. return 0;
  384. error_cleanup_ring:
  385. iio_triggered_buffer_cleanup(indio_dev);
  386. error_disable_reg:
  387. regulator_disable(st->reg);
  388. return ret;
  389. }
  390. static int ti_ads7950_remove(struct spi_device *spi)
  391. {
  392. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  393. struct ti_ads7950_state *st = iio_priv(indio_dev);
  394. iio_device_unregister(indio_dev);
  395. iio_triggered_buffer_cleanup(indio_dev);
  396. regulator_disable(st->reg);
  397. return 0;
  398. }
  399. static const struct spi_device_id ti_ads7950_id[] = {
  400. { "ads7950", TI_ADS7950 },
  401. { "ads7951", TI_ADS7951 },
  402. { "ads7952", TI_ADS7952 },
  403. { "ads7953", TI_ADS7953 },
  404. { "ads7954", TI_ADS7954 },
  405. { "ads7955", TI_ADS7955 },
  406. { "ads7956", TI_ADS7956 },
  407. { "ads7957", TI_ADS7957 },
  408. { "ads7958", TI_ADS7958 },
  409. { "ads7959", TI_ADS7959 },
  410. { "ads7960", TI_ADS7960 },
  411. { "ads7961", TI_ADS7961 },
  412. { }
  413. };
  414. MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
  415. static const struct of_device_id ads7950_of_table[] = {
  416. { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
  417. { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
  418. { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
  419. { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
  420. { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
  421. { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
  422. { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
  423. { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
  424. { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
  425. { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
  426. { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
  427. { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
  428. { },
  429. };
  430. MODULE_DEVICE_TABLE(of, ads7950_of_table);
  431. static struct spi_driver ti_ads7950_driver = {
  432. .driver = {
  433. .name = "ads7950",
  434. .of_match_table = ads7950_of_table,
  435. },
  436. .probe = ti_ads7950_probe,
  437. .remove = ti_ads7950_remove,
  438. .id_table = ti_ads7950_id,
  439. };
  440. module_spi_driver(ti_ads7950_driver);
  441. MODULE_AUTHOR("David Lechner <david@lechnology.com>");
  442. MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
  443. MODULE_LICENSE("GPL v2");