mtu3_plat.c 8.7 KB

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  1. /*
  2. * Copyright (C) 2016 MediaTek Inc.
  3. *
  4. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/pinctrl/consumer.h>
  24. #include <linux/platform_device.h>
  25. #include "mtu3.h"
  26. #include "mtu3_dr.h"
  27. /* u2-port0 should be powered on and enabled; */
  28. int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
  29. {
  30. void __iomem *ibase = ssusb->ippc_base;
  31. u32 value, check_val;
  32. int ret;
  33. check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
  34. SSUSB_REF_RST_B_STS;
  35. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
  36. (check_val == (value & check_val)), 100, 20000);
  37. if (ret) {
  38. dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
  39. return ret;
  40. }
  41. ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
  42. (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
  43. if (ret) {
  44. dev_err(ssusb->dev, "mac2 clock is not stable\n");
  45. return ret;
  46. }
  47. return 0;
  48. }
  49. static int ssusb_phy_init(struct ssusb_mtk *ssusb)
  50. {
  51. int i;
  52. int ret;
  53. for (i = 0; i < ssusb->num_phys; i++) {
  54. ret = phy_init(ssusb->phys[i]);
  55. if (ret)
  56. goto exit_phy;
  57. }
  58. return 0;
  59. exit_phy:
  60. for (; i > 0; i--)
  61. phy_exit(ssusb->phys[i - 1]);
  62. return ret;
  63. }
  64. static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
  65. {
  66. int i;
  67. for (i = 0; i < ssusb->num_phys; i++)
  68. phy_exit(ssusb->phys[i]);
  69. return 0;
  70. }
  71. static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
  72. {
  73. int i;
  74. int ret;
  75. for (i = 0; i < ssusb->num_phys; i++) {
  76. ret = phy_power_on(ssusb->phys[i]);
  77. if (ret)
  78. goto power_off_phy;
  79. }
  80. return 0;
  81. power_off_phy:
  82. for (; i > 0; i--)
  83. phy_power_off(ssusb->phys[i - 1]);
  84. return ret;
  85. }
  86. static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
  87. {
  88. unsigned int i;
  89. for (i = 0; i < ssusb->num_phys; i++)
  90. phy_power_off(ssusb->phys[i]);
  91. }
  92. static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
  93. {
  94. int ret = 0;
  95. ret = regulator_enable(ssusb->vusb33);
  96. if (ret) {
  97. dev_err(ssusb->dev, "failed to enable vusb33\n");
  98. goto vusb33_err;
  99. }
  100. ret = clk_prepare_enable(ssusb->sys_clk);
  101. if (ret) {
  102. dev_err(ssusb->dev, "failed to enable sys_clk\n");
  103. goto clk_err;
  104. }
  105. ret = ssusb_phy_init(ssusb);
  106. if (ret) {
  107. dev_err(ssusb->dev, "failed to init phy\n");
  108. goto phy_init_err;
  109. }
  110. ret = ssusb_phy_power_on(ssusb);
  111. if (ret) {
  112. dev_err(ssusb->dev, "failed to power on phy\n");
  113. goto phy_err;
  114. }
  115. return 0;
  116. phy_err:
  117. ssusb_phy_exit(ssusb);
  118. phy_init_err:
  119. clk_disable_unprepare(ssusb->sys_clk);
  120. clk_err:
  121. regulator_disable(ssusb->vusb33);
  122. vusb33_err:
  123. return ret;
  124. }
  125. static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
  126. {
  127. clk_disable_unprepare(ssusb->sys_clk);
  128. regulator_disable(ssusb->vusb33);
  129. ssusb_phy_power_off(ssusb);
  130. ssusb_phy_exit(ssusb);
  131. }
  132. static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
  133. {
  134. /* reset whole ip (xhci & u3d) */
  135. mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  136. udelay(1);
  137. mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
  138. }
  139. static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
  140. {
  141. struct device_node *node = pdev->dev.of_node;
  142. struct device *dev = &pdev->dev;
  143. struct resource *res;
  144. int i;
  145. int ret;
  146. ssusb->num_phys = of_count_phandle_with_args(node,
  147. "phys", "#phy-cells");
  148. if (ssusb->num_phys > 0) {
  149. ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
  150. sizeof(*ssusb->phys), GFP_KERNEL);
  151. if (!ssusb->phys)
  152. return -ENOMEM;
  153. } else {
  154. ssusb->num_phys = 0;
  155. }
  156. for (i = 0; i < ssusb->num_phys; i++) {
  157. ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
  158. if (IS_ERR(ssusb->phys[i])) {
  159. dev_err(dev, "failed to get phy-%d\n", i);
  160. return PTR_ERR(ssusb->phys[i]);
  161. }
  162. }
  163. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
  164. ssusb->ippc_base = devm_ioremap_resource(dev, res);
  165. if (IS_ERR(ssusb->ippc_base)) {
  166. dev_err(dev, "failed to map memory for ippc\n");
  167. return PTR_ERR(ssusb->ippc_base);
  168. }
  169. ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
  170. if (IS_ERR(ssusb->vusb33)) {
  171. dev_err(dev, "failed to get vusb33\n");
  172. return PTR_ERR(ssusb->vusb33);
  173. }
  174. ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
  175. if (IS_ERR(ssusb->sys_clk)) {
  176. dev_err(dev, "failed to get sys clock\n");
  177. return PTR_ERR(ssusb->sys_clk);
  178. }
  179. ssusb->dr_mode = usb_get_dr_mode(dev);
  180. if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
  181. dev_err(dev, "dr_mode is error\n");
  182. return -EINVAL;
  183. }
  184. if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
  185. return 0;
  186. /* if host role is supported */
  187. ret = ssusb_wakeup_of_property_parse(ssusb, node);
  188. if (ret)
  189. return ret;
  190. return 0;
  191. }
  192. static int mtu3_probe(struct platform_device *pdev)
  193. {
  194. struct device_node *node = pdev->dev.of_node;
  195. struct device *dev = &pdev->dev;
  196. struct ssusb_mtk *ssusb;
  197. int ret = -ENOMEM;
  198. /* all elements are set to ZERO as default value */
  199. ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
  200. if (!ssusb)
  201. return -ENOMEM;
  202. ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
  203. if (ret) {
  204. dev_err(dev, "No suitable DMA config available\n");
  205. return -ENOTSUPP;
  206. }
  207. platform_set_drvdata(pdev, ssusb);
  208. ssusb->dev = dev;
  209. ret = get_ssusb_rscs(pdev, ssusb);
  210. if (ret)
  211. return ret;
  212. /* enable power domain */
  213. pm_runtime_enable(dev);
  214. pm_runtime_get_sync(dev);
  215. device_enable_async_suspend(dev);
  216. ret = ssusb_rscs_init(ssusb);
  217. if (ret)
  218. goto comm_init_err;
  219. ssusb_ip_sw_reset(ssusb);
  220. if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
  221. ssusb->dr_mode = USB_DR_MODE_HOST;
  222. else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
  223. ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
  224. /* default as host */
  225. ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
  226. switch (ssusb->dr_mode) {
  227. case USB_DR_MODE_PERIPHERAL:
  228. ret = ssusb_gadget_init(ssusb);
  229. if (ret) {
  230. dev_err(dev, "failed to initialize gadget\n");
  231. goto comm_exit;
  232. }
  233. break;
  234. case USB_DR_MODE_HOST:
  235. ret = ssusb_host_init(ssusb, node);
  236. if (ret) {
  237. dev_err(dev, "failed to initialize host\n");
  238. goto comm_exit;
  239. }
  240. break;
  241. default:
  242. dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
  243. ret = -EINVAL;
  244. goto comm_exit;
  245. }
  246. return 0;
  247. comm_exit:
  248. ssusb_rscs_exit(ssusb);
  249. comm_init_err:
  250. pm_runtime_put_sync(dev);
  251. pm_runtime_disable(dev);
  252. return ret;
  253. }
  254. static int mtu3_remove(struct platform_device *pdev)
  255. {
  256. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  257. switch (ssusb->dr_mode) {
  258. case USB_DR_MODE_PERIPHERAL:
  259. ssusb_gadget_exit(ssusb);
  260. break;
  261. case USB_DR_MODE_HOST:
  262. ssusb_host_exit(ssusb);
  263. break;
  264. default:
  265. return -EINVAL;
  266. }
  267. ssusb_rscs_exit(ssusb);
  268. pm_runtime_put_sync(&pdev->dev);
  269. pm_runtime_disable(&pdev->dev);
  270. return 0;
  271. }
  272. /*
  273. * when support dual-role mode, we reject suspend when
  274. * it works as device mode;
  275. */
  276. static int __maybe_unused mtu3_suspend(struct device *dev)
  277. {
  278. struct platform_device *pdev = to_platform_device(dev);
  279. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  280. dev_dbg(dev, "%s\n", __func__);
  281. /* REVISIT: disconnect it for only device mode? */
  282. if (!ssusb->is_host)
  283. return 0;
  284. ssusb_host_disable(ssusb, true);
  285. ssusb_phy_power_off(ssusb);
  286. clk_disable_unprepare(ssusb->sys_clk);
  287. ssusb_wakeup_enable(ssusb);
  288. return 0;
  289. }
  290. static int __maybe_unused mtu3_resume(struct device *dev)
  291. {
  292. struct platform_device *pdev = to_platform_device(dev);
  293. struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
  294. dev_dbg(dev, "%s\n", __func__);
  295. if (!ssusb->is_host)
  296. return 0;
  297. ssusb_wakeup_disable(ssusb);
  298. clk_prepare_enable(ssusb->sys_clk);
  299. ssusb_phy_power_on(ssusb);
  300. ssusb_host_enable(ssusb);
  301. return 0;
  302. }
  303. static const struct dev_pm_ops mtu3_pm_ops = {
  304. SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
  305. };
  306. #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
  307. #ifdef CONFIG_OF
  308. static const struct of_device_id mtu3_of_match[] = {
  309. {.compatible = "mediatek,mt8173-mtu3",},
  310. {},
  311. };
  312. MODULE_DEVICE_TABLE(of, mtu3_of_match);
  313. #endif
  314. static struct platform_driver mtu3_driver = {
  315. .probe = mtu3_probe,
  316. .remove = mtu3_remove,
  317. .driver = {
  318. .name = MTU3_DRIVER_NAME,
  319. .pm = DEV_PM_OPS,
  320. .of_match_table = of_match_ptr(mtu3_of_match),
  321. },
  322. };
  323. module_platform_driver(mtu3_driver);
  324. MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
  325. MODULE_LICENSE("GPL v2");
  326. MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");