dm_common.c 54 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include <linux/export.h>
  30. #include "dm_common.h"
  31. #include "phy_common.h"
  32. #include "../pci.h"
  33. #include "../base.h"
  34. #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
  35. #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
  36. #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
  37. #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
  38. #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
  39. #define RTLPRIV (struct rtl_priv *)
  40. #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
  41. ((RTLPRIV(_priv))->mac80211.opmode == \
  42. NL80211_IFTYPE_ADHOC) ? \
  43. ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
  44. ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
  45. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  46. 0x7f8001fe,
  47. 0x788001e2,
  48. 0x71c001c7,
  49. 0x6b8001ae,
  50. 0x65400195,
  51. 0x5fc0017f,
  52. 0x5a400169,
  53. 0x55400155,
  54. 0x50800142,
  55. 0x4c000130,
  56. 0x47c0011f,
  57. 0x43c0010f,
  58. 0x40000100,
  59. 0x3c8000f2,
  60. 0x390000e4,
  61. 0x35c000d7,
  62. 0x32c000cb,
  63. 0x300000c0,
  64. 0x2d4000b5,
  65. 0x2ac000ab,
  66. 0x288000a2,
  67. 0x26000098,
  68. 0x24000090,
  69. 0x22000088,
  70. 0x20000080,
  71. 0x1e400079,
  72. 0x1c800072,
  73. 0x1b00006c,
  74. 0x19800066,
  75. 0x18000060,
  76. 0x16c0005b,
  77. 0x15800056,
  78. 0x14400051,
  79. 0x1300004c,
  80. 0x12000048,
  81. 0x11000044,
  82. 0x10000040,
  83. };
  84. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  85. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  86. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  87. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  88. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  89. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  90. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  91. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  92. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  93. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  94. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  95. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  96. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  97. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  98. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  99. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  100. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  101. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  102. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  103. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  104. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  105. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  106. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  107. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  108. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  109. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  110. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  111. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  112. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  113. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  114. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  115. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  116. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  117. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  118. };
  119. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  120. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  121. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  122. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  123. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  124. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  125. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  126. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  127. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  128. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  129. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  130. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  131. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  132. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  133. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  134. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  135. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  136. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  137. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  138. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  139. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  140. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  141. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  142. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  143. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  144. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  145. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  146. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  147. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  148. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  149. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  150. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  151. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  152. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  153. };
  154. static u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
  155. void dm_restorepowerindex(struct ieee80211_hw *hw)
  156. {
  157. struct rtl_priv *rtlpriv = rtl_priv(hw);
  158. u8 index;
  159. for (index = 0; index < 6; index++)
  160. rtl_write_byte(rtlpriv, power_index_reg[index],
  161. rtlpriv->dm.powerindex_backup[index]);
  162. }
  163. EXPORT_SYMBOL_GPL(dm_restorepowerindex);
  164. void dm_writepowerindex(struct ieee80211_hw *hw, u8 value)
  165. {
  166. struct rtl_priv *rtlpriv = rtl_priv(hw);
  167. u8 index;
  168. for (index = 0; index < 6; index++)
  169. rtl_write_byte(rtlpriv, power_index_reg[index], value);
  170. }
  171. EXPORT_SYMBOL_GPL(dm_writepowerindex);
  172. void dm_savepowerindex(struct ieee80211_hw *hw)
  173. {
  174. struct rtl_priv *rtlpriv = rtl_priv(hw);
  175. u8 index;
  176. u8 tmp;
  177. for (index = 0; index < 6; index++) {
  178. tmp = rtl_read_byte(rtlpriv, power_index_reg[index]);
  179. rtlpriv->dm.powerindex_backup[index] = tmp;
  180. }
  181. }
  182. EXPORT_SYMBOL_GPL(dm_savepowerindex);
  183. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  184. {
  185. struct rtl_priv *rtlpriv = rtl_priv(hw);
  186. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  187. dm_digtable->dig_enable_flag = true;
  188. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  189. dm_digtable->cur_igvalue = 0x20;
  190. dm_digtable->pre_igvalue = 0x0;
  191. dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
  192. dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
  193. dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
  194. dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
  195. dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
  196. dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  197. dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  198. dm_digtable->rx_gain_max = DM_DIG_MAX;
  199. dm_digtable->rx_gain_min = DM_DIG_MIN;
  200. dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  201. dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
  202. dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
  203. dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
  204. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_LowRssi;
  205. dm_digtable->forbidden_igi = DM_DIG_MIN;
  206. dm_digtable->large_fa_hit = 0;
  207. dm_digtable->recover_cnt = 0;
  208. dm_digtable->dig_dynamic_min = 0x25;
  209. }
  210. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  211. {
  212. struct rtl_priv *rtlpriv = rtl_priv(hw);
  213. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  214. long rssi_val_min = 0;
  215. if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
  216. (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
  217. if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
  218. rssi_val_min =
  219. (rtlpriv->dm.entry_min_undec_sm_pwdb >
  220. rtlpriv->dm.undec_sm_pwdb) ?
  221. rtlpriv->dm.undec_sm_pwdb :
  222. rtlpriv->dm.entry_min_undec_sm_pwdb;
  223. else
  224. rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  225. } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
  226. dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
  227. rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  228. } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
  229. rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
  230. }
  231. if (rssi_val_min > 100)
  232. rssi_val_min = 100;
  233. return (u8)rssi_val_min;
  234. }
  235. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  236. {
  237. u32 ret_value;
  238. struct rtl_priv *rtlpriv = rtl_priv(hw);
  239. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  240. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  241. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  242. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  243. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  244. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  245. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  246. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  247. ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
  248. falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
  249. falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
  250. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  251. falsealm_cnt->cnt_rate_illegal +
  252. falsealm_cnt->cnt_crc8_fail +
  253. falsealm_cnt->cnt_mcs_fail +
  254. falsealm_cnt->cnt_fast_fsync_fail +
  255. falsealm_cnt->cnt_sb_search_fail;
  256. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  257. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  258. falsealm_cnt->cnt_cck_fail = ret_value;
  259. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  260. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  261. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  262. falsealm_cnt->cnt_rate_illegal +
  263. falsealm_cnt->cnt_crc8_fail +
  264. falsealm_cnt->cnt_mcs_fail +
  265. falsealm_cnt->cnt_cck_fail);
  266. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  267. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  268. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  269. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  270. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  271. "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  272. falsealm_cnt->cnt_parity_fail,
  273. falsealm_cnt->cnt_rate_illegal,
  274. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
  275. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  276. "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  277. falsealm_cnt->cnt_ofdm_fail,
  278. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
  279. }
  280. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  281. {
  282. struct rtl_priv *rtlpriv = rtl_priv(hw);
  283. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  284. u8 value_igi = dm_digtable->cur_igvalue;
  285. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  286. value_igi--;
  287. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  288. value_igi += 0;
  289. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  290. value_igi++;
  291. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  292. value_igi += 2;
  293. if (value_igi > DM_DIG_FA_UPPER)
  294. value_igi = DM_DIG_FA_UPPER;
  295. else if (value_igi < DM_DIG_FA_LOWER)
  296. value_igi = DM_DIG_FA_LOWER;
  297. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  298. value_igi = DM_DIG_FA_UPPER;
  299. dm_digtable->cur_igvalue = value_igi;
  300. rtl92c_dm_write_dig(hw);
  301. }
  302. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  303. {
  304. struct rtl_priv *rtlpriv = rtl_priv(hw);
  305. struct dig_t *digtable = &rtlpriv->dm_digtable;
  306. u32 isbt;
  307. /* modify DIG lower bound, deal with abnorally large false alarm */
  308. if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
  309. digtable->large_fa_hit++;
  310. if (digtable->forbidden_igi < digtable->cur_igvalue) {
  311. digtable->forbidden_igi = digtable->cur_igvalue;
  312. digtable->large_fa_hit = 1;
  313. }
  314. if (digtable->large_fa_hit >= 3) {
  315. if ((digtable->forbidden_igi + 1) >
  316. digtable->rx_gain_max)
  317. digtable->rx_gain_min = digtable->rx_gain_max;
  318. else
  319. digtable->rx_gain_min = (digtable->forbidden_igi + 1);
  320. digtable->recover_cnt = 3600; /* 3600=2hr */
  321. }
  322. } else {
  323. /* Recovery mechanism for IGI lower bound */
  324. if (digtable->recover_cnt != 0) {
  325. digtable->recover_cnt--;
  326. } else {
  327. if (digtable->large_fa_hit == 0) {
  328. if ((digtable->forbidden_igi-1) < DM_DIG_MIN) {
  329. digtable->forbidden_igi = DM_DIG_MIN;
  330. digtable->rx_gain_min = DM_DIG_MIN;
  331. } else {
  332. digtable->forbidden_igi--;
  333. digtable->rx_gain_min = digtable->forbidden_igi + 1;
  334. }
  335. } else if (digtable->large_fa_hit == 3) {
  336. digtable->large_fa_hit = 0;
  337. }
  338. }
  339. }
  340. if (rtlpriv->falsealm_cnt.cnt_all < 250) {
  341. isbt = rtl_read_byte(rtlpriv, 0x4fd) & 0x01;
  342. if (!isbt) {
  343. if (rtlpriv->falsealm_cnt.cnt_all >
  344. digtable->fa_lowthresh) {
  345. if ((digtable->back_val - 2) <
  346. digtable->back_range_min)
  347. digtable->back_val = digtable->back_range_min;
  348. else
  349. digtable->back_val -= 2;
  350. } else if (rtlpriv->falsealm_cnt.cnt_all <
  351. digtable->fa_lowthresh) {
  352. if ((digtable->back_val + 2) >
  353. digtable->back_range_max)
  354. digtable->back_val = digtable->back_range_max;
  355. else
  356. digtable->back_val += 2;
  357. }
  358. } else {
  359. digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  360. }
  361. } else {
  362. /* Adjust initial gain by false alarm */
  363. if (rtlpriv->falsealm_cnt.cnt_all > 1000)
  364. digtable->cur_igvalue = digtable->pre_igvalue + 2;
  365. else if (rtlpriv->falsealm_cnt.cnt_all > 750)
  366. digtable->cur_igvalue = digtable->pre_igvalue + 1;
  367. else if (rtlpriv->falsealm_cnt.cnt_all < 500)
  368. digtable->cur_igvalue = digtable->pre_igvalue - 1;
  369. }
  370. /* Check initial gain by upper/lower bound */
  371. if (digtable->cur_igvalue > digtable->rx_gain_max)
  372. digtable->cur_igvalue = digtable->rx_gain_max;
  373. if (digtable->cur_igvalue < digtable->rx_gain_min)
  374. digtable->cur_igvalue = digtable->rx_gain_min;
  375. rtl92c_dm_write_dig(hw);
  376. }
  377. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  378. {
  379. static u8 initialized; /* initialized to false */
  380. struct rtl_priv *rtlpriv = rtl_priv(hw);
  381. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  382. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  383. long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
  384. bool multi_sta = false;
  385. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  386. multi_sta = true;
  387. if (!multi_sta ||
  388. dm_digtable->cursta_cstate == DIG_STA_DISCONNECT) {
  389. initialized = false;
  390. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  391. return;
  392. } else if (initialized == false) {
  393. initialized = true;
  394. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  395. dm_digtable->cur_igvalue = 0x20;
  396. rtl92c_dm_write_dig(hw);
  397. }
  398. if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
  399. if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
  400. (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  401. if (dm_digtable->dig_ext_port_stage ==
  402. DIG_EXT_PORT_STAGE_2) {
  403. dm_digtable->cur_igvalue = 0x20;
  404. rtl92c_dm_write_dig(hw);
  405. }
  406. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  407. } else if (rssi_strength > dm_digtable->rssi_highthresh) {
  408. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  409. rtl92c_dm_ctrl_initgain_by_fa(hw);
  410. }
  411. } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  412. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  413. dm_digtable->cur_igvalue = 0x20;
  414. rtl92c_dm_write_dig(hw);
  415. }
  416. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  417. "curmultista_cstate = %x dig_ext_port_stage %x\n",
  418. dm_digtable->curmultista_cstate,
  419. dm_digtable->dig_ext_port_stage);
  420. }
  421. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  422. {
  423. struct rtl_priv *rtlpriv = rtl_priv(hw);
  424. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  425. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  426. "presta_cstate = %x, cursta_cstate = %x\n",
  427. dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
  428. if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
  429. dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
  430. dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
  431. if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
  432. dm_digtable->rssi_val_min =
  433. rtl92c_dm_initial_gain_min_pwdb(hw);
  434. if (dm_digtable->rssi_val_min > 100)
  435. dm_digtable->rssi_val_min = 100;
  436. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  437. }
  438. } else {
  439. dm_digtable->rssi_val_min = 0;
  440. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  441. dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
  442. dm_digtable->cur_igvalue = 0x20;
  443. dm_digtable->pre_igvalue = 0;
  444. rtl92c_dm_write_dig(hw);
  445. }
  446. }
  447. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  448. {
  449. struct rtl_priv *rtlpriv = rtl_priv(hw);
  450. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  451. if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
  452. dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  453. if (dm_digtable->rssi_val_min > 100)
  454. dm_digtable->rssi_val_min = 100;
  455. if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  456. if (dm_digtable->rssi_val_min <= 25)
  457. dm_digtable->cur_cck_pd_state =
  458. CCK_PD_STAGE_LowRssi;
  459. else
  460. dm_digtable->cur_cck_pd_state =
  461. CCK_PD_STAGE_HighRssi;
  462. } else {
  463. if (dm_digtable->rssi_val_min <= 20)
  464. dm_digtable->cur_cck_pd_state =
  465. CCK_PD_STAGE_LowRssi;
  466. else
  467. dm_digtable->cur_cck_pd_state =
  468. CCK_PD_STAGE_HighRssi;
  469. }
  470. } else {
  471. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
  472. }
  473. if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
  474. if ((dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) ||
  475. (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_MAX))
  476. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
  477. else
  478. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  479. dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
  480. }
  481. }
  482. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  483. {
  484. struct rtl_priv *rtlpriv = rtl_priv(hw);
  485. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  486. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  487. if (mac->act_scanning)
  488. return;
  489. if (mac->link_state >= MAC80211_LINKED)
  490. dm_digtable->cursta_cstate = DIG_STA_CONNECT;
  491. else
  492. dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
  493. dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
  494. rtl92c_dm_initial_gain_sta(hw);
  495. rtl92c_dm_initial_gain_multi_sta(hw);
  496. rtl92c_dm_cck_packet_detection_thresh(hw);
  497. dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
  498. }
  499. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  500. {
  501. struct rtl_priv *rtlpriv = rtl_priv(hw);
  502. if (rtlpriv->dm.dm_initialgain_enable == false)
  503. return;
  504. if (!(rtlpriv->dm.dm_flag & DYNAMIC_FUNC_DIG))
  505. return;
  506. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  507. }
  508. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  509. {
  510. struct rtl_priv *rtlpriv = rtl_priv(hw);
  511. if (rtlpriv->rtlhal.interface == INTF_USB &&
  512. rtlpriv->rtlhal.board_type & 0x1) {
  513. dm_savepowerindex(hw);
  514. rtlpriv->dm.dynamic_txpower_enable = true;
  515. } else {
  516. rtlpriv->dm.dynamic_txpower_enable = false;
  517. }
  518. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  519. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  520. }
  521. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  522. {
  523. struct rtl_priv *rtlpriv = rtl_priv(hw);
  524. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  525. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  526. "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
  527. dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
  528. dm_digtable->back_val);
  529. if (rtlpriv->rtlhal.interface == INTF_USB &&
  530. !dm_digtable->dig_enable_flag) {
  531. dm_digtable->pre_igvalue = 0x17;
  532. return;
  533. }
  534. dm_digtable->cur_igvalue -= 1;
  535. if (dm_digtable->cur_igvalue < DM_DIG_MIN)
  536. dm_digtable->cur_igvalue = DM_DIG_MIN;
  537. if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
  538. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  539. dm_digtable->cur_igvalue);
  540. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  541. dm_digtable->cur_igvalue);
  542. dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
  543. }
  544. RT_TRACE(rtlpriv, COMP_DIG, DBG_WARNING,
  545. "dig values 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
  546. dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
  547. dm_digtable->rssi_val_min, dm_digtable->back_val,
  548. dm_digtable->rx_gain_max, dm_digtable->rx_gain_min,
  549. dm_digtable->large_fa_hit, dm_digtable->forbidden_igi);
  550. }
  551. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  552. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  553. {
  554. struct rtl_priv *rtlpriv = rtl_priv(hw);
  555. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  556. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  557. if (mac->link_state != MAC80211_LINKED)
  558. return;
  559. if (mac->opmode == NL80211_IFTYPE_ADHOC ||
  560. mac->opmode == NL80211_IFTYPE_AP) {
  561. /* TODO: Handle ADHOC and AP Mode */
  562. }
  563. if (tmpentry_max_pwdb != 0)
  564. rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb;
  565. else
  566. rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
  567. if (tmpentry_min_pwdb != 0xff)
  568. rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb;
  569. else
  570. rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
  571. /* TODO:
  572. * if (mac->opmode == NL80211_IFTYPE_STATION) {
  573. * if (rtlpriv->rtlhal.fw_ready) {
  574. * u32 param = (u32)(rtlpriv->dm.undec_sm_pwdb << 16);
  575. * rtl8192c_set_rssi_cmd(hw, param);
  576. * }
  577. * }
  578. */
  579. }
  580. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  581. {
  582. struct rtl_priv *rtlpriv = rtl_priv(hw);
  583. rtlpriv->dm.current_turbo_edca = false;
  584. rtlpriv->dm.is_any_nonbepkts = false;
  585. rtlpriv->dm.is_cur_rdlstate = false;
  586. }
  587. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  588. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  589. {
  590. struct rtl_priv *rtlpriv = rtl_priv(hw);
  591. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  592. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  593. static u64 last_txok_cnt;
  594. static u64 last_rxok_cnt;
  595. static u32 last_bt_edca_ul;
  596. static u32 last_bt_edca_dl;
  597. u64 cur_txok_cnt = 0;
  598. u64 cur_rxok_cnt = 0;
  599. u32 edca_be_ul = 0x5ea42b;
  600. u32 edca_be_dl = 0x5ea42b;
  601. bool bt_change_edca = false;
  602. if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
  603. (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
  604. rtlpriv->dm.current_turbo_edca = false;
  605. last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  606. last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
  607. }
  608. if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
  609. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  610. bt_change_edca = true;
  611. }
  612. if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
  613. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
  614. bt_change_edca = true;
  615. }
  616. if (mac->link_state != MAC80211_LINKED) {
  617. rtlpriv->dm.current_turbo_edca = false;
  618. return;
  619. }
  620. if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
  621. if (!(edca_be_ul & 0xffff0000))
  622. edca_be_ul |= 0x005e0000;
  623. if (!(edca_be_dl & 0xffff0000))
  624. edca_be_dl |= 0x005e0000;
  625. }
  626. if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
  627. (!rtlpriv->dm.disable_framebursting))) {
  628. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  629. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  630. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  631. if (!rtlpriv->dm.is_cur_rdlstate ||
  632. !rtlpriv->dm.current_turbo_edca) {
  633. rtl_write_dword(rtlpriv,
  634. REG_EDCA_BE_PARAM,
  635. edca_be_dl);
  636. rtlpriv->dm.is_cur_rdlstate = true;
  637. }
  638. } else {
  639. if (rtlpriv->dm.is_cur_rdlstate ||
  640. !rtlpriv->dm.current_turbo_edca) {
  641. rtl_write_dword(rtlpriv,
  642. REG_EDCA_BE_PARAM,
  643. edca_be_ul);
  644. rtlpriv->dm.is_cur_rdlstate = false;
  645. }
  646. }
  647. rtlpriv->dm.current_turbo_edca = true;
  648. } else {
  649. if (rtlpriv->dm.current_turbo_edca) {
  650. u8 tmp = AC0_BE;
  651. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  652. &tmp);
  653. rtlpriv->dm.current_turbo_edca = false;
  654. }
  655. }
  656. rtlpriv->dm.is_any_nonbepkts = false;
  657. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  658. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  659. }
  660. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  661. *hw)
  662. {
  663. struct rtl_priv *rtlpriv = rtl_priv(hw);
  664. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  665. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  666. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  667. u8 thermalvalue, delta, delta_lck, delta_iqk;
  668. long ele_a, ele_d, temp_cck, val_x, value32;
  669. long val_y, ele_c = 0;
  670. u8 ofdm_index[2], ofdm_index_old[2] = {0, 0}, cck_index_old = 0;
  671. s8 cck_index = 0;
  672. int i;
  673. bool is2t = IS_92C_SERIAL(rtlhal->version);
  674. s8 txpwr_level[3] = {0, 0, 0};
  675. u8 ofdm_min_index = 6, rf;
  676. rtlpriv->dm.txpower_trackinginit = true;
  677. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  678. "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
  679. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  680. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  681. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
  682. thermalvalue, rtlpriv->dm.thermalvalue,
  683. rtlefuse->eeprom_thermalmeter);
  684. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  685. rtlefuse->eeprom_thermalmeter));
  686. if (is2t)
  687. rf = 2;
  688. else
  689. rf = 1;
  690. if (thermalvalue) {
  691. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  692. MASKDWORD) & MASKOFDM_D;
  693. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  694. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  695. ofdm_index_old[0] = (u8) i;
  696. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  697. "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  698. ROFDM0_XATXIQIMBALANCE,
  699. ele_d, ofdm_index_old[0]);
  700. break;
  701. }
  702. }
  703. if (is2t) {
  704. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  705. MASKDWORD) & MASKOFDM_D;
  706. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  707. if (ele_d == (ofdmswing_table[i] &
  708. MASKOFDM_D)) {
  709. ofdm_index_old[1] = (u8) i;
  710. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  711. DBG_LOUD,
  712. "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  713. ROFDM0_XBTXIQIMBALANCE, ele_d,
  714. ofdm_index_old[1]);
  715. break;
  716. }
  717. }
  718. }
  719. temp_cck =
  720. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  721. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  722. if (rtlpriv->dm.cck_inch14) {
  723. if (memcmp((void *)&temp_cck,
  724. (void *)&cckswing_table_ch14[i][2],
  725. 4) == 0) {
  726. cck_index_old = (u8) i;
  727. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  728. DBG_LOUD,
  729. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
  730. RCCK0_TXFILTER2, temp_cck,
  731. cck_index_old,
  732. rtlpriv->dm.cck_inch14);
  733. break;
  734. }
  735. } else {
  736. if (memcmp((void *)&temp_cck,
  737. (void *)
  738. &cckswing_table_ch1ch13[i][2],
  739. 4) == 0) {
  740. cck_index_old = (u8) i;
  741. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  742. DBG_LOUD,
  743. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
  744. RCCK0_TXFILTER2, temp_cck,
  745. cck_index_old,
  746. rtlpriv->dm.cck_inch14);
  747. break;
  748. }
  749. }
  750. }
  751. if (!rtlpriv->dm.thermalvalue) {
  752. rtlpriv->dm.thermalvalue =
  753. rtlefuse->eeprom_thermalmeter;
  754. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  755. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  756. for (i = 0; i < rf; i++)
  757. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  758. rtlpriv->dm.cck_index = cck_index_old;
  759. }
  760. /* Handle USB High PA boards */
  761. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  762. (thermalvalue - rtlpriv->dm.thermalvalue) :
  763. (rtlpriv->dm.thermalvalue - thermalvalue);
  764. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  765. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  766. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  767. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  768. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  769. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  770. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  771. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
  772. thermalvalue, rtlpriv->dm.thermalvalue,
  773. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  774. delta_iqk);
  775. if (delta_lck > 1) {
  776. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  777. rtl92c_phy_lc_calibrate(hw);
  778. }
  779. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  780. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  781. for (i = 0; i < rf; i++)
  782. rtlpriv->dm.ofdm_index[i] -= delta;
  783. rtlpriv->dm.cck_index -= delta;
  784. } else {
  785. for (i = 0; i < rf; i++)
  786. rtlpriv->dm.ofdm_index[i] += delta;
  787. rtlpriv->dm.cck_index += delta;
  788. }
  789. if (is2t) {
  790. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  791. "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  792. rtlpriv->dm.ofdm_index[0],
  793. rtlpriv->dm.ofdm_index[1],
  794. rtlpriv->dm.cck_index);
  795. } else {
  796. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  797. "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
  798. rtlpriv->dm.ofdm_index[0],
  799. rtlpriv->dm.cck_index);
  800. }
  801. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  802. for (i = 0; i < rf; i++)
  803. ofdm_index[i] =
  804. rtlpriv->dm.ofdm_index[i]
  805. + 1;
  806. cck_index = rtlpriv->dm.cck_index + 1;
  807. } else {
  808. for (i = 0; i < rf; i++)
  809. ofdm_index[i] =
  810. rtlpriv->dm.ofdm_index[i];
  811. cck_index = rtlpriv->dm.cck_index;
  812. }
  813. for (i = 0; i < rf; i++) {
  814. if (txpwr_level[i] >= 0 &&
  815. txpwr_level[i] <= 26) {
  816. if (thermalvalue >
  817. rtlefuse->eeprom_thermalmeter) {
  818. if (delta < 5)
  819. ofdm_index[i] -= 1;
  820. else
  821. ofdm_index[i] -= 2;
  822. } else if (delta > 5 && thermalvalue <
  823. rtlefuse->
  824. eeprom_thermalmeter) {
  825. ofdm_index[i] += 1;
  826. }
  827. } else if (txpwr_level[i] >= 27 &&
  828. txpwr_level[i] <= 32
  829. && thermalvalue >
  830. rtlefuse->eeprom_thermalmeter) {
  831. if (delta < 5)
  832. ofdm_index[i] -= 1;
  833. else
  834. ofdm_index[i] -= 2;
  835. } else if (txpwr_level[i] >= 32 &&
  836. txpwr_level[i] <= 38 &&
  837. thermalvalue >
  838. rtlefuse->eeprom_thermalmeter
  839. && delta > 5) {
  840. ofdm_index[i] -= 1;
  841. }
  842. }
  843. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  844. if (thermalvalue >
  845. rtlefuse->eeprom_thermalmeter) {
  846. if (delta < 5)
  847. cck_index -= 1;
  848. else
  849. cck_index -= 2;
  850. } else if (delta > 5 && thermalvalue <
  851. rtlefuse->eeprom_thermalmeter) {
  852. cck_index += 1;
  853. }
  854. } else if (txpwr_level[i] >= 27 &&
  855. txpwr_level[i] <= 32 &&
  856. thermalvalue >
  857. rtlefuse->eeprom_thermalmeter) {
  858. if (delta < 5)
  859. cck_index -= 1;
  860. else
  861. cck_index -= 2;
  862. } else if (txpwr_level[i] >= 32 &&
  863. txpwr_level[i] <= 38 &&
  864. thermalvalue > rtlefuse->eeprom_thermalmeter
  865. && delta > 5) {
  866. cck_index -= 1;
  867. }
  868. for (i = 0; i < rf; i++) {
  869. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  870. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  871. else if (ofdm_index[i] < ofdm_min_index)
  872. ofdm_index[i] = ofdm_min_index;
  873. }
  874. if (cck_index > CCK_TABLE_SIZE - 1)
  875. cck_index = CCK_TABLE_SIZE - 1;
  876. else if (cck_index < 0)
  877. cck_index = 0;
  878. if (is2t) {
  879. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  880. "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  881. ofdm_index[0], ofdm_index[1],
  882. cck_index);
  883. } else {
  884. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  885. "new OFDM_A_index=0x%x, cck_index=0x%x\n",
  886. ofdm_index[0], cck_index);
  887. }
  888. }
  889. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  890. ele_d =
  891. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  892. val_x = rtlphy->reg_e94;
  893. val_y = rtlphy->reg_e9c;
  894. if (val_x != 0) {
  895. if ((val_x & 0x00000200) != 0)
  896. val_x = val_x | 0xFFFFFC00;
  897. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  898. if ((val_y & 0x00000200) != 0)
  899. val_y = val_y | 0xFFFFFC00;
  900. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  901. value32 = (ele_d << 22) |
  902. ((ele_c & 0x3F) << 16) | ele_a;
  903. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  904. MASKDWORD, value32);
  905. value32 = (ele_c & 0x000003C0) >> 6;
  906. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  907. value32);
  908. value32 = ((val_x * ele_d) >> 7) & 0x01;
  909. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  910. BIT(31), value32);
  911. value32 = ((val_y * ele_d) >> 7) & 0x01;
  912. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  913. BIT(29), value32);
  914. } else {
  915. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  916. MASKDWORD,
  917. ofdmswing_table[ofdm_index[0]]);
  918. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  919. 0x00);
  920. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  921. BIT(31) | BIT(29), 0x00);
  922. }
  923. if (!rtlpriv->dm.cck_inch14) {
  924. rtl_write_byte(rtlpriv, 0xa22,
  925. cckswing_table_ch1ch13[cck_index]
  926. [0]);
  927. rtl_write_byte(rtlpriv, 0xa23,
  928. cckswing_table_ch1ch13[cck_index]
  929. [1]);
  930. rtl_write_byte(rtlpriv, 0xa24,
  931. cckswing_table_ch1ch13[cck_index]
  932. [2]);
  933. rtl_write_byte(rtlpriv, 0xa25,
  934. cckswing_table_ch1ch13[cck_index]
  935. [3]);
  936. rtl_write_byte(rtlpriv, 0xa26,
  937. cckswing_table_ch1ch13[cck_index]
  938. [4]);
  939. rtl_write_byte(rtlpriv, 0xa27,
  940. cckswing_table_ch1ch13[cck_index]
  941. [5]);
  942. rtl_write_byte(rtlpriv, 0xa28,
  943. cckswing_table_ch1ch13[cck_index]
  944. [6]);
  945. rtl_write_byte(rtlpriv, 0xa29,
  946. cckswing_table_ch1ch13[cck_index]
  947. [7]);
  948. } else {
  949. rtl_write_byte(rtlpriv, 0xa22,
  950. cckswing_table_ch14[cck_index]
  951. [0]);
  952. rtl_write_byte(rtlpriv, 0xa23,
  953. cckswing_table_ch14[cck_index]
  954. [1]);
  955. rtl_write_byte(rtlpriv, 0xa24,
  956. cckswing_table_ch14[cck_index]
  957. [2]);
  958. rtl_write_byte(rtlpriv, 0xa25,
  959. cckswing_table_ch14[cck_index]
  960. [3]);
  961. rtl_write_byte(rtlpriv, 0xa26,
  962. cckswing_table_ch14[cck_index]
  963. [4]);
  964. rtl_write_byte(rtlpriv, 0xa27,
  965. cckswing_table_ch14[cck_index]
  966. [5]);
  967. rtl_write_byte(rtlpriv, 0xa28,
  968. cckswing_table_ch14[cck_index]
  969. [6]);
  970. rtl_write_byte(rtlpriv, 0xa29,
  971. cckswing_table_ch14[cck_index]
  972. [7]);
  973. }
  974. if (is2t) {
  975. ele_d = (ofdmswing_table[ofdm_index[1]] &
  976. 0xFFC00000) >> 22;
  977. val_x = rtlphy->reg_eb4;
  978. val_y = rtlphy->reg_ebc;
  979. if (val_x != 0) {
  980. if ((val_x & 0x00000200) != 0)
  981. val_x = val_x | 0xFFFFFC00;
  982. ele_a = ((val_x * ele_d) >> 8) &
  983. 0x000003FF;
  984. if ((val_y & 0x00000200) != 0)
  985. val_y = val_y | 0xFFFFFC00;
  986. ele_c = ((val_y * ele_d) >> 8) &
  987. 0x00003FF;
  988. value32 = (ele_d << 22) |
  989. ((ele_c & 0x3F) << 16) | ele_a;
  990. rtl_set_bbreg(hw,
  991. ROFDM0_XBTXIQIMBALANCE,
  992. MASKDWORD, value32);
  993. value32 = (ele_c & 0x000003C0) >> 6;
  994. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  995. MASKH4BITS, value32);
  996. value32 = ((val_x * ele_d) >> 7) & 0x01;
  997. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  998. BIT(27), value32);
  999. value32 = ((val_y * ele_d) >> 7) & 0x01;
  1000. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  1001. BIT(25), value32);
  1002. } else {
  1003. rtl_set_bbreg(hw,
  1004. ROFDM0_XBTXIQIMBALANCE,
  1005. MASKDWORD,
  1006. ofdmswing_table[ofdm_index
  1007. [1]]);
  1008. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  1009. MASKH4BITS, 0x00);
  1010. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  1011. BIT(27) | BIT(25), 0x00);
  1012. }
  1013. }
  1014. }
  1015. if (delta_iqk > 3) {
  1016. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  1017. rtl92c_phy_iq_calibrate(hw, false);
  1018. }
  1019. if (rtlpriv->dm.txpower_track_control)
  1020. rtlpriv->dm.thermalvalue = thermalvalue;
  1021. }
  1022. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
  1023. }
  1024. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  1025. struct ieee80211_hw *hw)
  1026. {
  1027. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1028. rtlpriv->dm.txpower_tracking = true;
  1029. rtlpriv->dm.txpower_trackinginit = false;
  1030. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1031. "pMgntInfo->txpower_tracking = %d\n",
  1032. rtlpriv->dm.txpower_tracking);
  1033. }
  1034. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  1035. {
  1036. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  1037. }
  1038. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  1039. {
  1040. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  1041. }
  1042. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  1043. struct ieee80211_hw *hw)
  1044. {
  1045. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1046. static u8 tm_trigger;
  1047. if (!rtlpriv->dm.txpower_tracking)
  1048. return;
  1049. if (!tm_trigger) {
  1050. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  1051. 0x60);
  1052. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1053. "Trigger 92S Thermal Meter!!\n");
  1054. tm_trigger = 1;
  1055. return;
  1056. } else {
  1057. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  1058. "Schedule TxPowerTracking direct call!!\n");
  1059. rtl92c_dm_txpower_tracking_directcall(hw);
  1060. tm_trigger = 0;
  1061. }
  1062. }
  1063. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  1064. {
  1065. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  1066. }
  1067. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  1068. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  1069. {
  1070. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1071. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  1072. p_ra->ratr_state = DM_RATR_STA_INIT;
  1073. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  1074. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  1075. rtlpriv->dm.useramask = true;
  1076. else
  1077. rtlpriv->dm.useramask = false;
  1078. }
  1079. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  1080. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1081. {
  1082. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1083. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1084. dm_pstable->pre_ccastate = CCA_MAX;
  1085. dm_pstable->cur_ccasate = CCA_MAX;
  1086. dm_pstable->pre_rfstate = RF_MAX;
  1087. dm_pstable->cur_rfstate = RF_MAX;
  1088. dm_pstable->rssi_val_min = 0;
  1089. }
  1090. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1091. {
  1092. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1093. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1094. if (!rtlpriv->reg_init) {
  1095. rtlpriv->reg_874 = (rtl_get_bbreg(hw,
  1096. RFPGA0_XCD_RFINTERFACESW,
  1097. MASKDWORD) & 0x1CC000) >> 14;
  1098. rtlpriv->reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1099. MASKDWORD) & BIT(3)) >> 3;
  1100. rtlpriv->reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1101. MASKDWORD) & 0xFF000000) >> 24;
  1102. rtlpriv->reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) &
  1103. 0xF000) >> 12;
  1104. rtlpriv->reg_init = true;
  1105. }
  1106. if (!bforce_in_normal) {
  1107. if (dm_pstable->rssi_val_min != 0) {
  1108. if (dm_pstable->pre_rfstate == RF_NORMAL) {
  1109. if (dm_pstable->rssi_val_min >= 30)
  1110. dm_pstable->cur_rfstate = RF_SAVE;
  1111. else
  1112. dm_pstable->cur_rfstate = RF_NORMAL;
  1113. } else {
  1114. if (dm_pstable->rssi_val_min <= 25)
  1115. dm_pstable->cur_rfstate = RF_NORMAL;
  1116. else
  1117. dm_pstable->cur_rfstate = RF_SAVE;
  1118. }
  1119. } else {
  1120. dm_pstable->cur_rfstate = RF_MAX;
  1121. }
  1122. } else {
  1123. dm_pstable->cur_rfstate = RF_NORMAL;
  1124. }
  1125. if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
  1126. if (dm_pstable->cur_rfstate == RF_SAVE) {
  1127. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1128. 0x1C0000, 0x2);
  1129. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1130. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1131. 0xFF000000, 0x63);
  1132. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1133. 0xC000, 0x2);
  1134. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1135. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1136. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1137. } else {
  1138. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1139. 0x1CC000, rtlpriv->reg_874);
  1140. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1141. rtlpriv->reg_c70);
  1142. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1143. rtlpriv->reg_85c);
  1144. rtl_set_bbreg(hw, 0xa74, 0xF000, rtlpriv->reg_a74);
  1145. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1146. }
  1147. dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
  1148. }
  1149. }
  1150. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1151. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1152. {
  1153. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1154. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1155. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1156. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1157. /* Determine the minimum RSSI */
  1158. if (((mac->link_state == MAC80211_NOLINK)) &&
  1159. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  1160. dm_pstable->rssi_val_min = 0;
  1161. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
  1162. }
  1163. if (mac->link_state == MAC80211_LINKED) {
  1164. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1165. dm_pstable->rssi_val_min =
  1166. rtlpriv->dm.entry_min_undec_sm_pwdb;
  1167. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1168. "AP Client PWDB = 0x%lx\n",
  1169. dm_pstable->rssi_val_min);
  1170. } else {
  1171. dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
  1172. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1173. "STA Default Port PWDB = 0x%lx\n",
  1174. dm_pstable->rssi_val_min);
  1175. }
  1176. } else {
  1177. dm_pstable->rssi_val_min =
  1178. rtlpriv->dm.entry_min_undec_sm_pwdb;
  1179. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1180. "AP Ext Port PWDB = 0x%lx\n",
  1181. dm_pstable->rssi_val_min);
  1182. }
  1183. /* Power Saving for 92C */
  1184. if (IS_92C_SERIAL(rtlhal->version))
  1185. ;/* rtl92c_dm_1r_cca(hw); */
  1186. else
  1187. rtl92c_dm_rf_saving(hw, false);
  1188. }
  1189. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1190. {
  1191. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1192. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1193. rtlpriv->dm.dm_flag = DYNAMIC_FUNC_DISABLE | DYNAMIC_FUNC_DIG;
  1194. rtlpriv->dm.undec_sm_pwdb = -1;
  1195. rtlpriv->dm.undec_sm_cck = -1;
  1196. rtlpriv->dm.dm_initialgain_enable = true;
  1197. rtl92c_dm_diginit(hw);
  1198. rtlpriv->dm.dm_flag |= HAL_DM_HIPWR_DISABLE;
  1199. rtl92c_dm_init_dynamic_txpower(hw);
  1200. rtl92c_dm_init_edca_turbo(hw);
  1201. rtl92c_dm_init_rate_adaptive_mask(hw);
  1202. rtlpriv->dm.dm_flag |= DYNAMIC_FUNC_SS;
  1203. rtl92c_dm_initialize_txpower_tracking(hw);
  1204. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1205. rtlpriv->dm.ofdm_pkt_cnt = 0;
  1206. rtlpriv->dm.dm_rssi_sel = RSSI_DEFAULT;
  1207. }
  1208. EXPORT_SYMBOL(rtl92c_dm_init);
  1209. void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  1210. {
  1211. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1212. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1213. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1214. long undec_sm_pwdb;
  1215. if (!rtlpriv->dm.dynamic_txpower_enable)
  1216. return;
  1217. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  1218. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1219. return;
  1220. }
  1221. if ((mac->link_state < MAC80211_LINKED) &&
  1222. (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
  1223. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1224. "Not connected to any\n");
  1225. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1226. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  1227. return;
  1228. }
  1229. if (mac->link_state >= MAC80211_LINKED) {
  1230. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1231. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1232. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1233. "AP Client PWDB = 0x%lx\n",
  1234. undec_sm_pwdb);
  1235. } else {
  1236. undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
  1237. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1238. "STA Default Port PWDB = 0x%lx\n",
  1239. undec_sm_pwdb);
  1240. }
  1241. } else {
  1242. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1243. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1244. "AP Ext Port PWDB = 0x%lx\n",
  1245. undec_sm_pwdb);
  1246. }
  1247. if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  1248. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL2;
  1249. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1250. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
  1251. } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  1252. (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  1253. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1254. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1255. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
  1256. } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  1257. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1258. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1259. "TXHIGHPWRLEVEL_NORMAL\n");
  1260. }
  1261. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  1262. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1263. "PHY_SetTxPowerLevel8192S() Channel = %d\n",
  1264. rtlphy->current_channel);
  1265. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  1266. if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  1267. TXHIGHPWRLEVEL_NORMAL)
  1268. dm_restorepowerindex(hw);
  1269. else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  1270. TXHIGHPWRLEVEL_LEVEL1)
  1271. dm_writepowerindex(hw, 0x14);
  1272. else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
  1273. TXHIGHPWRLEVEL_LEVEL2)
  1274. dm_writepowerindex(hw, 0x10);
  1275. }
  1276. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  1277. }
  1278. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1279. {
  1280. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1281. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1282. bool fw_current_inpsmode = false;
  1283. bool fw_ps_awake = true;
  1284. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1285. (u8 *) (&fw_current_inpsmode));
  1286. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1287. (u8 *) (&fw_ps_awake));
  1288. if (ppsc->p2p_ps_info.p2p_ps_mode)
  1289. fw_ps_awake = false;
  1290. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1291. fw_ps_awake)
  1292. && (!ppsc->rfchange_inprogress)) {
  1293. rtl92c_dm_pwdb_monitor(hw);
  1294. rtl92c_dm_dig(hw);
  1295. rtl92c_dm_false_alarm_counter_statistics(hw);
  1296. rtl92c_dm_dynamic_bb_powersaving(hw);
  1297. rtl92c_dm_dynamic_txpower(hw);
  1298. rtl92c_dm_check_txpower_tracking(hw);
  1299. /* rtl92c_dm_refresh_rate_adaptive_mask(hw); */
  1300. rtl92c_dm_bt_coexist(hw);
  1301. rtl92c_dm_check_edca_turbo(hw);
  1302. }
  1303. }
  1304. EXPORT_SYMBOL(rtl92c_dm_watchdog);
  1305. u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
  1306. {
  1307. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1308. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1309. long undec_sm_pwdb;
  1310. u8 curr_bt_rssi_state = 0x00;
  1311. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1312. undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
  1313. } else {
  1314. if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
  1315. undec_sm_pwdb = 100;
  1316. else
  1317. undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
  1318. }
  1319. /* Check RSSI to determine HighPower/NormalPower state for
  1320. * BT coexistence. */
  1321. if (undec_sm_pwdb >= 67)
  1322. curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
  1323. else if (undec_sm_pwdb < 62)
  1324. curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
  1325. /* Check RSSI to determine AMPDU setting for BT coexistence. */
  1326. if (undec_sm_pwdb >= 40)
  1327. curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
  1328. else if (undec_sm_pwdb <= 32)
  1329. curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
  1330. /* Marked RSSI state. It will be used to determine BT coexistence
  1331. * setting later. */
  1332. if (undec_sm_pwdb < 35)
  1333. curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
  1334. else
  1335. curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
  1336. /* Check BT state related to BT_Idle in B/G mode. */
  1337. if (undec_sm_pwdb < 15)
  1338. curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
  1339. else
  1340. curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
  1341. if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
  1342. rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
  1343. return true;
  1344. } else {
  1345. return false;
  1346. }
  1347. }
  1348. EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
  1349. static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
  1350. {
  1351. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1352. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1353. u32 polling, ratio_tx, ratio_pri;
  1354. u32 bt_tx, bt_pri;
  1355. u8 bt_state;
  1356. u8 cur_service_type;
  1357. if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
  1358. return false;
  1359. bt_state = rtl_read_byte(rtlpriv, 0x4fd);
  1360. bt_tx = rtl_read_dword(rtlpriv, 0x488);
  1361. bt_tx = bt_tx & 0x00ffffff;
  1362. bt_pri = rtl_read_dword(rtlpriv, 0x48c);
  1363. bt_pri = bt_pri & 0x00ffffff;
  1364. polling = rtl_read_dword(rtlpriv, 0x490);
  1365. if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
  1366. polling == 0xffffffff && bt_state == 0xff)
  1367. return false;
  1368. bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
  1369. if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
  1370. rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
  1371. if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1372. rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
  1373. bt_state = bt_state |
  1374. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1375. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1376. BIT_OFFSET_LEN_MASK_32(2, 1);
  1377. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1378. }
  1379. return true;
  1380. }
  1381. ratio_tx = bt_tx * 1000 / polling;
  1382. ratio_pri = bt_pri * 1000 / polling;
  1383. rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
  1384. rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
  1385. if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1386. if ((ratio_tx < 30) && (ratio_pri < 30))
  1387. cur_service_type = BT_IDLE;
  1388. else if ((ratio_pri > 110) && (ratio_pri < 250))
  1389. cur_service_type = BT_SCO;
  1390. else if ((ratio_tx >= 200) && (ratio_pri >= 200))
  1391. cur_service_type = BT_BUSY;
  1392. else if ((ratio_tx >= 350) && (ratio_tx < 500))
  1393. cur_service_type = BT_OTHERBUSY;
  1394. else if (ratio_tx >= 500)
  1395. cur_service_type = BT_PAN;
  1396. else
  1397. cur_service_type = BT_OTHER_ACTION;
  1398. if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
  1399. rtlpcipriv->bt_coexist.bt_service = cur_service_type;
  1400. bt_state = bt_state |
  1401. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1402. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1403. ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
  1404. 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
  1405. /* Add interrupt migration when bt is not ini
  1406. * idle state (no traffic). */
  1407. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1408. rtl_write_word(rtlpriv, 0x504, 0x0ccc);
  1409. rtl_write_byte(rtlpriv, 0x506, 0x54);
  1410. rtl_write_byte(rtlpriv, 0x507, 0x54);
  1411. } else {
  1412. rtl_write_byte(rtlpriv, 0x506, 0x00);
  1413. rtl_write_byte(rtlpriv, 0x507, 0x00);
  1414. }
  1415. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1416. return true;
  1417. }
  1418. }
  1419. return false;
  1420. }
  1421. static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
  1422. {
  1423. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1424. static bool media_connect;
  1425. if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1426. media_connect = false;
  1427. } else {
  1428. if (!media_connect) {
  1429. media_connect = true;
  1430. return true;
  1431. }
  1432. media_connect = true;
  1433. }
  1434. return false;
  1435. }
  1436. static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
  1437. {
  1438. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1439. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1440. if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
  1441. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
  1442. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
  1443. } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
  1444. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
  1445. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
  1446. } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
  1447. if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
  1448. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
  1449. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
  1450. } else {
  1451. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
  1452. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
  1453. }
  1454. } else {
  1455. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1456. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1457. }
  1458. if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
  1459. (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
  1460. (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
  1461. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1462. BT_RSSI_STATE_BG_EDCA_LOW)) {
  1463. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
  1464. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
  1465. }
  1466. }
  1467. static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw, u8 tmp1byte)
  1468. {
  1469. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1470. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1471. /* Only enable HW BT coexist when BT in "Busy" state. */
  1472. if (rtlpriv->mac80211.vendor == PEER_CISCO &&
  1473. rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
  1474. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1475. } else {
  1476. if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
  1477. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1478. BT_RSSI_STATE_NORMAL_POWER)) {
  1479. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1480. } else if ((rtlpcipriv->bt_coexist.bt_service ==
  1481. BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
  1482. WIRELESS_MODE_N_24G) &&
  1483. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1484. BT_RSSI_STATE_SPECIAL_LOW)) {
  1485. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1486. } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
  1487. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1488. } else {
  1489. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1490. }
  1491. }
  1492. if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
  1493. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
  1494. else
  1495. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
  1496. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1497. BT_RSSI_STATE_NORMAL_POWER) {
  1498. rtl92c_bt_set_normal(hw);
  1499. } else {
  1500. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1501. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1502. }
  1503. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1504. rtlpriv->cfg->ops->set_rfreg(hw,
  1505. RF90_PATH_A,
  1506. 0x1e,
  1507. 0xf0, 0xf);
  1508. } else {
  1509. rtlpriv->cfg->ops->set_rfreg(hw,
  1510. RF90_PATH_A, 0x1e, 0xf0,
  1511. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1512. }
  1513. if (!rtlpriv->dm.dynamic_txpower_enable) {
  1514. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1515. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1516. BT_RSSI_STATE_TXPOWER_LOW) {
  1517. rtlpriv->dm.dynamic_txhighpower_lvl =
  1518. TXHIGHPWRLEVEL_BT2;
  1519. } else {
  1520. rtlpriv->dm.dynamic_txhighpower_lvl =
  1521. TXHIGHPWRLEVEL_BT1;
  1522. }
  1523. } else {
  1524. rtlpriv->dm.dynamic_txhighpower_lvl =
  1525. TXHIGHPWRLEVEL_NORMAL;
  1526. }
  1527. rtl92c_phy_set_txpower_level(hw,
  1528. rtlpriv->phy.current_channel);
  1529. }
  1530. }
  1531. static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
  1532. {
  1533. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1534. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1535. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1536. u8 tmp1byte = 0;
  1537. if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version) &&
  1538. rtlpcipriv->bt_coexist.bt_coexistence)
  1539. tmp1byte |= BIT(5);
  1540. if (rtlpcipriv->bt_coexist.bt_cur_state) {
  1541. if (rtlpcipriv->bt_coexist.bt_ant_isolation)
  1542. rtl92c_bt_ant_isolation(hw, tmp1byte);
  1543. } else {
  1544. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, tmp1byte);
  1545. rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
  1546. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1547. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1548. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1549. }
  1550. }
  1551. void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
  1552. {
  1553. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1554. bool wifi_connect_change;
  1555. bool bt_state_change;
  1556. bool rssi_state_change;
  1557. if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
  1558. (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
  1559. wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
  1560. bt_state_change = rtl92c_bt_state_change(hw);
  1561. rssi_state_change = rtl92c_bt_rssi_state_change(hw);
  1562. if (wifi_connect_change || bt_state_change || rssi_state_change)
  1563. rtl92c_check_bt_change(hw);
  1564. }
  1565. }
  1566. EXPORT_SYMBOL(rtl92c_dm_bt_coexist);