at803x.c 6.1 KB

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  1. /*
  2. * drivers/net/phy/at803x.c
  3. *
  4. * Driver for Atheros 803x PHY
  5. *
  6. * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/phy.h>
  14. #include <linux/module.h>
  15. #include <linux/string.h>
  16. #include <linux/netdevice.h>
  17. #include <linux/etherdevice.h>
  18. #define AT803X_INTR_ENABLE 0x12
  19. #define AT803X_INTR_STATUS 0x13
  20. #define AT803X_WOL_ENABLE 0x01
  21. #define AT803X_DEVICE_ADDR 0x03
  22. #define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
  23. #define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
  24. #define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
  25. #define AT803X_MMD_ACCESS_CONTROL 0x0D
  26. #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
  27. #define AT803X_FUNC_DATA 0x4003
  28. #define AT803X_INER 0x0012
  29. #define AT803X_INER_INIT 0xec00
  30. #define AT803X_INSR 0x0013
  31. #define AT803X_DEBUG_ADDR 0x1D
  32. #define AT803X_DEBUG_DATA 0x1E
  33. #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
  34. #define AT803X_DEBUG_RGMII_TX_CLK_DLY BIT(8)
  35. MODULE_DESCRIPTION("Atheros 803x PHY driver");
  36. MODULE_AUTHOR("Matus Ujhelyi");
  37. MODULE_LICENSE("GPL");
  38. static int at803x_set_wol(struct phy_device *phydev,
  39. struct ethtool_wolinfo *wol)
  40. {
  41. struct net_device *ndev = phydev->attached_dev;
  42. const u8 *mac;
  43. int ret;
  44. u32 value;
  45. unsigned int i, offsets[] = {
  46. AT803X_LOC_MAC_ADDR_32_47_OFFSET,
  47. AT803X_LOC_MAC_ADDR_16_31_OFFSET,
  48. AT803X_LOC_MAC_ADDR_0_15_OFFSET,
  49. };
  50. if (!ndev)
  51. return -ENODEV;
  52. if (wol->wolopts & WAKE_MAGIC) {
  53. mac = (const u8 *) ndev->dev_addr;
  54. if (!is_valid_ether_addr(mac))
  55. return -EFAULT;
  56. for (i = 0; i < 3; i++) {
  57. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
  58. AT803X_DEVICE_ADDR);
  59. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
  60. offsets[i]);
  61. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL,
  62. AT803X_FUNC_DATA);
  63. phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA,
  64. mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
  65. }
  66. value = phy_read(phydev, AT803X_INTR_ENABLE);
  67. value |= AT803X_WOL_ENABLE;
  68. ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
  69. if (ret)
  70. return ret;
  71. value = phy_read(phydev, AT803X_INTR_STATUS);
  72. } else {
  73. value = phy_read(phydev, AT803X_INTR_ENABLE);
  74. value &= (~AT803X_WOL_ENABLE);
  75. ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
  76. if (ret)
  77. return ret;
  78. value = phy_read(phydev, AT803X_INTR_STATUS);
  79. }
  80. return ret;
  81. }
  82. static void at803x_get_wol(struct phy_device *phydev,
  83. struct ethtool_wolinfo *wol)
  84. {
  85. u32 value;
  86. wol->supported = WAKE_MAGIC;
  87. wol->wolopts = 0;
  88. value = phy_read(phydev, AT803X_INTR_ENABLE);
  89. if (value & AT803X_WOL_ENABLE)
  90. wol->wolopts |= WAKE_MAGIC;
  91. }
  92. static int at803x_suspend(struct phy_device *phydev)
  93. {
  94. int value;
  95. int wol_enabled;
  96. mutex_lock(&phydev->lock);
  97. value = phy_read(phydev, AT803X_INTR_ENABLE);
  98. wol_enabled = value & AT803X_WOL_ENABLE;
  99. value = phy_read(phydev, MII_BMCR);
  100. if (wol_enabled)
  101. value |= BMCR_ISOLATE;
  102. else
  103. value |= BMCR_PDOWN;
  104. phy_write(phydev, MII_BMCR, value);
  105. mutex_unlock(&phydev->lock);
  106. return 0;
  107. }
  108. static int at803x_resume(struct phy_device *phydev)
  109. {
  110. int value;
  111. mutex_lock(&phydev->lock);
  112. value = phy_read(phydev, MII_BMCR);
  113. value &= ~(BMCR_PDOWN | BMCR_ISOLATE);
  114. phy_write(phydev, MII_BMCR, value);
  115. mutex_unlock(&phydev->lock);
  116. return 0;
  117. }
  118. static int at803x_config_init(struct phy_device *phydev)
  119. {
  120. int ret;
  121. ret = genphy_config_init(phydev);
  122. if (ret < 0)
  123. return ret;
  124. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  125. ret = phy_write(phydev, AT803X_DEBUG_ADDR,
  126. AT803X_DEBUG_SYSTEM_MODE_CTRL);
  127. if (ret)
  128. return ret;
  129. ret = phy_write(phydev, AT803X_DEBUG_DATA,
  130. AT803X_DEBUG_RGMII_TX_CLK_DLY);
  131. if (ret)
  132. return ret;
  133. }
  134. return 0;
  135. }
  136. static int at803x_ack_interrupt(struct phy_device *phydev)
  137. {
  138. int err;
  139. err = phy_read(phydev, AT803X_INSR);
  140. return (err < 0) ? err : 0;
  141. }
  142. static int at803x_config_intr(struct phy_device *phydev)
  143. {
  144. int err;
  145. int value;
  146. value = phy_read(phydev, AT803X_INER);
  147. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  148. err = phy_write(phydev, AT803X_INER,
  149. value | AT803X_INER_INIT);
  150. else
  151. err = phy_write(phydev, AT803X_INER, 0);
  152. return err;
  153. }
  154. static struct phy_driver at803x_driver[] = {
  155. {
  156. /* ATHEROS 8035 */
  157. .phy_id = 0x004dd072,
  158. .name = "Atheros 8035 ethernet",
  159. .phy_id_mask = 0xffffffef,
  160. .config_init = at803x_config_init,
  161. .set_wol = at803x_set_wol,
  162. .get_wol = at803x_get_wol,
  163. .suspend = at803x_suspend,
  164. .resume = at803x_resume,
  165. .features = PHY_GBIT_FEATURES,
  166. .flags = PHY_HAS_INTERRUPT,
  167. .config_aneg = genphy_config_aneg,
  168. .read_status = genphy_read_status,
  169. .driver = {
  170. .owner = THIS_MODULE,
  171. },
  172. }, {
  173. /* ATHEROS 8030 */
  174. .phy_id = 0x004dd076,
  175. .name = "Atheros 8030 ethernet",
  176. .phy_id_mask = 0xffffffef,
  177. .config_init = at803x_config_init,
  178. .set_wol = at803x_set_wol,
  179. .get_wol = at803x_get_wol,
  180. .suspend = at803x_suspend,
  181. .resume = at803x_resume,
  182. .features = PHY_GBIT_FEATURES,
  183. .flags = PHY_HAS_INTERRUPT,
  184. .config_aneg = genphy_config_aneg,
  185. .read_status = genphy_read_status,
  186. .driver = {
  187. .owner = THIS_MODULE,
  188. },
  189. }, {
  190. /* ATHEROS 8031 */
  191. .phy_id = 0x004dd074,
  192. .name = "Atheros 8031 ethernet",
  193. .phy_id_mask = 0xffffffef,
  194. .config_init = at803x_config_init,
  195. .set_wol = at803x_set_wol,
  196. .get_wol = at803x_get_wol,
  197. .suspend = at803x_suspend,
  198. .resume = at803x_resume,
  199. .features = PHY_GBIT_FEATURES,
  200. .flags = PHY_HAS_INTERRUPT,
  201. .config_aneg = genphy_config_aneg,
  202. .read_status = genphy_read_status,
  203. .ack_interrupt = &at803x_ack_interrupt,
  204. .config_intr = &at803x_config_intr,
  205. .driver = {
  206. .owner = THIS_MODULE,
  207. },
  208. } };
  209. static int __init atheros_init(void)
  210. {
  211. return phy_drivers_register(at803x_driver,
  212. ARRAY_SIZE(at803x_driver));
  213. }
  214. static void __exit atheros_exit(void)
  215. {
  216. phy_drivers_unregister(at803x_driver, ARRAY_SIZE(at803x_driver));
  217. }
  218. module_init(atheros_init);
  219. module_exit(atheros_exit);
  220. static struct mdio_device_id __maybe_unused atheros_tbl[] = {
  221. { 0x004dd076, 0xffffffef },
  222. { 0x004dd074, 0xffffffef },
  223. { 0x004dd072, 0xffffffef },
  224. { }
  225. };
  226. MODULE_DEVICE_TABLE(mdio, atheros_tbl);