netxen_nic_init.c 46 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * Copyright (C) 2009 - QLogic Corporation.
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. * The full GNU General Public License is included in this distribution
  20. * in the file called "COPYING".
  21. *
  22. */
  23. #include <linux/netdevice.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/if_vlan.h>
  27. #include <net/checksum.h>
  28. #include "netxen_nic.h"
  29. #include "netxen_nic_hw.h"
  30. struct crb_addr_pair {
  31. u32 addr;
  32. u32 data;
  33. };
  34. #define NETXEN_MAX_CRB_XFORM 60
  35. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  36. #define NETXEN_ADDR_ERROR (0xffffffff)
  37. #define crb_addr_transform(name) \
  38. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  39. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  40. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  41. static void
  42. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  43. struct nx_host_rds_ring *rds_ring);
  44. static int netxen_p3_has_mn(struct netxen_adapter *adapter);
  45. static void crb_addr_transform_setup(void)
  46. {
  47. crb_addr_transform(XDMA);
  48. crb_addr_transform(TIMR);
  49. crb_addr_transform(SRE);
  50. crb_addr_transform(SQN3);
  51. crb_addr_transform(SQN2);
  52. crb_addr_transform(SQN1);
  53. crb_addr_transform(SQN0);
  54. crb_addr_transform(SQS3);
  55. crb_addr_transform(SQS2);
  56. crb_addr_transform(SQS1);
  57. crb_addr_transform(SQS0);
  58. crb_addr_transform(RPMX7);
  59. crb_addr_transform(RPMX6);
  60. crb_addr_transform(RPMX5);
  61. crb_addr_transform(RPMX4);
  62. crb_addr_transform(RPMX3);
  63. crb_addr_transform(RPMX2);
  64. crb_addr_transform(RPMX1);
  65. crb_addr_transform(RPMX0);
  66. crb_addr_transform(ROMUSB);
  67. crb_addr_transform(SN);
  68. crb_addr_transform(QMN);
  69. crb_addr_transform(QMS);
  70. crb_addr_transform(PGNI);
  71. crb_addr_transform(PGND);
  72. crb_addr_transform(PGN3);
  73. crb_addr_transform(PGN2);
  74. crb_addr_transform(PGN1);
  75. crb_addr_transform(PGN0);
  76. crb_addr_transform(PGSI);
  77. crb_addr_transform(PGSD);
  78. crb_addr_transform(PGS3);
  79. crb_addr_transform(PGS2);
  80. crb_addr_transform(PGS1);
  81. crb_addr_transform(PGS0);
  82. crb_addr_transform(PS);
  83. crb_addr_transform(PH);
  84. crb_addr_transform(NIU);
  85. crb_addr_transform(I2Q);
  86. crb_addr_transform(EG);
  87. crb_addr_transform(MN);
  88. crb_addr_transform(MS);
  89. crb_addr_transform(CAS2);
  90. crb_addr_transform(CAS1);
  91. crb_addr_transform(CAS0);
  92. crb_addr_transform(CAM);
  93. crb_addr_transform(C2C1);
  94. crb_addr_transform(C2C0);
  95. crb_addr_transform(SMB);
  96. crb_addr_transform(OCM0);
  97. crb_addr_transform(I2C0);
  98. }
  99. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  100. {
  101. struct netxen_recv_context *recv_ctx;
  102. struct nx_host_rds_ring *rds_ring;
  103. struct netxen_rx_buffer *rx_buf;
  104. int i, ring;
  105. recv_ctx = &adapter->recv_ctx;
  106. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  107. rds_ring = &recv_ctx->rds_rings[ring];
  108. for (i = 0; i < rds_ring->num_desc; ++i) {
  109. rx_buf = &(rds_ring->rx_buf_arr[i]);
  110. if (rx_buf->state == NETXEN_BUFFER_FREE)
  111. continue;
  112. pci_unmap_single(adapter->pdev,
  113. rx_buf->dma,
  114. rds_ring->dma_size,
  115. PCI_DMA_FROMDEVICE);
  116. if (rx_buf->skb != NULL)
  117. dev_kfree_skb_any(rx_buf->skb);
  118. }
  119. }
  120. }
  121. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  122. {
  123. struct netxen_cmd_buffer *cmd_buf;
  124. struct netxen_skb_frag *buffrag;
  125. int i, j;
  126. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  127. cmd_buf = tx_ring->cmd_buf_arr;
  128. for (i = 0; i < tx_ring->num_desc; i++) {
  129. buffrag = cmd_buf->frag_array;
  130. if (buffrag->dma) {
  131. pci_unmap_single(adapter->pdev, buffrag->dma,
  132. buffrag->length, PCI_DMA_TODEVICE);
  133. buffrag->dma = 0ULL;
  134. }
  135. for (j = 1; j < cmd_buf->frag_count; j++) {
  136. buffrag++;
  137. if (buffrag->dma) {
  138. pci_unmap_page(adapter->pdev, buffrag->dma,
  139. buffrag->length,
  140. PCI_DMA_TODEVICE);
  141. buffrag->dma = 0ULL;
  142. }
  143. }
  144. if (cmd_buf->skb) {
  145. dev_kfree_skb_any(cmd_buf->skb);
  146. cmd_buf->skb = NULL;
  147. }
  148. cmd_buf++;
  149. }
  150. }
  151. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  152. {
  153. struct netxen_recv_context *recv_ctx;
  154. struct nx_host_rds_ring *rds_ring;
  155. struct nx_host_tx_ring *tx_ring;
  156. int ring;
  157. recv_ctx = &adapter->recv_ctx;
  158. if (recv_ctx->rds_rings == NULL)
  159. goto skip_rds;
  160. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  161. rds_ring = &recv_ctx->rds_rings[ring];
  162. vfree(rds_ring->rx_buf_arr);
  163. rds_ring->rx_buf_arr = NULL;
  164. }
  165. kfree(recv_ctx->rds_rings);
  166. skip_rds:
  167. if (adapter->tx_ring == NULL)
  168. return;
  169. tx_ring = adapter->tx_ring;
  170. vfree(tx_ring->cmd_buf_arr);
  171. kfree(tx_ring);
  172. adapter->tx_ring = NULL;
  173. }
  174. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  175. {
  176. struct netxen_recv_context *recv_ctx;
  177. struct nx_host_rds_ring *rds_ring;
  178. struct nx_host_sds_ring *sds_ring;
  179. struct nx_host_tx_ring *tx_ring;
  180. struct netxen_rx_buffer *rx_buf;
  181. int ring, i;
  182. struct netxen_cmd_buffer *cmd_buf_arr;
  183. struct net_device *netdev = adapter->netdev;
  184. tx_ring = kzalloc(sizeof(struct nx_host_tx_ring), GFP_KERNEL);
  185. if (tx_ring == NULL)
  186. return -ENOMEM;
  187. adapter->tx_ring = tx_ring;
  188. tx_ring->num_desc = adapter->num_txd;
  189. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  190. cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
  191. if (cmd_buf_arr == NULL)
  192. goto err_out;
  193. tx_ring->cmd_buf_arr = cmd_buf_arr;
  194. recv_ctx = &adapter->recv_ctx;
  195. rds_ring = kcalloc(adapter->max_rds_rings,
  196. sizeof(struct nx_host_rds_ring), GFP_KERNEL);
  197. if (rds_ring == NULL)
  198. goto err_out;
  199. recv_ctx->rds_rings = rds_ring;
  200. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  201. rds_ring = &recv_ctx->rds_rings[ring];
  202. switch (ring) {
  203. case RCV_RING_NORMAL:
  204. rds_ring->num_desc = adapter->num_rxd;
  205. if (adapter->ahw.cut_through) {
  206. rds_ring->dma_size =
  207. NX_CT_DEFAULT_RX_BUF_LEN;
  208. rds_ring->skb_size =
  209. NX_CT_DEFAULT_RX_BUF_LEN;
  210. } else {
  211. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  212. rds_ring->dma_size =
  213. NX_P3_RX_BUF_MAX_LEN;
  214. else
  215. rds_ring->dma_size =
  216. NX_P2_RX_BUF_MAX_LEN;
  217. rds_ring->skb_size =
  218. rds_ring->dma_size + NET_IP_ALIGN;
  219. }
  220. break;
  221. case RCV_RING_JUMBO:
  222. rds_ring->num_desc = adapter->num_jumbo_rxd;
  223. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  224. rds_ring->dma_size =
  225. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  226. else
  227. rds_ring->dma_size =
  228. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  229. if (adapter->capabilities & NX_CAP0_HW_LRO)
  230. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  231. rds_ring->skb_size =
  232. rds_ring->dma_size + NET_IP_ALIGN;
  233. break;
  234. case RCV_RING_LRO:
  235. rds_ring->num_desc = adapter->num_lro_rxd;
  236. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  237. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  238. break;
  239. }
  240. rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
  241. if (rds_ring->rx_buf_arr == NULL)
  242. /* free whatever was already allocated */
  243. goto err_out;
  244. INIT_LIST_HEAD(&rds_ring->free_list);
  245. /*
  246. * Now go through all of them, set reference handles
  247. * and put them in the queues.
  248. */
  249. rx_buf = rds_ring->rx_buf_arr;
  250. for (i = 0; i < rds_ring->num_desc; i++) {
  251. list_add_tail(&rx_buf->list,
  252. &rds_ring->free_list);
  253. rx_buf->ref_handle = i;
  254. rx_buf->state = NETXEN_BUFFER_FREE;
  255. rx_buf++;
  256. }
  257. spin_lock_init(&rds_ring->lock);
  258. }
  259. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  260. sds_ring = &recv_ctx->sds_rings[ring];
  261. sds_ring->irq = adapter->msix_entries[ring].vector;
  262. sds_ring->adapter = adapter;
  263. sds_ring->num_desc = adapter->num_rxd;
  264. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  265. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  266. }
  267. return 0;
  268. err_out:
  269. netxen_free_sw_resources(adapter);
  270. return -ENOMEM;
  271. }
  272. /*
  273. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  274. * address to external PCI CRB address.
  275. */
  276. static u32 netxen_decode_crb_addr(u32 addr)
  277. {
  278. int i;
  279. u32 base_addr, offset, pci_base;
  280. crb_addr_transform_setup();
  281. pci_base = NETXEN_ADDR_ERROR;
  282. base_addr = addr & 0xfff00000;
  283. offset = addr & 0x000fffff;
  284. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  285. if (crb_addr_xform[i] == base_addr) {
  286. pci_base = i << 20;
  287. break;
  288. }
  289. }
  290. if (pci_base == NETXEN_ADDR_ERROR)
  291. return pci_base;
  292. else
  293. return pci_base + offset;
  294. }
  295. #define NETXEN_MAX_ROM_WAIT_USEC 100
  296. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  297. {
  298. long timeout = 0;
  299. long done = 0;
  300. cond_resched();
  301. while (done == 0) {
  302. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  303. done &= 2;
  304. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  305. dev_err(&adapter->pdev->dev,
  306. "Timeout reached waiting for rom done");
  307. return -EIO;
  308. }
  309. udelay(1);
  310. }
  311. return 0;
  312. }
  313. static int do_rom_fast_read(struct netxen_adapter *adapter,
  314. int addr, int *valp)
  315. {
  316. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  317. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  318. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  319. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  320. if (netxen_wait_rom_done(adapter)) {
  321. printk("Error waiting for rom done\n");
  322. return -EIO;
  323. }
  324. /* reset abyte_cnt and dummy_byte_cnt */
  325. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  326. udelay(10);
  327. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  328. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  329. return 0;
  330. }
  331. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  332. u8 *bytes, size_t size)
  333. {
  334. int addridx;
  335. int ret = 0;
  336. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  337. int v;
  338. ret = do_rom_fast_read(adapter, addridx, &v);
  339. if (ret != 0)
  340. break;
  341. *(__le32 *)bytes = cpu_to_le32(v);
  342. bytes += 4;
  343. }
  344. return ret;
  345. }
  346. int
  347. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  348. u8 *bytes, size_t size)
  349. {
  350. int ret;
  351. ret = netxen_rom_lock(adapter);
  352. if (ret < 0)
  353. return ret;
  354. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  355. netxen_rom_unlock(adapter);
  356. return ret;
  357. }
  358. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  359. {
  360. int ret;
  361. if (netxen_rom_lock(adapter) != 0)
  362. return -EIO;
  363. ret = do_rom_fast_read(adapter, addr, valp);
  364. netxen_rom_unlock(adapter);
  365. return ret;
  366. }
  367. #define NETXEN_BOARDTYPE 0x4008
  368. #define NETXEN_BOARDNUM 0x400c
  369. #define NETXEN_CHIPNUM 0x4010
  370. int netxen_pinit_from_rom(struct netxen_adapter *adapter)
  371. {
  372. int addr, val;
  373. int i, n, init_delay = 0;
  374. struct crb_addr_pair *buf;
  375. unsigned offset;
  376. u32 off;
  377. /* resetall */
  378. netxen_rom_lock(adapter);
  379. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xfeffffff);
  380. netxen_rom_unlock(adapter);
  381. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  382. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  383. (n != 0xcafecafe) ||
  384. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  385. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  386. "n: %08x\n", netxen_nic_driver_name, n);
  387. return -EIO;
  388. }
  389. offset = n & 0xffffU;
  390. n = (n >> 16) & 0xffffU;
  391. } else {
  392. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  393. !(n & 0x80000000)) {
  394. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  395. "n: %08x\n", netxen_nic_driver_name, n);
  396. return -EIO;
  397. }
  398. offset = 1;
  399. n &= ~0x80000000;
  400. }
  401. if (n >= 1024) {
  402. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  403. " initialized.\n", __func__, n);
  404. return -EIO;
  405. }
  406. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  407. if (buf == NULL)
  408. return -ENOMEM;
  409. for (i = 0; i < n; i++) {
  410. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  411. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  412. kfree(buf);
  413. return -EIO;
  414. }
  415. buf[i].addr = addr;
  416. buf[i].data = val;
  417. }
  418. for (i = 0; i < n; i++) {
  419. off = netxen_decode_crb_addr(buf[i].addr);
  420. if (off == NETXEN_ADDR_ERROR) {
  421. printk(KERN_ERR"CRB init value out of range %x\n",
  422. buf[i].addr);
  423. continue;
  424. }
  425. off += NETXEN_PCI_CRBSPACE;
  426. if (off & 1)
  427. continue;
  428. /* skipping cold reboot MAGIC */
  429. if (off == NETXEN_CAM_RAM(0x1fc))
  430. continue;
  431. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  432. if (off == (NETXEN_CRB_I2C0 + 0x1c))
  433. continue;
  434. /* do not reset PCI */
  435. if (off == (ROMUSB_GLB + 0xbc))
  436. continue;
  437. if (off == (ROMUSB_GLB + 0xa8))
  438. continue;
  439. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  440. continue;
  441. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  442. continue;
  443. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  444. continue;
  445. if ((off & 0x0ff00000) == NETXEN_CRB_DDR_NET)
  446. continue;
  447. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18) &&
  448. !NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  449. buf[i].data = 0x1020;
  450. /* skip the function enable register */
  451. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  452. continue;
  453. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  454. continue;
  455. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  456. continue;
  457. }
  458. init_delay = 1;
  459. /* After writing this register, HW needs time for CRB */
  460. /* to quiet down (else crb_window returns 0xffffffff) */
  461. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  462. init_delay = 1000;
  463. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  464. /* hold xdma in reset also */
  465. buf[i].data = NETXEN_NIC_XDMA_RESET;
  466. buf[i].data = 0x8000ff;
  467. }
  468. }
  469. NXWR32(adapter, off, buf[i].data);
  470. msleep(init_delay);
  471. }
  472. kfree(buf);
  473. /* disable_peg_cache_all */
  474. /* unreset_net_cache */
  475. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  476. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  477. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  478. }
  479. /* p2dn replyCount */
  480. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  481. /* disable_peg_cache 0 */
  482. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  483. /* disable_peg_cache 1 */
  484. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  485. /* peg_clr_all */
  486. /* peg_clr 0 */
  487. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  488. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  489. /* peg_clr 1 */
  490. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  491. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  492. /* peg_clr 2 */
  493. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  494. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  495. /* peg_clr 3 */
  496. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  497. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  498. return 0;
  499. }
  500. static struct uni_table_desc *nx_get_table_desc(const u8 *unirom, int section)
  501. {
  502. uint32_t i;
  503. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  504. __le32 entries = cpu_to_le32(directory->num_entries);
  505. for (i = 0; i < entries; i++) {
  506. __le32 offs = cpu_to_le32(directory->findex) +
  507. (i * cpu_to_le32(directory->entry_size));
  508. __le32 tab_type = cpu_to_le32(*((u32 *)&unirom[offs] + 8));
  509. if (tab_type == section)
  510. return (struct uni_table_desc *) &unirom[offs];
  511. }
  512. return NULL;
  513. }
  514. #define QLCNIC_FILEHEADER_SIZE (14 * 4)
  515. static int
  516. netxen_nic_validate_header(struct netxen_adapter *adapter)
  517. {
  518. const u8 *unirom = adapter->fw->data;
  519. struct uni_table_desc *directory = (struct uni_table_desc *) &unirom[0];
  520. u32 fw_file_size = adapter->fw->size;
  521. u32 tab_size;
  522. __le32 entries;
  523. __le32 entry_size;
  524. if (fw_file_size < QLCNIC_FILEHEADER_SIZE)
  525. return -EINVAL;
  526. entries = cpu_to_le32(directory->num_entries);
  527. entry_size = cpu_to_le32(directory->entry_size);
  528. tab_size = cpu_to_le32(directory->findex) + (entries * entry_size);
  529. if (fw_file_size < tab_size)
  530. return -EINVAL;
  531. return 0;
  532. }
  533. static int
  534. netxen_nic_validate_bootld(struct netxen_adapter *adapter)
  535. {
  536. struct uni_table_desc *tab_desc;
  537. struct uni_data_desc *descr;
  538. const u8 *unirom = adapter->fw->data;
  539. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  540. NX_UNI_BOOTLD_IDX_OFF));
  541. u32 offs;
  542. u32 tab_size;
  543. u32 data_size;
  544. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_BOOTLD);
  545. if (!tab_desc)
  546. return -EINVAL;
  547. tab_size = cpu_to_le32(tab_desc->findex) +
  548. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  549. if (adapter->fw->size < tab_size)
  550. return -EINVAL;
  551. offs = cpu_to_le32(tab_desc->findex) +
  552. (cpu_to_le32(tab_desc->entry_size) * (idx));
  553. descr = (struct uni_data_desc *)&unirom[offs];
  554. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  555. if (adapter->fw->size < data_size)
  556. return -EINVAL;
  557. return 0;
  558. }
  559. static int
  560. netxen_nic_validate_fw(struct netxen_adapter *adapter)
  561. {
  562. struct uni_table_desc *tab_desc;
  563. struct uni_data_desc *descr;
  564. const u8 *unirom = adapter->fw->data;
  565. __le32 idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  566. NX_UNI_FIRMWARE_IDX_OFF));
  567. u32 offs;
  568. u32 tab_size;
  569. u32 data_size;
  570. tab_desc = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_FW);
  571. if (!tab_desc)
  572. return -EINVAL;
  573. tab_size = cpu_to_le32(tab_desc->findex) +
  574. (cpu_to_le32(tab_desc->entry_size) * (idx + 1));
  575. if (adapter->fw->size < tab_size)
  576. return -EINVAL;
  577. offs = cpu_to_le32(tab_desc->findex) +
  578. (cpu_to_le32(tab_desc->entry_size) * (idx));
  579. descr = (struct uni_data_desc *)&unirom[offs];
  580. data_size = cpu_to_le32(descr->findex) + cpu_to_le32(descr->size);
  581. if (adapter->fw->size < data_size)
  582. return -EINVAL;
  583. return 0;
  584. }
  585. static int
  586. netxen_nic_validate_product_offs(struct netxen_adapter *adapter)
  587. {
  588. struct uni_table_desc *ptab_descr;
  589. const u8 *unirom = adapter->fw->data;
  590. int mn_present = (NX_IS_REVISION_P2(adapter->ahw.revision_id)) ?
  591. 1 : netxen_p3_has_mn(adapter);
  592. __le32 entries;
  593. __le32 entry_size;
  594. u32 tab_size;
  595. u32 i;
  596. ptab_descr = nx_get_table_desc(unirom, NX_UNI_DIR_SECT_PRODUCT_TBL);
  597. if (ptab_descr == NULL)
  598. return -EINVAL;
  599. entries = cpu_to_le32(ptab_descr->num_entries);
  600. entry_size = cpu_to_le32(ptab_descr->entry_size);
  601. tab_size = cpu_to_le32(ptab_descr->findex) + (entries * entry_size);
  602. if (adapter->fw->size < tab_size)
  603. return -EINVAL;
  604. nomn:
  605. for (i = 0; i < entries; i++) {
  606. __le32 flags, file_chiprev, offs;
  607. u8 chiprev = adapter->ahw.revision_id;
  608. uint32_t flagbit;
  609. offs = cpu_to_le32(ptab_descr->findex) +
  610. (i * cpu_to_le32(ptab_descr->entry_size));
  611. flags = cpu_to_le32(*((int *)&unirom[offs] + NX_UNI_FLAGS_OFF));
  612. file_chiprev = cpu_to_le32(*((int *)&unirom[offs] +
  613. NX_UNI_CHIP_REV_OFF));
  614. flagbit = mn_present ? 1 : 2;
  615. if ((chiprev == file_chiprev) &&
  616. ((1ULL << flagbit) & flags)) {
  617. adapter->file_prd_off = offs;
  618. return 0;
  619. }
  620. }
  621. if (mn_present && NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  622. mn_present = 0;
  623. goto nomn;
  624. }
  625. return -EINVAL;
  626. }
  627. static int
  628. netxen_nic_validate_unified_romimage(struct netxen_adapter *adapter)
  629. {
  630. if (netxen_nic_validate_header(adapter)) {
  631. dev_err(&adapter->pdev->dev,
  632. "unified image: header validation failed\n");
  633. return -EINVAL;
  634. }
  635. if (netxen_nic_validate_product_offs(adapter)) {
  636. dev_err(&adapter->pdev->dev,
  637. "unified image: product validation failed\n");
  638. return -EINVAL;
  639. }
  640. if (netxen_nic_validate_bootld(adapter)) {
  641. dev_err(&adapter->pdev->dev,
  642. "unified image: bootld validation failed\n");
  643. return -EINVAL;
  644. }
  645. if (netxen_nic_validate_fw(adapter)) {
  646. dev_err(&adapter->pdev->dev,
  647. "unified image: firmware validation failed\n");
  648. return -EINVAL;
  649. }
  650. return 0;
  651. }
  652. static struct uni_data_desc *nx_get_data_desc(struct netxen_adapter *adapter,
  653. u32 section, u32 idx_offset)
  654. {
  655. const u8 *unirom = adapter->fw->data;
  656. int idx = cpu_to_le32(*((int *)&unirom[adapter->file_prd_off] +
  657. idx_offset));
  658. struct uni_table_desc *tab_desc;
  659. __le32 offs;
  660. tab_desc = nx_get_table_desc(unirom, section);
  661. if (tab_desc == NULL)
  662. return NULL;
  663. offs = cpu_to_le32(tab_desc->findex) +
  664. (cpu_to_le32(tab_desc->entry_size) * idx);
  665. return (struct uni_data_desc *)&unirom[offs];
  666. }
  667. static u8 *
  668. nx_get_bootld_offs(struct netxen_adapter *adapter)
  669. {
  670. u32 offs = NETXEN_BOOTLD_START;
  671. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  672. offs = cpu_to_le32((nx_get_data_desc(adapter,
  673. NX_UNI_DIR_SECT_BOOTLD,
  674. NX_UNI_BOOTLD_IDX_OFF))->findex);
  675. return (u8 *)&adapter->fw->data[offs];
  676. }
  677. static u8 *
  678. nx_get_fw_offs(struct netxen_adapter *adapter)
  679. {
  680. u32 offs = NETXEN_IMAGE_START;
  681. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  682. offs = cpu_to_le32((nx_get_data_desc(adapter,
  683. NX_UNI_DIR_SECT_FW,
  684. NX_UNI_FIRMWARE_IDX_OFF))->findex);
  685. return (u8 *)&adapter->fw->data[offs];
  686. }
  687. static __le32
  688. nx_get_fw_size(struct netxen_adapter *adapter)
  689. {
  690. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE)
  691. return cpu_to_le32((nx_get_data_desc(adapter,
  692. NX_UNI_DIR_SECT_FW,
  693. NX_UNI_FIRMWARE_IDX_OFF))->size);
  694. else
  695. return cpu_to_le32(
  696. *(u32 *)&adapter->fw->data[NX_FW_SIZE_OFFSET]);
  697. }
  698. static __le32
  699. nx_get_fw_version(struct netxen_adapter *adapter)
  700. {
  701. struct uni_data_desc *fw_data_desc;
  702. const struct firmware *fw = adapter->fw;
  703. __le32 major, minor, sub;
  704. const u8 *ver_str;
  705. int i, ret = 0;
  706. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  707. fw_data_desc = nx_get_data_desc(adapter,
  708. NX_UNI_DIR_SECT_FW, NX_UNI_FIRMWARE_IDX_OFF);
  709. ver_str = fw->data + cpu_to_le32(fw_data_desc->findex) +
  710. cpu_to_le32(fw_data_desc->size) - 17;
  711. for (i = 0; i < 12; i++) {
  712. if (!strncmp(&ver_str[i], "REV=", 4)) {
  713. ret = sscanf(&ver_str[i+4], "%u.%u.%u ",
  714. &major, &minor, &sub);
  715. break;
  716. }
  717. }
  718. if (ret != 3)
  719. return 0;
  720. return major + (minor << 8) + (sub << 16);
  721. } else
  722. return cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  723. }
  724. static __le32
  725. nx_get_bios_version(struct netxen_adapter *adapter)
  726. {
  727. const struct firmware *fw = adapter->fw;
  728. __le32 bios_ver, prd_off = adapter->file_prd_off;
  729. if (adapter->fw_type == NX_UNIFIED_ROMIMAGE) {
  730. bios_ver = cpu_to_le32(*((u32 *) (&fw->data[prd_off])
  731. + NX_UNI_BIOS_VERSION_OFF));
  732. return (bios_ver << 16) + ((bios_ver >> 8) & 0xff00) +
  733. (bios_ver >> 24);
  734. } else
  735. return cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  736. }
  737. int
  738. netxen_need_fw_reset(struct netxen_adapter *adapter)
  739. {
  740. u32 count, old_count;
  741. u32 val, version, major, minor, build;
  742. int i, timeout;
  743. u8 fw_type;
  744. /* NX2031 firmware doesn't support heartbit */
  745. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  746. return 1;
  747. if (adapter->need_fw_reset)
  748. return 1;
  749. /* last attempt had failed */
  750. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  751. return 1;
  752. old_count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  753. for (i = 0; i < 10; i++) {
  754. timeout = msleep_interruptible(200);
  755. if (timeout) {
  756. NXWR32(adapter, CRB_CMDPEG_STATE,
  757. PHAN_INITIALIZE_FAILED);
  758. return -EINTR;
  759. }
  760. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  761. if (count != old_count)
  762. break;
  763. }
  764. /* firmware is dead */
  765. if (count == old_count)
  766. return 1;
  767. /* check if we have got newer or different file firmware */
  768. if (adapter->fw) {
  769. val = nx_get_fw_version(adapter);
  770. version = NETXEN_DECODE_VERSION(val);
  771. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  772. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  773. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  774. if (version > NETXEN_VERSION_CODE(major, minor, build))
  775. return 1;
  776. if (version == NETXEN_VERSION_CODE(major, minor, build) &&
  777. adapter->fw_type != NX_UNIFIED_ROMIMAGE) {
  778. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  779. fw_type = (val & 0x4) ?
  780. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  781. if (adapter->fw_type != fw_type)
  782. return 1;
  783. }
  784. }
  785. return 0;
  786. }
  787. #define NETXEN_MIN_P3_FW_SUPP NETXEN_VERSION_CODE(4, 0, 505)
  788. int
  789. netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter)
  790. {
  791. u32 flash_fw_ver, min_fw_ver;
  792. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  793. return 0;
  794. if (netxen_rom_fast_read(adapter,
  795. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  796. dev_err(&adapter->pdev->dev, "Unable to read flash fw"
  797. "version\n");
  798. return -EIO;
  799. }
  800. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  801. min_fw_ver = NETXEN_MIN_P3_FW_SUPP;
  802. if (flash_fw_ver >= min_fw_ver)
  803. return 0;
  804. dev_info(&adapter->pdev->dev, "Flash fw[%d.%d.%d] is < min fw supported"
  805. "[4.0.505]. Please update firmware on flash\n",
  806. _major(flash_fw_ver), _minor(flash_fw_ver),
  807. _build(flash_fw_ver));
  808. return -EINVAL;
  809. }
  810. static char *fw_name[] = {
  811. NX_P2_MN_ROMIMAGE_NAME,
  812. NX_P3_CT_ROMIMAGE_NAME,
  813. NX_P3_MN_ROMIMAGE_NAME,
  814. NX_UNIFIED_ROMIMAGE_NAME,
  815. NX_FLASH_ROMIMAGE_NAME,
  816. };
  817. int
  818. netxen_load_firmware(struct netxen_adapter *adapter)
  819. {
  820. u64 *ptr64;
  821. u32 i, flashaddr, size;
  822. const struct firmware *fw = adapter->fw;
  823. struct pci_dev *pdev = adapter->pdev;
  824. dev_info(&pdev->dev, "loading firmware from %s\n",
  825. fw_name[adapter->fw_type]);
  826. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  827. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  828. if (fw) {
  829. __le64 data;
  830. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  831. ptr64 = (u64 *)nx_get_bootld_offs(adapter);
  832. flashaddr = NETXEN_BOOTLD_START;
  833. for (i = 0; i < size; i++) {
  834. data = cpu_to_le64(ptr64[i]);
  835. if (adapter->pci_mem_write(adapter, flashaddr, data))
  836. return -EIO;
  837. flashaddr += 8;
  838. }
  839. size = (__force u32)nx_get_fw_size(adapter) / 8;
  840. ptr64 = (u64 *)nx_get_fw_offs(adapter);
  841. flashaddr = NETXEN_IMAGE_START;
  842. for (i = 0; i < size; i++) {
  843. data = cpu_to_le64(ptr64[i]);
  844. if (adapter->pci_mem_write(adapter,
  845. flashaddr, data))
  846. return -EIO;
  847. flashaddr += 8;
  848. }
  849. size = (__force u32)nx_get_fw_size(adapter) % 8;
  850. if (size) {
  851. data = cpu_to_le64(ptr64[i]);
  852. if (adapter->pci_mem_write(adapter,
  853. flashaddr, data))
  854. return -EIO;
  855. }
  856. } else {
  857. u64 data;
  858. u32 hi, lo;
  859. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  860. flashaddr = NETXEN_BOOTLD_START;
  861. for (i = 0; i < size; i++) {
  862. if (netxen_rom_fast_read(adapter,
  863. flashaddr, (int *)&lo) != 0)
  864. return -EIO;
  865. if (netxen_rom_fast_read(adapter,
  866. flashaddr + 4, (int *)&hi) != 0)
  867. return -EIO;
  868. /* hi, lo are already in host endian byteorder */
  869. data = (((u64)hi << 32) | lo);
  870. if (adapter->pci_mem_write(adapter,
  871. flashaddr, data))
  872. return -EIO;
  873. flashaddr += 8;
  874. }
  875. }
  876. msleep(1);
  877. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id)) {
  878. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x18, 0x1020);
  879. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001e);
  880. } else if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  881. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  882. else {
  883. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  884. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  885. }
  886. return 0;
  887. }
  888. static int
  889. netxen_validate_firmware(struct netxen_adapter *adapter)
  890. {
  891. __le32 val;
  892. __le32 flash_fw_ver;
  893. u32 file_fw_ver, min_ver, bios;
  894. struct pci_dev *pdev = adapter->pdev;
  895. const struct firmware *fw = adapter->fw;
  896. u8 fw_type = adapter->fw_type;
  897. u32 crbinit_fix_fw;
  898. if (fw_type == NX_UNIFIED_ROMIMAGE) {
  899. if (netxen_nic_validate_unified_romimage(adapter))
  900. return -EINVAL;
  901. } else {
  902. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  903. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  904. return -EINVAL;
  905. if (fw->size < NX_FW_MIN_SIZE)
  906. return -EINVAL;
  907. }
  908. val = nx_get_fw_version(adapter);
  909. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  910. min_ver = NETXEN_MIN_P3_FW_SUPP;
  911. else
  912. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  913. file_fw_ver = NETXEN_DECODE_VERSION(val);
  914. if ((_major(file_fw_ver) > _NETXEN_NIC_LINUX_MAJOR) ||
  915. (file_fw_ver < min_ver)) {
  916. dev_err(&pdev->dev,
  917. "%s: firmware version %d.%d.%d unsupported\n",
  918. fw_name[fw_type], _major(file_fw_ver), _minor(file_fw_ver),
  919. _build(file_fw_ver));
  920. return -EINVAL;
  921. }
  922. val = nx_get_bios_version(adapter);
  923. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  924. if ((__force u32)val != bios) {
  925. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  926. fw_name[fw_type]);
  927. return -EINVAL;
  928. }
  929. if (netxen_rom_fast_read(adapter,
  930. NX_FW_VERSION_OFFSET, (int *)&flash_fw_ver)) {
  931. dev_err(&pdev->dev, "Unable to read flash fw version\n");
  932. return -EIO;
  933. }
  934. flash_fw_ver = NETXEN_DECODE_VERSION(flash_fw_ver);
  935. /* New fw from file is not allowed, if fw on flash is < 4.0.554 */
  936. crbinit_fix_fw = NETXEN_VERSION_CODE(4, 0, 554);
  937. if (file_fw_ver >= crbinit_fix_fw && flash_fw_ver < crbinit_fix_fw &&
  938. NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  939. dev_err(&pdev->dev, "Incompatibility detected between driver "
  940. "and firmware version on flash. This configuration "
  941. "is not recommended. Please update the firmware on "
  942. "flash immediately\n");
  943. return -EINVAL;
  944. }
  945. /* check if flashed firmware is newer only for no-mn and P2 case*/
  946. if (!netxen_p3_has_mn(adapter) ||
  947. NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  948. if (flash_fw_ver > file_fw_ver) {
  949. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  950. fw_name[fw_type]);
  951. return -EINVAL;
  952. }
  953. }
  954. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  955. return 0;
  956. }
  957. static void
  958. nx_get_next_fwtype(struct netxen_adapter *adapter)
  959. {
  960. u8 fw_type;
  961. switch (adapter->fw_type) {
  962. case NX_UNKNOWN_ROMIMAGE:
  963. fw_type = NX_UNIFIED_ROMIMAGE;
  964. break;
  965. case NX_UNIFIED_ROMIMAGE:
  966. if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
  967. fw_type = NX_FLASH_ROMIMAGE;
  968. else if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  969. fw_type = NX_P2_MN_ROMIMAGE;
  970. else if (netxen_p3_has_mn(adapter))
  971. fw_type = NX_P3_MN_ROMIMAGE;
  972. else
  973. fw_type = NX_P3_CT_ROMIMAGE;
  974. break;
  975. case NX_P3_MN_ROMIMAGE:
  976. fw_type = NX_P3_CT_ROMIMAGE;
  977. break;
  978. case NX_P2_MN_ROMIMAGE:
  979. case NX_P3_CT_ROMIMAGE:
  980. default:
  981. fw_type = NX_FLASH_ROMIMAGE;
  982. break;
  983. }
  984. adapter->fw_type = fw_type;
  985. }
  986. static int
  987. netxen_p3_has_mn(struct netxen_adapter *adapter)
  988. {
  989. u32 capability, flashed_ver;
  990. capability = 0;
  991. /* NX2031 always had MN */
  992. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  993. return 1;
  994. netxen_rom_fast_read(adapter,
  995. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  996. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  997. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  998. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  999. if (capability & NX_PEG_TUNE_MN_PRESENT)
  1000. return 1;
  1001. }
  1002. return 0;
  1003. }
  1004. void netxen_request_firmware(struct netxen_adapter *adapter)
  1005. {
  1006. struct pci_dev *pdev = adapter->pdev;
  1007. int rc = 0;
  1008. adapter->fw_type = NX_UNKNOWN_ROMIMAGE;
  1009. next:
  1010. nx_get_next_fwtype(adapter);
  1011. if (adapter->fw_type == NX_FLASH_ROMIMAGE) {
  1012. adapter->fw = NULL;
  1013. } else {
  1014. rc = request_firmware(&adapter->fw,
  1015. fw_name[adapter->fw_type], &pdev->dev);
  1016. if (rc != 0)
  1017. goto next;
  1018. rc = netxen_validate_firmware(adapter);
  1019. if (rc != 0) {
  1020. release_firmware(adapter->fw);
  1021. msleep(1);
  1022. goto next;
  1023. }
  1024. }
  1025. }
  1026. void
  1027. netxen_release_firmware(struct netxen_adapter *adapter)
  1028. {
  1029. release_firmware(adapter->fw);
  1030. adapter->fw = NULL;
  1031. }
  1032. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  1033. {
  1034. u64 addr;
  1035. u32 hi, lo;
  1036. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1037. return 0;
  1038. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  1039. NETXEN_HOST_DUMMY_DMA_SIZE,
  1040. &adapter->dummy_dma.phys_addr);
  1041. if (adapter->dummy_dma.addr == NULL) {
  1042. dev_err(&adapter->pdev->dev,
  1043. "ERROR: Could not allocate dummy DMA memory\n");
  1044. return -ENOMEM;
  1045. }
  1046. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  1047. hi = (addr >> 32) & 0xffffffff;
  1048. lo = addr & 0xffffffff;
  1049. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  1050. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  1051. return 0;
  1052. }
  1053. /*
  1054. * NetXen DMA watchdog control:
  1055. *
  1056. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  1057. * Bit 1 : disable_request => 1 req disable dma watchdog
  1058. * Bit 2 : enable_request => 1 req enable dma watchdog
  1059. * Bit 3-31 : unused
  1060. */
  1061. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  1062. {
  1063. int i = 100;
  1064. u32 ctrl;
  1065. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1066. return;
  1067. if (!adapter->dummy_dma.addr)
  1068. return;
  1069. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1070. if ((ctrl & 0x1) != 0) {
  1071. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  1072. while ((ctrl & 0x1) != 0) {
  1073. msleep(50);
  1074. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  1075. if (--i == 0)
  1076. break;
  1077. }
  1078. }
  1079. if (i) {
  1080. pci_free_consistent(adapter->pdev,
  1081. NETXEN_HOST_DUMMY_DMA_SIZE,
  1082. adapter->dummy_dma.addr,
  1083. adapter->dummy_dma.phys_addr);
  1084. adapter->dummy_dma.addr = NULL;
  1085. } else
  1086. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  1087. }
  1088. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  1089. {
  1090. u32 val = 0;
  1091. int retries = 60;
  1092. if (pegtune_val)
  1093. return 0;
  1094. do {
  1095. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  1096. switch (val) {
  1097. case PHAN_INITIALIZE_COMPLETE:
  1098. case PHAN_INITIALIZE_ACK:
  1099. return 0;
  1100. case PHAN_INITIALIZE_FAILED:
  1101. goto out_err;
  1102. default:
  1103. break;
  1104. }
  1105. msleep(500);
  1106. } while (--retries);
  1107. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  1108. out_err:
  1109. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  1110. return -EIO;
  1111. }
  1112. static int
  1113. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  1114. {
  1115. u32 val = 0;
  1116. int retries = 2000;
  1117. do {
  1118. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  1119. if (val == PHAN_PEG_RCV_INITIALIZED)
  1120. return 0;
  1121. msleep(10);
  1122. } while (--retries);
  1123. if (!retries) {
  1124. printk(KERN_ERR "Receive Peg initialization not "
  1125. "complete, state: 0x%x.\n", val);
  1126. return -EIO;
  1127. }
  1128. return 0;
  1129. }
  1130. int netxen_init_firmware(struct netxen_adapter *adapter)
  1131. {
  1132. int err;
  1133. err = netxen_receive_peg_ready(adapter);
  1134. if (err)
  1135. return err;
  1136. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  1137. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  1138. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  1139. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  1140. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  1141. return err;
  1142. }
  1143. static void
  1144. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  1145. {
  1146. u32 cable_OUI;
  1147. u16 cable_len;
  1148. u16 link_speed;
  1149. u8 link_status, module, duplex, autoneg;
  1150. struct net_device *netdev = adapter->netdev;
  1151. adapter->has_link_events = 1;
  1152. cable_OUI = msg->body[1] & 0xffffffff;
  1153. cable_len = (msg->body[1] >> 32) & 0xffff;
  1154. link_speed = (msg->body[1] >> 48) & 0xffff;
  1155. link_status = msg->body[2] & 0xff;
  1156. duplex = (msg->body[2] >> 16) & 0xff;
  1157. autoneg = (msg->body[2] >> 24) & 0xff;
  1158. module = (msg->body[2] >> 8) & 0xff;
  1159. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  1160. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  1161. netdev->name, cable_OUI, cable_len);
  1162. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  1163. printk(KERN_INFO "%s: unsupported cable length %d\n",
  1164. netdev->name, cable_len);
  1165. }
  1166. /* update link parameters */
  1167. if (duplex == LINKEVENT_FULL_DUPLEX)
  1168. adapter->link_duplex = DUPLEX_FULL;
  1169. else
  1170. adapter->link_duplex = DUPLEX_HALF;
  1171. adapter->module_type = module;
  1172. adapter->link_autoneg = autoneg;
  1173. adapter->link_speed = link_speed;
  1174. netxen_advert_link_change(adapter, link_status);
  1175. }
  1176. static void
  1177. netxen_handle_fw_message(int desc_cnt, int index,
  1178. struct nx_host_sds_ring *sds_ring)
  1179. {
  1180. nx_fw_msg_t msg;
  1181. struct status_desc *desc;
  1182. int i = 0, opcode;
  1183. while (desc_cnt > 0 && i < 8) {
  1184. desc = &sds_ring->desc_head[index];
  1185. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  1186. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  1187. index = get_next_index(index, sds_ring->num_desc);
  1188. desc_cnt--;
  1189. }
  1190. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  1191. switch (opcode) {
  1192. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  1193. netxen_handle_linkevent(sds_ring->adapter, &msg);
  1194. break;
  1195. default:
  1196. break;
  1197. }
  1198. }
  1199. static int
  1200. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  1201. struct nx_host_rds_ring *rds_ring,
  1202. struct netxen_rx_buffer *buffer)
  1203. {
  1204. struct sk_buff *skb;
  1205. dma_addr_t dma;
  1206. struct pci_dev *pdev = adapter->pdev;
  1207. buffer->skb = netdev_alloc_skb(adapter->netdev, rds_ring->skb_size);
  1208. if (!buffer->skb)
  1209. return 1;
  1210. skb = buffer->skb;
  1211. if (!adapter->ahw.cut_through)
  1212. skb_reserve(skb, 2);
  1213. dma = pci_map_single(pdev, skb->data,
  1214. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1215. if (pci_dma_mapping_error(pdev, dma)) {
  1216. dev_kfree_skb_any(skb);
  1217. buffer->skb = NULL;
  1218. return 1;
  1219. }
  1220. buffer->skb = skb;
  1221. buffer->dma = dma;
  1222. buffer->state = NETXEN_BUFFER_BUSY;
  1223. return 0;
  1224. }
  1225. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1226. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1227. {
  1228. struct netxen_rx_buffer *buffer;
  1229. struct sk_buff *skb;
  1230. buffer = &rds_ring->rx_buf_arr[index];
  1231. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1232. PCI_DMA_FROMDEVICE);
  1233. skb = buffer->skb;
  1234. if (!skb)
  1235. goto no_skb;
  1236. if (likely((adapter->netdev->features & NETIF_F_RXCSUM)
  1237. && cksum == STATUS_CKSUM_OK)) {
  1238. adapter->stats.csummed++;
  1239. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1240. } else
  1241. skb->ip_summed = CHECKSUM_NONE;
  1242. buffer->skb = NULL;
  1243. no_skb:
  1244. buffer->state = NETXEN_BUFFER_FREE;
  1245. return skb;
  1246. }
  1247. static struct netxen_rx_buffer *
  1248. netxen_process_rcv(struct netxen_adapter *adapter,
  1249. struct nx_host_sds_ring *sds_ring,
  1250. int ring, u64 sts_data0)
  1251. {
  1252. struct net_device *netdev = adapter->netdev;
  1253. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1254. struct netxen_rx_buffer *buffer;
  1255. struct sk_buff *skb;
  1256. struct nx_host_rds_ring *rds_ring;
  1257. int index, length, cksum, pkt_offset;
  1258. if (unlikely(ring >= adapter->max_rds_rings))
  1259. return NULL;
  1260. rds_ring = &recv_ctx->rds_rings[ring];
  1261. index = netxen_get_sts_refhandle(sts_data0);
  1262. if (unlikely(index >= rds_ring->num_desc))
  1263. return NULL;
  1264. buffer = &rds_ring->rx_buf_arr[index];
  1265. length = netxen_get_sts_totallength(sts_data0);
  1266. cksum = netxen_get_sts_status(sts_data0);
  1267. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1268. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1269. if (!skb)
  1270. return buffer;
  1271. if (length > rds_ring->skb_size)
  1272. skb_put(skb, rds_ring->skb_size);
  1273. else
  1274. skb_put(skb, length);
  1275. if (pkt_offset)
  1276. skb_pull(skb, pkt_offset);
  1277. skb->protocol = eth_type_trans(skb, netdev);
  1278. napi_gro_receive(&sds_ring->napi, skb);
  1279. adapter->stats.rx_pkts++;
  1280. adapter->stats.rxbytes += length;
  1281. return buffer;
  1282. }
  1283. #define TCP_HDR_SIZE 20
  1284. #define TCP_TS_OPTION_SIZE 12
  1285. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1286. static struct netxen_rx_buffer *
  1287. netxen_process_lro(struct netxen_adapter *adapter,
  1288. struct nx_host_sds_ring *sds_ring,
  1289. int ring, u64 sts_data0, u64 sts_data1)
  1290. {
  1291. struct net_device *netdev = adapter->netdev;
  1292. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1293. struct netxen_rx_buffer *buffer;
  1294. struct sk_buff *skb;
  1295. struct nx_host_rds_ring *rds_ring;
  1296. struct iphdr *iph;
  1297. struct tcphdr *th;
  1298. bool push, timestamp;
  1299. int l2_hdr_offset, l4_hdr_offset;
  1300. int index;
  1301. u16 lro_length, length, data_offset;
  1302. u32 seq_number;
  1303. u8 vhdr_len = 0;
  1304. if (unlikely(ring >= adapter->max_rds_rings))
  1305. return NULL;
  1306. rds_ring = &recv_ctx->rds_rings[ring];
  1307. index = netxen_get_lro_sts_refhandle(sts_data0);
  1308. if (unlikely(index >= rds_ring->num_desc))
  1309. return NULL;
  1310. buffer = &rds_ring->rx_buf_arr[index];
  1311. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1312. lro_length = netxen_get_lro_sts_length(sts_data0);
  1313. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1314. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1315. push = netxen_get_lro_sts_push_flag(sts_data0);
  1316. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1317. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1318. if (!skb)
  1319. return buffer;
  1320. if (timestamp)
  1321. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1322. else
  1323. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1324. skb_put(skb, lro_length + data_offset);
  1325. skb_pull(skb, l2_hdr_offset);
  1326. skb->protocol = eth_type_trans(skb, netdev);
  1327. if (skb->protocol == htons(ETH_P_8021Q))
  1328. vhdr_len = VLAN_HLEN;
  1329. iph = (struct iphdr *)(skb->data + vhdr_len);
  1330. th = (struct tcphdr *)((skb->data + vhdr_len) + (iph->ihl << 2));
  1331. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1332. csum_replace2(&iph->check, iph->tot_len, htons(length));
  1333. iph->tot_len = htons(length);
  1334. th->psh = push;
  1335. th->seq = htonl(seq_number);
  1336. length = skb->len;
  1337. if (adapter->flags & NETXEN_FW_MSS_CAP)
  1338. skb_shinfo(skb)->gso_size = netxen_get_lro_sts_mss(sts_data1);
  1339. netif_receive_skb(skb);
  1340. adapter->stats.lro_pkts++;
  1341. adapter->stats.rxbytes += length;
  1342. return buffer;
  1343. }
  1344. #define netxen_merge_rx_buffers(list, head) \
  1345. do { list_splice_tail_init(list, head); } while (0);
  1346. int
  1347. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1348. {
  1349. struct netxen_adapter *adapter = sds_ring->adapter;
  1350. struct list_head *cur;
  1351. struct status_desc *desc;
  1352. struct netxen_rx_buffer *rxbuf;
  1353. u32 consumer = sds_ring->consumer;
  1354. int count = 0;
  1355. u64 sts_data0, sts_data1;
  1356. int opcode, ring = 0, desc_cnt;
  1357. while (count < max) {
  1358. desc = &sds_ring->desc_head[consumer];
  1359. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1360. if (!(sts_data0 & STATUS_OWNER_HOST))
  1361. break;
  1362. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1363. opcode = netxen_get_sts_opcode(sts_data0);
  1364. switch (opcode) {
  1365. case NETXEN_NIC_RXPKT_DESC:
  1366. case NETXEN_OLD_RXPKT_DESC:
  1367. case NETXEN_NIC_SYN_OFFLOAD:
  1368. ring = netxen_get_sts_type(sts_data0);
  1369. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1370. ring, sts_data0);
  1371. break;
  1372. case NETXEN_NIC_LRO_DESC:
  1373. ring = netxen_get_lro_sts_type(sts_data0);
  1374. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1375. rxbuf = netxen_process_lro(adapter, sds_ring,
  1376. ring, sts_data0, sts_data1);
  1377. break;
  1378. case NETXEN_NIC_RESPONSE_DESC:
  1379. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1380. default:
  1381. goto skip;
  1382. }
  1383. WARN_ON(desc_cnt > 1);
  1384. if (rxbuf)
  1385. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1386. skip:
  1387. for (; desc_cnt > 0; desc_cnt--) {
  1388. desc = &sds_ring->desc_head[consumer];
  1389. desc->status_desc_data[0] =
  1390. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1391. consumer = get_next_index(consumer, sds_ring->num_desc);
  1392. }
  1393. count++;
  1394. }
  1395. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1396. struct nx_host_rds_ring *rds_ring =
  1397. &adapter->recv_ctx.rds_rings[ring];
  1398. if (!list_empty(&sds_ring->free_list[ring])) {
  1399. list_for_each(cur, &sds_ring->free_list[ring]) {
  1400. rxbuf = list_entry(cur,
  1401. struct netxen_rx_buffer, list);
  1402. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1403. }
  1404. spin_lock(&rds_ring->lock);
  1405. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1406. &rds_ring->free_list);
  1407. spin_unlock(&rds_ring->lock);
  1408. }
  1409. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1410. }
  1411. if (count) {
  1412. sds_ring->consumer = consumer;
  1413. NXWRIO(adapter, sds_ring->crb_sts_consumer, consumer);
  1414. }
  1415. return count;
  1416. }
  1417. /* Process Command status ring */
  1418. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1419. {
  1420. u32 sw_consumer, hw_consumer;
  1421. int count = 0, i;
  1422. struct netxen_cmd_buffer *buffer;
  1423. struct pci_dev *pdev = adapter->pdev;
  1424. struct net_device *netdev = adapter->netdev;
  1425. struct netxen_skb_frag *frag;
  1426. int done = 0;
  1427. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1428. if (!spin_trylock(&adapter->tx_clean_lock))
  1429. return 1;
  1430. sw_consumer = tx_ring->sw_consumer;
  1431. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1432. while (sw_consumer != hw_consumer) {
  1433. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1434. if (buffer->skb) {
  1435. frag = &buffer->frag_array[0];
  1436. pci_unmap_single(pdev, frag->dma, frag->length,
  1437. PCI_DMA_TODEVICE);
  1438. frag->dma = 0ULL;
  1439. for (i = 1; i < buffer->frag_count; i++) {
  1440. frag++; /* Get the next frag */
  1441. pci_unmap_page(pdev, frag->dma, frag->length,
  1442. PCI_DMA_TODEVICE);
  1443. frag->dma = 0ULL;
  1444. }
  1445. adapter->stats.xmitfinished++;
  1446. dev_kfree_skb_any(buffer->skb);
  1447. buffer->skb = NULL;
  1448. }
  1449. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1450. if (++count >= MAX_STATUS_HANDLE)
  1451. break;
  1452. }
  1453. if (count && netif_running(netdev)) {
  1454. tx_ring->sw_consumer = sw_consumer;
  1455. smp_mb();
  1456. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev))
  1457. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1458. netif_wake_queue(netdev);
  1459. adapter->tx_timeo_cnt = 0;
  1460. }
  1461. /*
  1462. * If everything is freed up to consumer then check if the ring is full
  1463. * If the ring is full then check if more needs to be freed and
  1464. * schedule the call back again.
  1465. *
  1466. * This happens when there are 2 CPUs. One could be freeing and the
  1467. * other filling it. If the ring is full when we get out of here and
  1468. * the card has already interrupted the host then the host can miss the
  1469. * interrupt.
  1470. *
  1471. * There is still a possible race condition and the host could miss an
  1472. * interrupt. The card has to take care of this.
  1473. */
  1474. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1475. done = (sw_consumer == hw_consumer);
  1476. spin_unlock(&adapter->tx_clean_lock);
  1477. return done;
  1478. }
  1479. void
  1480. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1481. struct nx_host_rds_ring *rds_ring)
  1482. {
  1483. struct rcv_desc *pdesc;
  1484. struct netxen_rx_buffer *buffer;
  1485. int producer, count = 0;
  1486. netxen_ctx_msg msg = 0;
  1487. struct list_head *head;
  1488. producer = rds_ring->producer;
  1489. head = &rds_ring->free_list;
  1490. while (!list_empty(head)) {
  1491. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1492. if (!buffer->skb) {
  1493. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1494. break;
  1495. }
  1496. count++;
  1497. list_del(&buffer->list);
  1498. /* make a rcv descriptor */
  1499. pdesc = &rds_ring->desc_head[producer];
  1500. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1501. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1502. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1503. producer = get_next_index(producer, rds_ring->num_desc);
  1504. }
  1505. if (count) {
  1506. rds_ring->producer = producer;
  1507. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1508. (producer-1) & (rds_ring->num_desc-1));
  1509. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1510. /*
  1511. * Write a doorbell msg to tell phanmon of change in
  1512. * receive ring producer
  1513. * Only for firmware version < 4.0.0
  1514. */
  1515. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1516. netxen_set_msg_privid(msg);
  1517. netxen_set_msg_count(msg,
  1518. ((producer - 1) &
  1519. (rds_ring->num_desc - 1)));
  1520. netxen_set_msg_ctxid(msg, adapter->portnum);
  1521. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1522. NXWRIO(adapter, DB_NORMALIZE(adapter,
  1523. NETXEN_RCV_PRODUCER_OFFSET), msg);
  1524. }
  1525. }
  1526. }
  1527. static void
  1528. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1529. struct nx_host_rds_ring *rds_ring)
  1530. {
  1531. struct rcv_desc *pdesc;
  1532. struct netxen_rx_buffer *buffer;
  1533. int producer, count = 0;
  1534. struct list_head *head;
  1535. if (!spin_trylock(&rds_ring->lock))
  1536. return;
  1537. producer = rds_ring->producer;
  1538. head = &rds_ring->free_list;
  1539. while (!list_empty(head)) {
  1540. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1541. if (!buffer->skb) {
  1542. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1543. break;
  1544. }
  1545. count++;
  1546. list_del(&buffer->list);
  1547. /* make a rcv descriptor */
  1548. pdesc = &rds_ring->desc_head[producer];
  1549. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1550. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1551. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1552. producer = get_next_index(producer, rds_ring->num_desc);
  1553. }
  1554. if (count) {
  1555. rds_ring->producer = producer;
  1556. NXWRIO(adapter, rds_ring->crb_rcv_producer,
  1557. (producer - 1) & (rds_ring->num_desc - 1));
  1558. }
  1559. spin_unlock(&rds_ring->lock);
  1560. }
  1561. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1562. {
  1563. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1564. }