setup.c 26 KB

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  1. /*
  2. * linux/arch/arm/kernel/setup.c
  3. *
  4. * Copyright (C) 1995-2001 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/export.h>
  11. #include <linux/kernel.h>
  12. #include <linux/stddef.h>
  13. #include <linux/ioport.h>
  14. #include <linux/delay.h>
  15. #include <linux/utsname.h>
  16. #include <linux/initrd.h>
  17. #include <linux/console.h>
  18. #include <linux/bootmem.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/screen_info.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/init.h>
  23. #include <linux/kexec.h>
  24. #include <linux/of_fdt.h>
  25. #include <linux/cpu.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/smp.h>
  28. #include <linux/proc_fs.h>
  29. #include <linux/memblock.h>
  30. #include <linux/bug.h>
  31. #include <linux/compiler.h>
  32. #include <linux/sort.h>
  33. #include <asm/unified.h>
  34. #include <asm/cp15.h>
  35. #include <asm/cpu.h>
  36. #include <asm/cputype.h>
  37. #include <asm/elf.h>
  38. #include <asm/procinfo.h>
  39. #include <asm/psci.h>
  40. #include <asm/sections.h>
  41. #include <asm/setup.h>
  42. #include <asm/smp_plat.h>
  43. #include <asm/mach-types.h>
  44. #include <asm/cacheflush.h>
  45. #include <asm/cachetype.h>
  46. #include <asm/tlbflush.h>
  47. #include <asm/prom.h>
  48. #include <asm/mach/arch.h>
  49. #include <asm/mach/irq.h>
  50. #include <asm/mach/time.h>
  51. #include <asm/system_info.h>
  52. #include <asm/system_misc.h>
  53. #include <asm/traps.h>
  54. #include <asm/unwind.h>
  55. #include <asm/memblock.h>
  56. #include <asm/virt.h>
  57. #include "atags.h"
  58. #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
  59. char fpe_type[8];
  60. static int __init fpe_setup(char *line)
  61. {
  62. memcpy(fpe_type, line, 8);
  63. return 1;
  64. }
  65. __setup("fpe=", fpe_setup);
  66. #endif
  67. extern void paging_init(const struct machine_desc *desc);
  68. extern void early_paging_init(const struct machine_desc *,
  69. struct proc_info_list *);
  70. extern void sanity_check_meminfo(void);
  71. extern enum reboot_mode reboot_mode;
  72. extern void setup_dma_zone(const struct machine_desc *desc);
  73. unsigned int processor_id;
  74. EXPORT_SYMBOL(processor_id);
  75. unsigned int __machine_arch_type __read_mostly;
  76. EXPORT_SYMBOL(__machine_arch_type);
  77. unsigned int cacheid __read_mostly;
  78. EXPORT_SYMBOL(cacheid);
  79. unsigned int __atags_pointer __initdata;
  80. unsigned int system_rev;
  81. EXPORT_SYMBOL(system_rev);
  82. unsigned int system_serial_low;
  83. EXPORT_SYMBOL(system_serial_low);
  84. unsigned int system_serial_high;
  85. EXPORT_SYMBOL(system_serial_high);
  86. unsigned int elf_hwcap __read_mostly;
  87. EXPORT_SYMBOL(elf_hwcap);
  88. unsigned int elf_hwcap2 __read_mostly;
  89. EXPORT_SYMBOL(elf_hwcap2);
  90. #ifdef MULTI_CPU
  91. struct processor processor __read_mostly;
  92. #endif
  93. #ifdef MULTI_TLB
  94. struct cpu_tlb_fns cpu_tlb __read_mostly;
  95. #endif
  96. #ifdef MULTI_USER
  97. struct cpu_user_fns cpu_user __read_mostly;
  98. #endif
  99. #ifdef MULTI_CACHE
  100. struct cpu_cache_fns cpu_cache __read_mostly;
  101. #endif
  102. #ifdef CONFIG_OUTER_CACHE
  103. struct outer_cache_fns outer_cache __read_mostly;
  104. EXPORT_SYMBOL(outer_cache);
  105. #endif
  106. /*
  107. * Cached cpu_architecture() result for use by assembler code.
  108. * C code should use the cpu_architecture() function instead of accessing this
  109. * variable directly.
  110. */
  111. int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
  112. struct stack {
  113. u32 irq[3];
  114. u32 abt[3];
  115. u32 und[3];
  116. } ____cacheline_aligned;
  117. #ifndef CONFIG_CPU_V7M
  118. static struct stack stacks[NR_CPUS];
  119. #endif
  120. char elf_platform[ELF_PLATFORM_SIZE];
  121. EXPORT_SYMBOL(elf_platform);
  122. static const char *cpu_name;
  123. static const char *machine_name;
  124. static char __initdata cmd_line[COMMAND_LINE_SIZE];
  125. const struct machine_desc *machine_desc __initdata;
  126. static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
  127. #define ENDIANNESS ((char)endian_test.l)
  128. DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
  129. /*
  130. * Standard memory resources
  131. */
  132. static struct resource mem_res[] = {
  133. {
  134. .name = "Video RAM",
  135. .start = 0,
  136. .end = 0,
  137. .flags = IORESOURCE_MEM
  138. },
  139. {
  140. .name = "Kernel code",
  141. .start = 0,
  142. .end = 0,
  143. .flags = IORESOURCE_MEM
  144. },
  145. {
  146. .name = "Kernel data",
  147. .start = 0,
  148. .end = 0,
  149. .flags = IORESOURCE_MEM
  150. }
  151. };
  152. #define video_ram mem_res[0]
  153. #define kernel_code mem_res[1]
  154. #define kernel_data mem_res[2]
  155. static struct resource io_res[] = {
  156. {
  157. .name = "reserved",
  158. .start = 0x3bc,
  159. .end = 0x3be,
  160. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  161. },
  162. {
  163. .name = "reserved",
  164. .start = 0x378,
  165. .end = 0x37f,
  166. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  167. },
  168. {
  169. .name = "reserved",
  170. .start = 0x278,
  171. .end = 0x27f,
  172. .flags = IORESOURCE_IO | IORESOURCE_BUSY
  173. }
  174. };
  175. #define lp0 io_res[0]
  176. #define lp1 io_res[1]
  177. #define lp2 io_res[2]
  178. static const char *proc_arch[] = {
  179. "undefined/unknown",
  180. "3",
  181. "4",
  182. "4T",
  183. "5",
  184. "5T",
  185. "5TE",
  186. "5TEJ",
  187. "6TEJ",
  188. "7",
  189. "7M",
  190. "?(12)",
  191. "?(13)",
  192. "?(14)",
  193. "?(15)",
  194. "?(16)",
  195. "?(17)",
  196. };
  197. #ifdef CONFIG_CPU_V7M
  198. static int __get_cpu_architecture(void)
  199. {
  200. return CPU_ARCH_ARMv7M;
  201. }
  202. #else
  203. static int __get_cpu_architecture(void)
  204. {
  205. int cpu_arch;
  206. if ((read_cpuid_id() & 0x0008f000) == 0) {
  207. cpu_arch = CPU_ARCH_UNKNOWN;
  208. } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
  209. cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
  210. } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
  211. cpu_arch = (read_cpuid_id() >> 16) & 7;
  212. if (cpu_arch)
  213. cpu_arch += CPU_ARCH_ARMv3;
  214. } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
  215. unsigned int mmfr0;
  216. /* Revised CPUID format. Read the Memory Model Feature
  217. * Register 0 and check for VMSAv7 or PMSAv7 */
  218. asm("mrc p15, 0, %0, c0, c1, 4"
  219. : "=r" (mmfr0));
  220. if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
  221. (mmfr0 & 0x000000f0) >= 0x00000030)
  222. cpu_arch = CPU_ARCH_ARMv7;
  223. else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
  224. (mmfr0 & 0x000000f0) == 0x00000020)
  225. cpu_arch = CPU_ARCH_ARMv6;
  226. else
  227. cpu_arch = CPU_ARCH_UNKNOWN;
  228. } else
  229. cpu_arch = CPU_ARCH_UNKNOWN;
  230. return cpu_arch;
  231. }
  232. #endif
  233. int __pure cpu_architecture(void)
  234. {
  235. BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
  236. return __cpu_architecture;
  237. }
  238. static int cpu_has_aliasing_icache(unsigned int arch)
  239. {
  240. int aliasing_icache;
  241. unsigned int id_reg, num_sets, line_size;
  242. /* PIPT caches never alias. */
  243. if (icache_is_pipt())
  244. return 0;
  245. /* arch specifies the register format */
  246. switch (arch) {
  247. case CPU_ARCH_ARMv7:
  248. asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
  249. : /* No output operands */
  250. : "r" (1));
  251. isb();
  252. asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
  253. : "=r" (id_reg));
  254. line_size = 4 << ((id_reg & 0x7) + 2);
  255. num_sets = ((id_reg >> 13) & 0x7fff) + 1;
  256. aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
  257. break;
  258. case CPU_ARCH_ARMv6:
  259. aliasing_icache = read_cpuid_cachetype() & (1 << 11);
  260. break;
  261. default:
  262. /* I-cache aliases will be handled by D-cache aliasing code */
  263. aliasing_icache = 0;
  264. }
  265. return aliasing_icache;
  266. }
  267. static void __init cacheid_init(void)
  268. {
  269. unsigned int arch = cpu_architecture();
  270. if (arch == CPU_ARCH_ARMv7M) {
  271. cacheid = 0;
  272. } else if (arch >= CPU_ARCH_ARMv6) {
  273. unsigned int cachetype = read_cpuid_cachetype();
  274. if ((cachetype & (7 << 29)) == 4 << 29) {
  275. /* ARMv7 register format */
  276. arch = CPU_ARCH_ARMv7;
  277. cacheid = CACHEID_VIPT_NONALIASING;
  278. switch (cachetype & (3 << 14)) {
  279. case (1 << 14):
  280. cacheid |= CACHEID_ASID_TAGGED;
  281. break;
  282. case (3 << 14):
  283. cacheid |= CACHEID_PIPT;
  284. break;
  285. }
  286. } else {
  287. arch = CPU_ARCH_ARMv6;
  288. if (cachetype & (1 << 23))
  289. cacheid = CACHEID_VIPT_ALIASING;
  290. else
  291. cacheid = CACHEID_VIPT_NONALIASING;
  292. }
  293. if (cpu_has_aliasing_icache(arch))
  294. cacheid |= CACHEID_VIPT_I_ALIASING;
  295. } else {
  296. cacheid = CACHEID_VIVT;
  297. }
  298. pr_info("CPU: %s data cache, %s instruction cache\n",
  299. cache_is_vivt() ? "VIVT" :
  300. cache_is_vipt_aliasing() ? "VIPT aliasing" :
  301. cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
  302. cache_is_vivt() ? "VIVT" :
  303. icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
  304. icache_is_vipt_aliasing() ? "VIPT aliasing" :
  305. icache_is_pipt() ? "PIPT" :
  306. cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
  307. }
  308. /*
  309. * These functions re-use the assembly code in head.S, which
  310. * already provide the required functionality.
  311. */
  312. extern struct proc_info_list *lookup_processor_type(unsigned int);
  313. void __init early_print(const char *str, ...)
  314. {
  315. extern void printascii(const char *);
  316. char buf[256];
  317. va_list ap;
  318. va_start(ap, str);
  319. vsnprintf(buf, sizeof(buf), str, ap);
  320. va_end(ap);
  321. #ifdef CONFIG_DEBUG_LL
  322. printascii(buf);
  323. #endif
  324. printk("%s", buf);
  325. }
  326. static void __init cpuid_init_hwcaps(void)
  327. {
  328. unsigned int divide_instrs, vmsa;
  329. if (cpu_architecture() < CPU_ARCH_ARMv7)
  330. return;
  331. divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
  332. switch (divide_instrs) {
  333. case 2:
  334. elf_hwcap |= HWCAP_IDIVA;
  335. case 1:
  336. elf_hwcap |= HWCAP_IDIVT;
  337. }
  338. /* LPAE implies atomic ldrd/strd instructions */
  339. vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
  340. if (vmsa >= 5)
  341. elf_hwcap |= HWCAP_LPAE;
  342. }
  343. static void __init feat_v6_fixup(void)
  344. {
  345. int id = read_cpuid_id();
  346. if ((id & 0xff0f0000) != 0x41070000)
  347. return;
  348. /*
  349. * HWCAP_TLS is available only on 1136 r1p0 and later,
  350. * see also kuser_get_tls_init.
  351. */
  352. if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
  353. elf_hwcap &= ~HWCAP_TLS;
  354. }
  355. /*
  356. * cpu_init - initialise one CPU.
  357. *
  358. * cpu_init sets up the per-CPU stacks.
  359. */
  360. void notrace cpu_init(void)
  361. {
  362. #ifndef CONFIG_CPU_V7M
  363. unsigned int cpu = smp_processor_id();
  364. struct stack *stk = &stacks[cpu];
  365. if (cpu >= NR_CPUS) {
  366. pr_crit("CPU%u: bad primary CPU number\n", cpu);
  367. BUG();
  368. }
  369. /*
  370. * This only works on resume and secondary cores. For booting on the
  371. * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
  372. */
  373. set_my_cpu_offset(per_cpu_offset(cpu));
  374. cpu_proc_init();
  375. /*
  376. * Define the placement constraint for the inline asm directive below.
  377. * In Thumb-2, msr with an immediate value is not allowed.
  378. */
  379. #ifdef CONFIG_THUMB2_KERNEL
  380. #define PLC "r"
  381. #else
  382. #define PLC "I"
  383. #endif
  384. /*
  385. * setup stacks for re-entrant exception handlers
  386. */
  387. __asm__ (
  388. "msr cpsr_c, %1\n\t"
  389. "add r14, %0, %2\n\t"
  390. "mov sp, r14\n\t"
  391. "msr cpsr_c, %3\n\t"
  392. "add r14, %0, %4\n\t"
  393. "mov sp, r14\n\t"
  394. "msr cpsr_c, %5\n\t"
  395. "add r14, %0, %6\n\t"
  396. "mov sp, r14\n\t"
  397. "msr cpsr_c, %7"
  398. :
  399. : "r" (stk),
  400. PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
  401. "I" (offsetof(struct stack, irq[0])),
  402. PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
  403. "I" (offsetof(struct stack, abt[0])),
  404. PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
  405. "I" (offsetof(struct stack, und[0])),
  406. PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
  407. : "r14");
  408. #endif
  409. }
  410. u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
  411. void __init smp_setup_processor_id(void)
  412. {
  413. int i;
  414. u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
  415. u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
  416. cpu_logical_map(0) = cpu;
  417. for (i = 1; i < nr_cpu_ids; ++i)
  418. cpu_logical_map(i) = i == cpu ? 0 : i;
  419. /*
  420. * clear __my_cpu_offset on boot CPU to avoid hang caused by
  421. * using percpu variable early, for example, lockdep will
  422. * access percpu variable inside lock_release
  423. */
  424. set_my_cpu_offset(0);
  425. pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
  426. }
  427. struct mpidr_hash mpidr_hash;
  428. #ifdef CONFIG_SMP
  429. /**
  430. * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
  431. * level in order to build a linear index from an
  432. * MPIDR value. Resulting algorithm is a collision
  433. * free hash carried out through shifting and ORing
  434. */
  435. static void __init smp_build_mpidr_hash(void)
  436. {
  437. u32 i, affinity;
  438. u32 fs[3], bits[3], ls, mask = 0;
  439. /*
  440. * Pre-scan the list of MPIDRS and filter out bits that do
  441. * not contribute to affinity levels, ie they never toggle.
  442. */
  443. for_each_possible_cpu(i)
  444. mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
  445. pr_debug("mask of set bits 0x%x\n", mask);
  446. /*
  447. * Find and stash the last and first bit set at all affinity levels to
  448. * check how many bits are required to represent them.
  449. */
  450. for (i = 0; i < 3; i++) {
  451. affinity = MPIDR_AFFINITY_LEVEL(mask, i);
  452. /*
  453. * Find the MSB bit and LSB bits position
  454. * to determine how many bits are required
  455. * to express the affinity level.
  456. */
  457. ls = fls(affinity);
  458. fs[i] = affinity ? ffs(affinity) - 1 : 0;
  459. bits[i] = ls - fs[i];
  460. }
  461. /*
  462. * An index can be created from the MPIDR by isolating the
  463. * significant bits at each affinity level and by shifting
  464. * them in order to compress the 24 bits values space to a
  465. * compressed set of values. This is equivalent to hashing
  466. * the MPIDR through shifting and ORing. It is a collision free
  467. * hash though not minimal since some levels might contain a number
  468. * of CPUs that is not an exact power of 2 and their bit
  469. * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
  470. */
  471. mpidr_hash.shift_aff[0] = fs[0];
  472. mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
  473. mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
  474. (bits[1] + bits[0]);
  475. mpidr_hash.mask = mask;
  476. mpidr_hash.bits = bits[2] + bits[1] + bits[0];
  477. pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
  478. mpidr_hash.shift_aff[0],
  479. mpidr_hash.shift_aff[1],
  480. mpidr_hash.shift_aff[2],
  481. mpidr_hash.mask,
  482. mpidr_hash.bits);
  483. /*
  484. * 4x is an arbitrary value used to warn on a hash table much bigger
  485. * than expected on most systems.
  486. */
  487. if (mpidr_hash_size() > 4 * num_possible_cpus())
  488. pr_warn("Large number of MPIDR hash buckets detected\n");
  489. sync_cache_w(&mpidr_hash);
  490. }
  491. #endif
  492. static void __init setup_processor(void)
  493. {
  494. struct proc_info_list *list;
  495. /*
  496. * locate processor in the list of supported processor
  497. * types. The linker builds this table for us from the
  498. * entries in arch/arm/mm/proc-*.S
  499. */
  500. list = lookup_processor_type(read_cpuid_id());
  501. if (!list) {
  502. pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
  503. read_cpuid_id());
  504. while (1);
  505. }
  506. cpu_name = list->cpu_name;
  507. __cpu_architecture = __get_cpu_architecture();
  508. #ifdef MULTI_CPU
  509. processor = *list->proc;
  510. #endif
  511. #ifdef MULTI_TLB
  512. cpu_tlb = *list->tlb;
  513. #endif
  514. #ifdef MULTI_USER
  515. cpu_user = *list->user;
  516. #endif
  517. #ifdef MULTI_CACHE
  518. cpu_cache = *list->cache;
  519. #endif
  520. pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
  521. cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
  522. proc_arch[cpu_architecture()], cr_alignment);
  523. snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
  524. list->arch_name, ENDIANNESS);
  525. snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
  526. list->elf_name, ENDIANNESS);
  527. elf_hwcap = list->elf_hwcap;
  528. cpuid_init_hwcaps();
  529. #ifndef CONFIG_ARM_THUMB
  530. elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
  531. #endif
  532. erratum_a15_798181_init();
  533. feat_v6_fixup();
  534. cacheid_init();
  535. cpu_init();
  536. }
  537. void __init dump_machine_table(void)
  538. {
  539. const struct machine_desc *p;
  540. early_print("Available machine support:\n\nID (hex)\tNAME\n");
  541. for_each_machine_desc(p)
  542. early_print("%08x\t%s\n", p->nr, p->name);
  543. early_print("\nPlease check your kernel config and/or bootloader.\n");
  544. while (true)
  545. /* can't use cpu_relax() here as it may require MMU setup */;
  546. }
  547. int __init arm_add_memory(u64 start, u64 size)
  548. {
  549. struct membank *bank = &meminfo.bank[meminfo.nr_banks];
  550. u64 aligned_start;
  551. if (meminfo.nr_banks >= NR_BANKS) {
  552. pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n",
  553. (long long)start);
  554. return -EINVAL;
  555. }
  556. /*
  557. * Ensure that start/size are aligned to a page boundary.
  558. * Size is appropriately rounded down, start is rounded up.
  559. */
  560. size -= start & ~PAGE_MASK;
  561. aligned_start = PAGE_ALIGN(start);
  562. #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
  563. if (aligned_start > ULONG_MAX) {
  564. pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
  565. (long long)start);
  566. return -EINVAL;
  567. }
  568. if (aligned_start + size > ULONG_MAX) {
  569. pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
  570. (long long)start);
  571. /*
  572. * To ensure bank->start + bank->size is representable in
  573. * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
  574. * This means we lose a page after masking.
  575. */
  576. size = ULONG_MAX - aligned_start;
  577. }
  578. #endif
  579. if (aligned_start < PHYS_OFFSET) {
  580. if (aligned_start + size <= PHYS_OFFSET) {
  581. pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
  582. aligned_start, aligned_start + size);
  583. return -EINVAL;
  584. }
  585. pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
  586. aligned_start, (u64)PHYS_OFFSET);
  587. size -= PHYS_OFFSET - aligned_start;
  588. aligned_start = PHYS_OFFSET;
  589. }
  590. bank->start = aligned_start;
  591. bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
  592. /*
  593. * Check whether this memory region has non-zero size or
  594. * invalid node number.
  595. */
  596. if (bank->size == 0)
  597. return -EINVAL;
  598. meminfo.nr_banks++;
  599. return 0;
  600. }
  601. /*
  602. * Pick out the memory size. We look for mem=size@start,
  603. * where start and size are "size[KkMm]"
  604. */
  605. static int __init early_mem(char *p)
  606. {
  607. static int usermem __initdata = 0;
  608. u64 size;
  609. u64 start;
  610. char *endp;
  611. /*
  612. * If the user specifies memory size, we
  613. * blow away any automatically generated
  614. * size.
  615. */
  616. if (usermem == 0) {
  617. usermem = 1;
  618. meminfo.nr_banks = 0;
  619. }
  620. start = PHYS_OFFSET;
  621. size = memparse(p, &endp);
  622. if (*endp == '@')
  623. start = memparse(endp + 1, NULL);
  624. arm_add_memory(start, size);
  625. return 0;
  626. }
  627. early_param("mem", early_mem);
  628. static void __init request_standard_resources(const struct machine_desc *mdesc)
  629. {
  630. struct memblock_region *region;
  631. struct resource *res;
  632. kernel_code.start = virt_to_phys(_text);
  633. kernel_code.end = virt_to_phys(_etext - 1);
  634. kernel_data.start = virt_to_phys(_sdata);
  635. kernel_data.end = virt_to_phys(_end - 1);
  636. for_each_memblock(memory, region) {
  637. res = memblock_virt_alloc(sizeof(*res), 0);
  638. res->name = "System RAM";
  639. res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
  640. res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
  641. res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
  642. request_resource(&iomem_resource, res);
  643. if (kernel_code.start >= res->start &&
  644. kernel_code.end <= res->end)
  645. request_resource(res, &kernel_code);
  646. if (kernel_data.start >= res->start &&
  647. kernel_data.end <= res->end)
  648. request_resource(res, &kernel_data);
  649. }
  650. if (mdesc->video_start) {
  651. video_ram.start = mdesc->video_start;
  652. video_ram.end = mdesc->video_end;
  653. request_resource(&iomem_resource, &video_ram);
  654. }
  655. /*
  656. * Some machines don't have the possibility of ever
  657. * possessing lp0, lp1 or lp2
  658. */
  659. if (mdesc->reserve_lp0)
  660. request_resource(&ioport_resource, &lp0);
  661. if (mdesc->reserve_lp1)
  662. request_resource(&ioport_resource, &lp1);
  663. if (mdesc->reserve_lp2)
  664. request_resource(&ioport_resource, &lp2);
  665. }
  666. #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
  667. struct screen_info screen_info = {
  668. .orig_video_lines = 30,
  669. .orig_video_cols = 80,
  670. .orig_video_mode = 0,
  671. .orig_video_ega_bx = 0,
  672. .orig_video_isVGA = 1,
  673. .orig_video_points = 8
  674. };
  675. #endif
  676. static int __init customize_machine(void)
  677. {
  678. /*
  679. * customizes platform devices, or adds new ones
  680. * On DT based machines, we fall back to populating the
  681. * machine from the device tree, if no callback is provided,
  682. * otherwise we would always need an init_machine callback.
  683. */
  684. if (machine_desc->init_machine)
  685. machine_desc->init_machine();
  686. #ifdef CONFIG_OF
  687. else
  688. of_platform_populate(NULL, of_default_bus_match_table,
  689. NULL, NULL);
  690. #endif
  691. return 0;
  692. }
  693. arch_initcall(customize_machine);
  694. static int __init init_machine_late(void)
  695. {
  696. if (machine_desc->init_late)
  697. machine_desc->init_late();
  698. return 0;
  699. }
  700. late_initcall(init_machine_late);
  701. #ifdef CONFIG_KEXEC
  702. static inline unsigned long long get_total_mem(void)
  703. {
  704. unsigned long total;
  705. total = max_low_pfn - min_low_pfn;
  706. return total << PAGE_SHIFT;
  707. }
  708. /**
  709. * reserve_crashkernel() - reserves memory are for crash kernel
  710. *
  711. * This function reserves memory area given in "crashkernel=" kernel command
  712. * line parameter. The memory reserved is used by a dump capture kernel when
  713. * primary kernel is crashing.
  714. */
  715. static void __init reserve_crashkernel(void)
  716. {
  717. unsigned long long crash_size, crash_base;
  718. unsigned long long total_mem;
  719. int ret;
  720. total_mem = get_total_mem();
  721. ret = parse_crashkernel(boot_command_line, total_mem,
  722. &crash_size, &crash_base);
  723. if (ret)
  724. return;
  725. ret = memblock_reserve(crash_base, crash_size);
  726. if (ret < 0) {
  727. pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
  728. (unsigned long)crash_base);
  729. return;
  730. }
  731. pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
  732. (unsigned long)(crash_size >> 20),
  733. (unsigned long)(crash_base >> 20),
  734. (unsigned long)(total_mem >> 20));
  735. crashk_res.start = crash_base;
  736. crashk_res.end = crash_base + crash_size - 1;
  737. insert_resource(&iomem_resource, &crashk_res);
  738. }
  739. #else
  740. static inline void reserve_crashkernel(void) {}
  741. #endif /* CONFIG_KEXEC */
  742. static int __init meminfo_cmp(const void *_a, const void *_b)
  743. {
  744. const struct membank *a = _a, *b = _b;
  745. long cmp = bank_pfn_start(a) - bank_pfn_start(b);
  746. return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
  747. }
  748. void __init hyp_mode_check(void)
  749. {
  750. #ifdef CONFIG_ARM_VIRT_EXT
  751. sync_boot_mode();
  752. if (is_hyp_mode_available()) {
  753. pr_info("CPU: All CPU(s) started in HYP mode.\n");
  754. pr_info("CPU: Virtualization extensions available.\n");
  755. } else if (is_hyp_mode_mismatched()) {
  756. pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
  757. __boot_cpu_mode & MODE_MASK);
  758. pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
  759. } else
  760. pr_info("CPU: All CPU(s) started in SVC mode.\n");
  761. #endif
  762. }
  763. void __init setup_arch(char **cmdline_p)
  764. {
  765. const struct machine_desc *mdesc;
  766. setup_processor();
  767. mdesc = setup_machine_fdt(__atags_pointer);
  768. if (!mdesc)
  769. mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
  770. machine_desc = mdesc;
  771. machine_name = mdesc->name;
  772. if (mdesc->reboot_mode != REBOOT_HARD)
  773. reboot_mode = mdesc->reboot_mode;
  774. init_mm.start_code = (unsigned long) _text;
  775. init_mm.end_code = (unsigned long) _etext;
  776. init_mm.end_data = (unsigned long) _edata;
  777. init_mm.brk = (unsigned long) _end;
  778. /* populate cmd_line too for later use, preserving boot_command_line */
  779. strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
  780. *cmdline_p = cmd_line;
  781. parse_early_param();
  782. sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
  783. early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
  784. setup_dma_zone(mdesc);
  785. sanity_check_meminfo();
  786. arm_memblock_init(&meminfo, mdesc);
  787. paging_init(mdesc);
  788. request_standard_resources(mdesc);
  789. if (mdesc->restart)
  790. arm_pm_restart = mdesc->restart;
  791. unflatten_device_tree();
  792. arm_dt_init_cpu_maps();
  793. psci_init();
  794. #ifdef CONFIG_SMP
  795. if (is_smp()) {
  796. if (!mdesc->smp_init || !mdesc->smp_init()) {
  797. if (psci_smp_available())
  798. smp_set_ops(&psci_smp_ops);
  799. else if (mdesc->smp)
  800. smp_set_ops(mdesc->smp);
  801. }
  802. smp_init_cpus();
  803. smp_build_mpidr_hash();
  804. }
  805. #endif
  806. if (!is_smp())
  807. hyp_mode_check();
  808. reserve_crashkernel();
  809. #ifdef CONFIG_MULTI_IRQ_HANDLER
  810. handle_arch_irq = mdesc->handle_irq;
  811. #endif
  812. #ifdef CONFIG_VT
  813. #if defined(CONFIG_VGA_CONSOLE)
  814. conswitchp = &vga_con;
  815. #elif defined(CONFIG_DUMMY_CONSOLE)
  816. conswitchp = &dummy_con;
  817. #endif
  818. #endif
  819. if (mdesc->init_early)
  820. mdesc->init_early();
  821. }
  822. static int __init topology_init(void)
  823. {
  824. int cpu;
  825. for_each_possible_cpu(cpu) {
  826. struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
  827. cpuinfo->cpu.hotpluggable = 1;
  828. register_cpu(&cpuinfo->cpu, cpu);
  829. }
  830. return 0;
  831. }
  832. subsys_initcall(topology_init);
  833. #ifdef CONFIG_HAVE_PROC_CPU
  834. static int __init proc_cpu_init(void)
  835. {
  836. struct proc_dir_entry *res;
  837. res = proc_mkdir("cpu", NULL);
  838. if (!res)
  839. return -ENOMEM;
  840. return 0;
  841. }
  842. fs_initcall(proc_cpu_init);
  843. #endif
  844. static const char *hwcap_str[] = {
  845. "swp",
  846. "half",
  847. "thumb",
  848. "26bit",
  849. "fastmult",
  850. "fpa",
  851. "vfp",
  852. "edsp",
  853. "java",
  854. "iwmmxt",
  855. "crunch",
  856. "thumbee",
  857. "neon",
  858. "vfpv3",
  859. "vfpv3d16",
  860. "tls",
  861. "vfpv4",
  862. "idiva",
  863. "idivt",
  864. "vfpd32",
  865. "lpae",
  866. "evtstrm",
  867. NULL
  868. };
  869. static const char *hwcap2_str[] = {
  870. "aes",
  871. "pmull",
  872. "sha1",
  873. "sha2",
  874. "crc32",
  875. NULL
  876. };
  877. static int c_show(struct seq_file *m, void *v)
  878. {
  879. int i, j;
  880. u32 cpuid;
  881. for_each_online_cpu(i) {
  882. /*
  883. * glibc reads /proc/cpuinfo to determine the number of
  884. * online processors, looking for lines beginning with
  885. * "processor". Give glibc what it expects.
  886. */
  887. seq_printf(m, "processor\t: %d\n", i);
  888. cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
  889. seq_printf(m, "model name\t: %s rev %d (%s)\n",
  890. cpu_name, cpuid & 15, elf_platform);
  891. /* dump out the processor features */
  892. seq_puts(m, "Features\t: ");
  893. for (j = 0; hwcap_str[j]; j++)
  894. if (elf_hwcap & (1 << j))
  895. seq_printf(m, "%s ", hwcap_str[j]);
  896. for (j = 0; hwcap2_str[j]; j++)
  897. if (elf_hwcap2 & (1 << j))
  898. seq_printf(m, "%s ", hwcap2_str[j]);
  899. seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
  900. seq_printf(m, "CPU architecture: %s\n",
  901. proc_arch[cpu_architecture()]);
  902. if ((cpuid & 0x0008f000) == 0x00000000) {
  903. /* pre-ARM7 */
  904. seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
  905. } else {
  906. if ((cpuid & 0x0008f000) == 0x00007000) {
  907. /* ARM7 */
  908. seq_printf(m, "CPU variant\t: 0x%02x\n",
  909. (cpuid >> 16) & 127);
  910. } else {
  911. /* post-ARM7 */
  912. seq_printf(m, "CPU variant\t: 0x%x\n",
  913. (cpuid >> 20) & 15);
  914. }
  915. seq_printf(m, "CPU part\t: 0x%03x\n",
  916. (cpuid >> 4) & 0xfff);
  917. }
  918. seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
  919. }
  920. seq_printf(m, "Hardware\t: %s\n", machine_name);
  921. seq_printf(m, "Revision\t: %04x\n", system_rev);
  922. seq_printf(m, "Serial\t\t: %08x%08x\n",
  923. system_serial_high, system_serial_low);
  924. return 0;
  925. }
  926. static void *c_start(struct seq_file *m, loff_t *pos)
  927. {
  928. return *pos < 1 ? (void *)1 : NULL;
  929. }
  930. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  931. {
  932. ++*pos;
  933. return NULL;
  934. }
  935. static void c_stop(struct seq_file *m, void *v)
  936. {
  937. }
  938. const struct seq_operations cpuinfo_op = {
  939. .start = c_start,
  940. .next = c_next,
  941. .stop = c_stop,
  942. .show = c_show
  943. };