cxgbit_main.c 17 KB

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  1. /*
  2. * Copyright (c) 2016 Chelsio Communications, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #define DRV_NAME "cxgbit"
  9. #define DRV_VERSION "1.0.0-ko"
  10. #define pr_fmt(fmt) DRV_NAME ": " fmt
  11. #include "cxgbit.h"
  12. #ifdef CONFIG_CHELSIO_T4_DCB
  13. #include <net/dcbevent.h>
  14. #include "cxgb4_dcb.h"
  15. #endif
  16. LIST_HEAD(cdev_list_head);
  17. /* cdev list lock */
  18. DEFINE_MUTEX(cdev_list_lock);
  19. void _cxgbit_free_cdev(struct kref *kref)
  20. {
  21. struct cxgbit_device *cdev;
  22. cdev = container_of(kref, struct cxgbit_device, kref);
  23. cxgbi_ppm_release(cdev2ppm(cdev));
  24. kfree(cdev);
  25. }
  26. static void cxgbit_set_mdsl(struct cxgbit_device *cdev)
  27. {
  28. struct cxgb4_lld_info *lldi = &cdev->lldi;
  29. u32 mdsl;
  30. #define ULP2_MAX_PKT_LEN 16224
  31. #define ISCSI_PDU_NONPAYLOAD_LEN 312
  32. mdsl = min_t(u32, lldi->iscsi_iolen - ISCSI_PDU_NONPAYLOAD_LEN,
  33. ULP2_MAX_PKT_LEN - ISCSI_PDU_NONPAYLOAD_LEN);
  34. mdsl = min_t(u32, mdsl, 8192);
  35. mdsl = min_t(u32, mdsl, (MAX_SKB_FRAGS - 1) * PAGE_SIZE);
  36. cdev->mdsl = mdsl;
  37. }
  38. static void *cxgbit_uld_add(const struct cxgb4_lld_info *lldi)
  39. {
  40. struct cxgbit_device *cdev;
  41. if (is_t4(lldi->adapter_type))
  42. return ERR_PTR(-ENODEV);
  43. cdev = kzalloc(sizeof(*cdev), GFP_KERNEL);
  44. if (!cdev)
  45. return ERR_PTR(-ENOMEM);
  46. kref_init(&cdev->kref);
  47. cdev->lldi = *lldi;
  48. cxgbit_set_mdsl(cdev);
  49. if (cxgbit_ddp_init(cdev) < 0) {
  50. kfree(cdev);
  51. return ERR_PTR(-EINVAL);
  52. }
  53. if (!test_bit(CDEV_DDP_ENABLE, &cdev->flags))
  54. pr_info("cdev %s ddp init failed\n",
  55. pci_name(lldi->pdev));
  56. if (lldi->fw_vers >= 0x10d2b00)
  57. set_bit(CDEV_ISO_ENABLE, &cdev->flags);
  58. spin_lock_init(&cdev->cskq.lock);
  59. INIT_LIST_HEAD(&cdev->cskq.list);
  60. mutex_lock(&cdev_list_lock);
  61. list_add_tail(&cdev->list, &cdev_list_head);
  62. mutex_unlock(&cdev_list_lock);
  63. pr_info("cdev %s added for iSCSI target transport\n",
  64. pci_name(lldi->pdev));
  65. return cdev;
  66. }
  67. static void cxgbit_close_conn(struct cxgbit_device *cdev)
  68. {
  69. struct cxgbit_sock *csk;
  70. struct sk_buff *skb;
  71. bool wakeup_thread = false;
  72. spin_lock_bh(&cdev->cskq.lock);
  73. list_for_each_entry(csk, &cdev->cskq.list, list) {
  74. skb = alloc_skb(0, GFP_ATOMIC);
  75. if (!skb)
  76. continue;
  77. spin_lock_bh(&csk->rxq.lock);
  78. __skb_queue_tail(&csk->rxq, skb);
  79. if (skb_queue_len(&csk->rxq) == 1)
  80. wakeup_thread = true;
  81. spin_unlock_bh(&csk->rxq.lock);
  82. if (wakeup_thread) {
  83. wake_up(&csk->waitq);
  84. wakeup_thread = false;
  85. }
  86. }
  87. spin_unlock_bh(&cdev->cskq.lock);
  88. }
  89. static void cxgbit_detach_cdev(struct cxgbit_device *cdev)
  90. {
  91. bool free_cdev = false;
  92. spin_lock_bh(&cdev->cskq.lock);
  93. if (list_empty(&cdev->cskq.list))
  94. free_cdev = true;
  95. spin_unlock_bh(&cdev->cskq.lock);
  96. if (free_cdev) {
  97. mutex_lock(&cdev_list_lock);
  98. list_del(&cdev->list);
  99. mutex_unlock(&cdev_list_lock);
  100. cxgbit_put_cdev(cdev);
  101. } else {
  102. cxgbit_close_conn(cdev);
  103. }
  104. }
  105. static int cxgbit_uld_state_change(void *handle, enum cxgb4_state state)
  106. {
  107. struct cxgbit_device *cdev = handle;
  108. switch (state) {
  109. case CXGB4_STATE_UP:
  110. set_bit(CDEV_STATE_UP, &cdev->flags);
  111. pr_info("cdev %s state UP.\n", pci_name(cdev->lldi.pdev));
  112. break;
  113. case CXGB4_STATE_START_RECOVERY:
  114. clear_bit(CDEV_STATE_UP, &cdev->flags);
  115. cxgbit_close_conn(cdev);
  116. pr_info("cdev %s state RECOVERY.\n", pci_name(cdev->lldi.pdev));
  117. break;
  118. case CXGB4_STATE_DOWN:
  119. pr_info("cdev %s state DOWN.\n", pci_name(cdev->lldi.pdev));
  120. break;
  121. case CXGB4_STATE_DETACH:
  122. clear_bit(CDEV_STATE_UP, &cdev->flags);
  123. pr_info("cdev %s state DETACH.\n", pci_name(cdev->lldi.pdev));
  124. cxgbit_detach_cdev(cdev);
  125. break;
  126. default:
  127. pr_info("cdev %s unknown state %d.\n",
  128. pci_name(cdev->lldi.pdev), state);
  129. break;
  130. }
  131. return 0;
  132. }
  133. static void
  134. cxgbit_process_ddpvld(struct cxgbit_sock *csk, struct cxgbit_lro_pdu_cb *pdu_cb,
  135. u32 ddpvld)
  136. {
  137. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_HCRC_SHIFT)) {
  138. pr_info("tid 0x%x, status 0x%x, hcrc bad.\n", csk->tid, ddpvld);
  139. pdu_cb->flags |= PDUCBF_RX_HCRC_ERR;
  140. }
  141. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_DCRC_SHIFT)) {
  142. pr_info("tid 0x%x, status 0x%x, dcrc bad.\n", csk->tid, ddpvld);
  143. pdu_cb->flags |= PDUCBF_RX_DCRC_ERR;
  144. }
  145. if (ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_PAD_SHIFT))
  146. pr_info("tid 0x%x, status 0x%x, pad bad.\n", csk->tid, ddpvld);
  147. if ((ddpvld & (1 << CPL_RX_ISCSI_DDP_STATUS_DDP_SHIFT)) &&
  148. (!(pdu_cb->flags & PDUCBF_RX_DATA))) {
  149. pdu_cb->flags |= PDUCBF_RX_DATA_DDPD;
  150. }
  151. }
  152. static void
  153. cxgbit_lro_add_packet_rsp(struct sk_buff *skb, u8 op, const __be64 *rsp)
  154. {
  155. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  156. struct cxgbit_lro_pdu_cb *pdu_cb = cxgbit_skb_lro_pdu_cb(skb,
  157. lro_cb->pdu_idx);
  158. struct cpl_rx_iscsi_ddp *cpl = (struct cpl_rx_iscsi_ddp *)(rsp + 1);
  159. cxgbit_process_ddpvld(lro_cb->csk, pdu_cb, be32_to_cpu(cpl->ddpvld));
  160. pdu_cb->flags |= PDUCBF_RX_STATUS;
  161. pdu_cb->ddigest = ntohl(cpl->ulp_crc);
  162. pdu_cb->pdulen = ntohs(cpl->len);
  163. if (pdu_cb->flags & PDUCBF_RX_HDR)
  164. pdu_cb->complete = true;
  165. lro_cb->pdu_totallen += pdu_cb->pdulen;
  166. lro_cb->complete = true;
  167. lro_cb->pdu_idx++;
  168. }
  169. static void
  170. cxgbit_copy_frags(struct sk_buff *skb, const struct pkt_gl *gl,
  171. unsigned int offset)
  172. {
  173. u8 skb_frag_idx = skb_shinfo(skb)->nr_frags;
  174. u8 i;
  175. /* usually there's just one frag */
  176. __skb_fill_page_desc(skb, skb_frag_idx, gl->frags[0].page,
  177. gl->frags[0].offset + offset,
  178. gl->frags[0].size - offset);
  179. for (i = 1; i < gl->nfrags; i++)
  180. __skb_fill_page_desc(skb, skb_frag_idx + i,
  181. gl->frags[i].page,
  182. gl->frags[i].offset,
  183. gl->frags[i].size);
  184. skb_shinfo(skb)->nr_frags += gl->nfrags;
  185. /* get a reference to the last page, we don't own it */
  186. get_page(gl->frags[gl->nfrags - 1].page);
  187. }
  188. static void
  189. cxgbit_lro_add_packet_gl(struct sk_buff *skb, u8 op, const struct pkt_gl *gl)
  190. {
  191. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  192. struct cxgbit_lro_pdu_cb *pdu_cb = cxgbit_skb_lro_pdu_cb(skb,
  193. lro_cb->pdu_idx);
  194. u32 len, offset;
  195. if (op == CPL_ISCSI_HDR) {
  196. struct cpl_iscsi_hdr *cpl = (struct cpl_iscsi_hdr *)gl->va;
  197. offset = sizeof(struct cpl_iscsi_hdr);
  198. pdu_cb->flags |= PDUCBF_RX_HDR;
  199. pdu_cb->seq = ntohl(cpl->seq);
  200. len = ntohs(cpl->len);
  201. pdu_cb->hdr = gl->va + offset;
  202. pdu_cb->hlen = len;
  203. pdu_cb->hfrag_idx = skb_shinfo(skb)->nr_frags;
  204. if (unlikely(gl->nfrags > 1))
  205. cxgbit_skcb_flags(skb) = 0;
  206. lro_cb->complete = false;
  207. } else if (op == CPL_ISCSI_DATA) {
  208. struct cpl_iscsi_data *cpl = (struct cpl_iscsi_data *)gl->va;
  209. offset = sizeof(struct cpl_iscsi_data);
  210. pdu_cb->flags |= PDUCBF_RX_DATA;
  211. len = ntohs(cpl->len);
  212. pdu_cb->dlen = len;
  213. pdu_cb->doffset = lro_cb->offset;
  214. pdu_cb->nr_dfrags = gl->nfrags;
  215. pdu_cb->dfrag_idx = skb_shinfo(skb)->nr_frags;
  216. lro_cb->complete = false;
  217. } else {
  218. struct cpl_rx_iscsi_cmp *cpl;
  219. cpl = (struct cpl_rx_iscsi_cmp *)gl->va;
  220. offset = sizeof(struct cpl_rx_iscsi_cmp);
  221. pdu_cb->flags |= (PDUCBF_RX_HDR | PDUCBF_RX_STATUS);
  222. len = be16_to_cpu(cpl->len);
  223. pdu_cb->hdr = gl->va + offset;
  224. pdu_cb->hlen = len;
  225. pdu_cb->hfrag_idx = skb_shinfo(skb)->nr_frags;
  226. pdu_cb->ddigest = be32_to_cpu(cpl->ulp_crc);
  227. pdu_cb->pdulen = ntohs(cpl->len);
  228. if (unlikely(gl->nfrags > 1))
  229. cxgbit_skcb_flags(skb) = 0;
  230. cxgbit_process_ddpvld(lro_cb->csk, pdu_cb,
  231. be32_to_cpu(cpl->ddpvld));
  232. if (pdu_cb->flags & PDUCBF_RX_DATA_DDPD) {
  233. pdu_cb->flags |= PDUCBF_RX_DDP_CMP;
  234. pdu_cb->complete = true;
  235. } else if (pdu_cb->flags & PDUCBF_RX_DATA) {
  236. pdu_cb->complete = true;
  237. }
  238. lro_cb->pdu_totallen += pdu_cb->hlen + pdu_cb->dlen;
  239. lro_cb->complete = true;
  240. lro_cb->pdu_idx++;
  241. }
  242. cxgbit_copy_frags(skb, gl, offset);
  243. pdu_cb->frags += gl->nfrags;
  244. lro_cb->offset += len;
  245. skb->len += len;
  246. skb->data_len += len;
  247. skb->truesize += len;
  248. }
  249. static struct sk_buff *
  250. cxgbit_lro_init_skb(struct cxgbit_sock *csk, u8 op, const struct pkt_gl *gl,
  251. const __be64 *rsp, struct napi_struct *napi)
  252. {
  253. struct sk_buff *skb;
  254. struct cxgbit_lro_cb *lro_cb;
  255. skb = napi_alloc_skb(napi, LRO_SKB_MAX_HEADROOM);
  256. if (unlikely(!skb))
  257. return NULL;
  258. memset(skb->data, 0, LRO_SKB_MAX_HEADROOM);
  259. cxgbit_skcb_flags(skb) |= SKCBF_RX_LRO;
  260. lro_cb = cxgbit_skb_lro_cb(skb);
  261. cxgbit_get_csk(csk);
  262. lro_cb->csk = csk;
  263. return skb;
  264. }
  265. static void cxgbit_queue_lro_skb(struct cxgbit_sock *csk, struct sk_buff *skb)
  266. {
  267. bool wakeup_thread = false;
  268. spin_lock(&csk->rxq.lock);
  269. __skb_queue_tail(&csk->rxq, skb);
  270. if (skb_queue_len(&csk->rxq) == 1)
  271. wakeup_thread = true;
  272. spin_unlock(&csk->rxq.lock);
  273. if (wakeup_thread)
  274. wake_up(&csk->waitq);
  275. }
  276. static void cxgbit_lro_flush(struct t4_lro_mgr *lro_mgr, struct sk_buff *skb)
  277. {
  278. struct cxgbit_lro_cb *lro_cb = cxgbit_skb_lro_cb(skb);
  279. struct cxgbit_sock *csk = lro_cb->csk;
  280. csk->lro_skb = NULL;
  281. __skb_unlink(skb, &lro_mgr->lroq);
  282. cxgbit_queue_lro_skb(csk, skb);
  283. cxgbit_put_csk(csk);
  284. lro_mgr->lro_pkts++;
  285. lro_mgr->lro_session_cnt--;
  286. }
  287. static void cxgbit_uld_lro_flush(struct t4_lro_mgr *lro_mgr)
  288. {
  289. struct sk_buff *skb;
  290. while ((skb = skb_peek(&lro_mgr->lroq)))
  291. cxgbit_lro_flush(lro_mgr, skb);
  292. }
  293. static int
  294. cxgbit_lro_receive(struct cxgbit_sock *csk, u8 op, const __be64 *rsp,
  295. const struct pkt_gl *gl, struct t4_lro_mgr *lro_mgr,
  296. struct napi_struct *napi)
  297. {
  298. struct sk_buff *skb;
  299. struct cxgbit_lro_cb *lro_cb;
  300. if (!csk) {
  301. pr_err("%s: csk NULL, op 0x%x.\n", __func__, op);
  302. goto out;
  303. }
  304. if (csk->lro_skb)
  305. goto add_packet;
  306. start_lro:
  307. if (lro_mgr->lro_session_cnt >= MAX_LRO_SESSIONS) {
  308. cxgbit_uld_lro_flush(lro_mgr);
  309. goto start_lro;
  310. }
  311. skb = cxgbit_lro_init_skb(csk, op, gl, rsp, napi);
  312. if (unlikely(!skb))
  313. goto out;
  314. csk->lro_skb = skb;
  315. __skb_queue_tail(&lro_mgr->lroq, skb);
  316. lro_mgr->lro_session_cnt++;
  317. add_packet:
  318. skb = csk->lro_skb;
  319. lro_cb = cxgbit_skb_lro_cb(skb);
  320. if ((gl && (((skb_shinfo(skb)->nr_frags + gl->nfrags) >
  321. MAX_SKB_FRAGS) || (lro_cb->pdu_totallen >= LRO_FLUSH_LEN_MAX))) ||
  322. (lro_cb->pdu_idx >= MAX_SKB_FRAGS)) {
  323. cxgbit_lro_flush(lro_mgr, skb);
  324. goto start_lro;
  325. }
  326. if (gl)
  327. cxgbit_lro_add_packet_gl(skb, op, gl);
  328. else
  329. cxgbit_lro_add_packet_rsp(skb, op, rsp);
  330. lro_mgr->lro_merged++;
  331. return 0;
  332. out:
  333. return -1;
  334. }
  335. static int
  336. cxgbit_uld_lro_rx_handler(void *hndl, const __be64 *rsp,
  337. const struct pkt_gl *gl, struct t4_lro_mgr *lro_mgr,
  338. struct napi_struct *napi)
  339. {
  340. struct cxgbit_device *cdev = hndl;
  341. struct cxgb4_lld_info *lldi = &cdev->lldi;
  342. struct cpl_tx_data *rpl = NULL;
  343. struct cxgbit_sock *csk = NULL;
  344. unsigned int tid = 0;
  345. struct sk_buff *skb;
  346. unsigned int op = *(u8 *)rsp;
  347. bool lro_flush = true;
  348. switch (op) {
  349. case CPL_ISCSI_HDR:
  350. case CPL_ISCSI_DATA:
  351. case CPL_RX_ISCSI_CMP:
  352. case CPL_RX_ISCSI_DDP:
  353. case CPL_FW4_ACK:
  354. lro_flush = false;
  355. case CPL_ABORT_RPL_RSS:
  356. case CPL_PASS_ESTABLISH:
  357. case CPL_PEER_CLOSE:
  358. case CPL_CLOSE_CON_RPL:
  359. case CPL_ABORT_REQ_RSS:
  360. case CPL_SET_TCB_RPL:
  361. case CPL_RX_DATA:
  362. rpl = gl ? (struct cpl_tx_data *)gl->va :
  363. (struct cpl_tx_data *)(rsp + 1);
  364. tid = GET_TID(rpl);
  365. csk = lookup_tid(lldi->tids, tid);
  366. break;
  367. default:
  368. break;
  369. }
  370. if (csk && csk->lro_skb && lro_flush)
  371. cxgbit_lro_flush(lro_mgr, csk->lro_skb);
  372. if (!gl) {
  373. unsigned int len;
  374. if (op == CPL_RX_ISCSI_DDP) {
  375. if (!cxgbit_lro_receive(csk, op, rsp, NULL, lro_mgr,
  376. napi))
  377. return 0;
  378. }
  379. len = 64 - sizeof(struct rsp_ctrl) - 8;
  380. skb = napi_alloc_skb(napi, len);
  381. if (!skb)
  382. goto nomem;
  383. __skb_put(skb, len);
  384. skb_copy_to_linear_data(skb, &rsp[1], len);
  385. } else {
  386. if (unlikely(op != *(u8 *)gl->va)) {
  387. pr_info("? FL 0x%p,RSS%#llx,FL %#llx,len %u.\n",
  388. gl->va, be64_to_cpu(*rsp),
  389. get_unaligned_be64(gl->va),
  390. gl->tot_len);
  391. return 0;
  392. }
  393. if ((op == CPL_ISCSI_HDR) || (op == CPL_ISCSI_DATA) ||
  394. (op == CPL_RX_ISCSI_CMP)) {
  395. if (!cxgbit_lro_receive(csk, op, rsp, gl, lro_mgr,
  396. napi))
  397. return 0;
  398. }
  399. #define RX_PULL_LEN 128
  400. skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
  401. if (unlikely(!skb))
  402. goto nomem;
  403. }
  404. rpl = (struct cpl_tx_data *)skb->data;
  405. op = rpl->ot.opcode;
  406. cxgbit_skcb_rx_opcode(skb) = op;
  407. pr_debug("cdev %p, opcode 0x%x(0x%x,0x%x), skb %p.\n",
  408. cdev, op, rpl->ot.opcode_tid,
  409. ntohl(rpl->ot.opcode_tid), skb);
  410. if (op < NUM_CPL_CMDS && cxgbit_cplhandlers[op]) {
  411. cxgbit_cplhandlers[op](cdev, skb);
  412. } else {
  413. pr_err("No handler for opcode 0x%x.\n", op);
  414. __kfree_skb(skb);
  415. }
  416. return 0;
  417. nomem:
  418. pr_err("%s OOM bailing out.\n", __func__);
  419. return 1;
  420. }
  421. #ifdef CONFIG_CHELSIO_T4_DCB
  422. struct cxgbit_dcb_work {
  423. struct dcb_app_type dcb_app;
  424. struct work_struct work;
  425. };
  426. static void
  427. cxgbit_update_dcb_priority(struct cxgbit_device *cdev, u8 port_id,
  428. u8 dcb_priority, u16 port_num)
  429. {
  430. struct cxgbit_sock *csk;
  431. struct sk_buff *skb;
  432. u16 local_port;
  433. bool wakeup_thread = false;
  434. spin_lock_bh(&cdev->cskq.lock);
  435. list_for_each_entry(csk, &cdev->cskq.list, list) {
  436. if (csk->port_id != port_id)
  437. continue;
  438. if (csk->com.local_addr.ss_family == AF_INET6) {
  439. struct sockaddr_in6 *sock_in6;
  440. sock_in6 = (struct sockaddr_in6 *)&csk->com.local_addr;
  441. local_port = ntohs(sock_in6->sin6_port);
  442. } else {
  443. struct sockaddr_in *sock_in;
  444. sock_in = (struct sockaddr_in *)&csk->com.local_addr;
  445. local_port = ntohs(sock_in->sin_port);
  446. }
  447. if (local_port != port_num)
  448. continue;
  449. if (csk->dcb_priority == dcb_priority)
  450. continue;
  451. skb = alloc_skb(0, GFP_ATOMIC);
  452. if (!skb)
  453. continue;
  454. spin_lock(&csk->rxq.lock);
  455. __skb_queue_tail(&csk->rxq, skb);
  456. if (skb_queue_len(&csk->rxq) == 1)
  457. wakeup_thread = true;
  458. spin_unlock(&csk->rxq.lock);
  459. if (wakeup_thread) {
  460. wake_up(&csk->waitq);
  461. wakeup_thread = false;
  462. }
  463. }
  464. spin_unlock_bh(&cdev->cskq.lock);
  465. }
  466. static void cxgbit_dcb_workfn(struct work_struct *work)
  467. {
  468. struct cxgbit_dcb_work *dcb_work;
  469. struct net_device *ndev;
  470. struct cxgbit_device *cdev = NULL;
  471. struct dcb_app_type *iscsi_app;
  472. u8 priority, port_id = 0xff;
  473. dcb_work = container_of(work, struct cxgbit_dcb_work, work);
  474. iscsi_app = &dcb_work->dcb_app;
  475. if (iscsi_app->dcbx & DCB_CAP_DCBX_VER_IEEE) {
  476. if (iscsi_app->app.selector != IEEE_8021QAZ_APP_SEL_ANY)
  477. goto out;
  478. priority = iscsi_app->app.priority;
  479. } else if (iscsi_app->dcbx & DCB_CAP_DCBX_VER_CEE) {
  480. if (iscsi_app->app.selector != DCB_APP_IDTYPE_PORTNUM)
  481. goto out;
  482. if (!iscsi_app->app.priority)
  483. goto out;
  484. priority = ffs(iscsi_app->app.priority) - 1;
  485. } else {
  486. goto out;
  487. }
  488. pr_debug("priority for ifid %d is %u\n",
  489. iscsi_app->ifindex, priority);
  490. ndev = dev_get_by_index(&init_net, iscsi_app->ifindex);
  491. if (!ndev)
  492. goto out;
  493. mutex_lock(&cdev_list_lock);
  494. cdev = cxgbit_find_device(ndev, &port_id);
  495. dev_put(ndev);
  496. if (!cdev) {
  497. mutex_unlock(&cdev_list_lock);
  498. goto out;
  499. }
  500. cxgbit_update_dcb_priority(cdev, port_id, priority,
  501. iscsi_app->app.protocol);
  502. mutex_unlock(&cdev_list_lock);
  503. out:
  504. kfree(dcb_work);
  505. }
  506. static int
  507. cxgbit_dcbevent_notify(struct notifier_block *nb, unsigned long action,
  508. void *data)
  509. {
  510. struct cxgbit_dcb_work *dcb_work;
  511. struct dcb_app_type *dcb_app = data;
  512. dcb_work = kzalloc(sizeof(*dcb_work), GFP_ATOMIC);
  513. if (!dcb_work)
  514. return NOTIFY_DONE;
  515. dcb_work->dcb_app = *dcb_app;
  516. INIT_WORK(&dcb_work->work, cxgbit_dcb_workfn);
  517. schedule_work(&dcb_work->work);
  518. return NOTIFY_OK;
  519. }
  520. #endif
  521. static enum target_prot_op cxgbit_get_sup_prot_ops(struct iscsi_conn *conn)
  522. {
  523. return TARGET_PROT_NORMAL;
  524. }
  525. static struct iscsit_transport cxgbit_transport = {
  526. .name = DRV_NAME,
  527. .transport_type = ISCSI_CXGBIT,
  528. .rdma_shutdown = false,
  529. .priv_size = sizeof(struct cxgbit_cmd),
  530. .owner = THIS_MODULE,
  531. .iscsit_setup_np = cxgbit_setup_np,
  532. .iscsit_accept_np = cxgbit_accept_np,
  533. .iscsit_free_np = cxgbit_free_np,
  534. .iscsit_free_conn = cxgbit_free_conn,
  535. .iscsit_get_login_rx = cxgbit_get_login_rx,
  536. .iscsit_put_login_tx = cxgbit_put_login_tx,
  537. .iscsit_immediate_queue = iscsit_immediate_queue,
  538. .iscsit_response_queue = iscsit_response_queue,
  539. .iscsit_get_dataout = iscsit_build_r2ts_for_cmd,
  540. .iscsit_queue_data_in = iscsit_queue_rsp,
  541. .iscsit_queue_status = iscsit_queue_rsp,
  542. .iscsit_xmit_pdu = cxgbit_xmit_pdu,
  543. .iscsit_get_r2t_ttt = cxgbit_get_r2t_ttt,
  544. .iscsit_get_rx_pdu = cxgbit_get_rx_pdu,
  545. .iscsit_validate_params = cxgbit_validate_params,
  546. .iscsit_release_cmd = cxgbit_release_cmd,
  547. .iscsit_aborted_task = iscsit_aborted_task,
  548. .iscsit_get_sup_prot_ops = cxgbit_get_sup_prot_ops,
  549. };
  550. static struct cxgb4_uld_info cxgbit_uld_info = {
  551. .name = DRV_NAME,
  552. .nrxq = MAX_ULD_QSETS,
  553. .ntxq = MAX_ULD_QSETS,
  554. .rxq_size = 1024,
  555. .lro = true,
  556. .add = cxgbit_uld_add,
  557. .state_change = cxgbit_uld_state_change,
  558. .lro_rx_handler = cxgbit_uld_lro_rx_handler,
  559. .lro_flush = cxgbit_uld_lro_flush,
  560. };
  561. #ifdef CONFIG_CHELSIO_T4_DCB
  562. static struct notifier_block cxgbit_dcbevent_nb = {
  563. .notifier_call = cxgbit_dcbevent_notify,
  564. };
  565. #endif
  566. static int __init cxgbit_init(void)
  567. {
  568. cxgb4_register_uld(CXGB4_ULD_ISCSIT, &cxgbit_uld_info);
  569. iscsit_register_transport(&cxgbit_transport);
  570. #ifdef CONFIG_CHELSIO_T4_DCB
  571. pr_info("%s dcb enabled.\n", DRV_NAME);
  572. register_dcbevent_notifier(&cxgbit_dcbevent_nb);
  573. #endif
  574. BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, cb) <
  575. sizeof(union cxgbit_skb_cb));
  576. return 0;
  577. }
  578. static void __exit cxgbit_exit(void)
  579. {
  580. struct cxgbit_device *cdev, *tmp;
  581. #ifdef CONFIG_CHELSIO_T4_DCB
  582. unregister_dcbevent_notifier(&cxgbit_dcbevent_nb);
  583. #endif
  584. mutex_lock(&cdev_list_lock);
  585. list_for_each_entry_safe(cdev, tmp, &cdev_list_head, list) {
  586. list_del(&cdev->list);
  587. cxgbit_put_cdev(cdev);
  588. }
  589. mutex_unlock(&cdev_list_lock);
  590. iscsit_unregister_transport(&cxgbit_transport);
  591. cxgb4_unregister_uld(CXGB4_ULD_ISCSIT);
  592. }
  593. module_init(cxgbit_init);
  594. module_exit(cxgbit_exit);
  595. MODULE_DESCRIPTION("Chelsio iSCSI target offload driver");
  596. MODULE_AUTHOR("Chelsio Communications");
  597. MODULE_VERSION(DRV_VERSION);
  598. MODULE_LICENSE("GPL");