halbtc8192e2ant.c 102 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. /**************************************************************
  26. * Description:
  27. *
  28. * This file is for RTL8192E Co-exist mechanism
  29. *
  30. * History
  31. * 2012/11/15 Cosa first check in.
  32. *
  33. **************************************************************/
  34. /**************************************************************
  35. * include files
  36. **************************************************************/
  37. #include "halbt_precomp.h"
  38. /**************************************************************
  39. * Global variables, these are static variables
  40. **************************************************************/
  41. static struct coex_dm_8192e_2ant glcoex_dm_8192e_2ant;
  42. static struct coex_dm_8192e_2ant *coex_dm = &glcoex_dm_8192e_2ant;
  43. static struct coex_sta_8192e_2ant glcoex_sta_8192e_2ant;
  44. static struct coex_sta_8192e_2ant *coex_sta = &glcoex_sta_8192e_2ant;
  45. static const char *const glbt_info_src_8192e_2ant[] = {
  46. "BT Info[wifi fw]",
  47. "BT Info[bt rsp]",
  48. "BT Info[bt auto report]",
  49. };
  50. static u32 glcoex_ver_date_8192e_2ant = 20130902;
  51. static u32 glcoex_ver_8192e_2ant = 0x34;
  52. /**************************************************************
  53. * local function proto type if needed
  54. **************************************************************/
  55. /**************************************************************
  56. * local function start with btc8192e2ant_
  57. **************************************************************/
  58. static u8 btc8192e2ant_bt_rssi_state(struct btc_coexist *btcoexist,
  59. u8 level_num, u8 rssi_thresh,
  60. u8 rssi_thresh1)
  61. {
  62. struct rtl_priv *rtlpriv = btcoexist->adapter;
  63. int bt_rssi = 0;
  64. u8 bt_rssi_state = coex_sta->pre_bt_rssi_state;
  65. bt_rssi = coex_sta->bt_rssi;
  66. if (level_num == 2) {
  67. if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  68. (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  69. if (bt_rssi >=
  70. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  71. bt_rssi_state = BTC_RSSI_STATE_HIGH;
  72. else
  73. bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  74. } else {
  75. if (bt_rssi < rssi_thresh)
  76. bt_rssi_state = BTC_RSSI_STATE_LOW;
  77. else
  78. bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  79. }
  80. } else if (level_num == 3) {
  81. if (rssi_thresh > rssi_thresh1) {
  82. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  83. "[BTCoex], BT Rssi thresh error!!\n");
  84. return coex_sta->pre_bt_rssi_state;
  85. }
  86. if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  87. (coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  88. if (bt_rssi >=
  89. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  90. bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
  91. else
  92. bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  93. } else if ((coex_sta->pre_bt_rssi_state ==
  94. BTC_RSSI_STATE_MEDIUM) ||
  95. (coex_sta->pre_bt_rssi_state ==
  96. BTC_RSSI_STATE_STAY_MEDIUM)) {
  97. if (bt_rssi >= (rssi_thresh1 +
  98. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  99. bt_rssi_state = BTC_RSSI_STATE_HIGH;
  100. else if (bt_rssi < rssi_thresh)
  101. bt_rssi_state = BTC_RSSI_STATE_LOW;
  102. else
  103. bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
  104. } else {
  105. if (bt_rssi < rssi_thresh1)
  106. bt_rssi_state = BTC_RSSI_STATE_MEDIUM;
  107. else
  108. bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  109. }
  110. }
  111. coex_sta->pre_bt_rssi_state = bt_rssi_state;
  112. return bt_rssi_state;
  113. }
  114. static u8 btc8192e2ant_wifi_rssi_state(struct btc_coexist *btcoexist,
  115. u8 index, u8 level_num, u8 rssi_thresh,
  116. u8 rssi_thresh1)
  117. {
  118. struct rtl_priv *rtlpriv = btcoexist->adapter;
  119. int wifi_rssi = 0;
  120. u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index];
  121. btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
  122. if (level_num == 2) {
  123. if ((coex_sta->pre_wifi_rssi_state[index] ==
  124. BTC_RSSI_STATE_LOW) ||
  125. (coex_sta->pre_wifi_rssi_state[index] ==
  126. BTC_RSSI_STATE_STAY_LOW)) {
  127. if (wifi_rssi >=
  128. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  129. wifi_rssi_state = BTC_RSSI_STATE_HIGH;
  130. else
  131. wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  132. } else {
  133. if (wifi_rssi < rssi_thresh)
  134. wifi_rssi_state = BTC_RSSI_STATE_LOW;
  135. else
  136. wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  137. }
  138. } else if (level_num == 3) {
  139. if (rssi_thresh > rssi_thresh1) {
  140. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  141. "[BTCoex], wifi RSSI thresh error!!\n");
  142. return coex_sta->pre_wifi_rssi_state[index];
  143. }
  144. if ((coex_sta->pre_wifi_rssi_state[index] ==
  145. BTC_RSSI_STATE_LOW) ||
  146. (coex_sta->pre_wifi_rssi_state[index] ==
  147. BTC_RSSI_STATE_STAY_LOW)) {
  148. if (wifi_rssi >=
  149. (rssi_thresh + BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  150. wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
  151. else
  152. wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  153. } else if ((coex_sta->pre_wifi_rssi_state[index] ==
  154. BTC_RSSI_STATE_MEDIUM) ||
  155. (coex_sta->pre_wifi_rssi_state[index] ==
  156. BTC_RSSI_STATE_STAY_MEDIUM)) {
  157. if (wifi_rssi >= (rssi_thresh1 +
  158. BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT))
  159. wifi_rssi_state = BTC_RSSI_STATE_HIGH;
  160. else if (wifi_rssi < rssi_thresh)
  161. wifi_rssi_state = BTC_RSSI_STATE_LOW;
  162. else
  163. wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM;
  164. } else {
  165. if (wifi_rssi < rssi_thresh1)
  166. wifi_rssi_state = BTC_RSSI_STATE_MEDIUM;
  167. else
  168. wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH;
  169. }
  170. }
  171. coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state;
  172. return wifi_rssi_state;
  173. }
  174. static void btc8192e2ant_monitor_bt_enable_disable(struct btc_coexist
  175. *btcoexist)
  176. {
  177. struct rtl_priv *rtlpriv = btcoexist->adapter;
  178. static bool pre_bt_disabled;
  179. static u32 bt_disable_cnt;
  180. bool bt_active = true, bt_disabled = false;
  181. /* This function check if bt is disabled */
  182. if (coex_sta->high_priority_tx == 0 &&
  183. coex_sta->high_priority_rx == 0 &&
  184. coex_sta->low_priority_tx == 0 &&
  185. coex_sta->low_priority_rx == 0)
  186. bt_active = false;
  187. if (coex_sta->high_priority_tx == 0xffff &&
  188. coex_sta->high_priority_rx == 0xffff &&
  189. coex_sta->low_priority_tx == 0xffff &&
  190. coex_sta->low_priority_rx == 0xffff)
  191. bt_active = false;
  192. if (bt_active) {
  193. bt_disable_cnt = 0;
  194. bt_disabled = false;
  195. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
  196. &bt_disabled);
  197. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  198. "[BTCoex], BT is enabled !!\n");
  199. } else {
  200. bt_disable_cnt++;
  201. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  202. "[BTCoex], bt all counters = 0, %d times!!\n",
  203. bt_disable_cnt);
  204. if (bt_disable_cnt >= 2) {
  205. bt_disabled = true;
  206. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE,
  207. &bt_disabled);
  208. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  209. "[BTCoex], BT is disabled !!\n");
  210. }
  211. }
  212. if (pre_bt_disabled != bt_disabled) {
  213. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  214. "[BTCoex], BT is from %s to %s!!\n",
  215. (pre_bt_disabled ? "disabled" : "enabled"),
  216. (bt_disabled ? "disabled" : "enabled"));
  217. pre_bt_disabled = bt_disabled;
  218. }
  219. }
  220. static u32 btc8192e2ant_decide_ra_mask(struct btc_coexist *btcoexist,
  221. u8 ss_type, u32 ra_mask_type)
  222. {
  223. u32 dis_ra_mask = 0x0;
  224. switch (ra_mask_type) {
  225. case 0: /* normal mode */
  226. if (ss_type == 2)
  227. dis_ra_mask = 0x0; /* enable 2ss */
  228. else
  229. dis_ra_mask = 0xfff00000; /* disable 2ss */
  230. break;
  231. case 1: /* disable cck 1/2 */
  232. if (ss_type == 2)
  233. dis_ra_mask = 0x00000003; /* enable 2ss */
  234. else
  235. dis_ra_mask = 0xfff00003; /* disable 2ss */
  236. break;
  237. case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */
  238. if (ss_type == 2)
  239. dis_ra_mask = 0x0001f1f7; /* enable 2ss */
  240. else
  241. dis_ra_mask = 0xfff1f1f7; /* disable 2ss */
  242. break;
  243. default:
  244. break;
  245. }
  246. return dis_ra_mask;
  247. }
  248. static void btc8192e2ant_update_ra_mask(struct btc_coexist *btcoexist,
  249. bool force_exec, u32 dis_rate_mask)
  250. {
  251. coex_dm->cur_ra_mask = dis_rate_mask;
  252. if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask))
  253. btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK,
  254. &coex_dm->cur_ra_mask);
  255. coex_dm->pre_ra_mask = coex_dm->cur_ra_mask;
  256. }
  257. static void btc8192e2ant_auto_rate_fallback_retry(struct btc_coexist *btcoexist,
  258. bool force_exec, u8 type)
  259. {
  260. bool wifi_under_b_mode = false;
  261. coex_dm->cur_arfr_type = type;
  262. if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) {
  263. switch (coex_dm->cur_arfr_type) {
  264. case 0: /* normal mode */
  265. btcoexist->btc_write_4byte(btcoexist, 0x430,
  266. coex_dm->backup_arfr_cnt1);
  267. btcoexist->btc_write_4byte(btcoexist, 0x434,
  268. coex_dm->backup_arfr_cnt2);
  269. break;
  270. case 1:
  271. btcoexist->btc_get(btcoexist,
  272. BTC_GET_BL_WIFI_UNDER_B_MODE,
  273. &wifi_under_b_mode);
  274. if (wifi_under_b_mode) {
  275. btcoexist->btc_write_4byte(btcoexist, 0x430,
  276. 0x0);
  277. btcoexist->btc_write_4byte(btcoexist, 0x434,
  278. 0x01010101);
  279. } else {
  280. btcoexist->btc_write_4byte(btcoexist, 0x430,
  281. 0x0);
  282. btcoexist->btc_write_4byte(btcoexist, 0x434,
  283. 0x04030201);
  284. }
  285. break;
  286. default:
  287. break;
  288. }
  289. }
  290. coex_dm->pre_arfr_type = coex_dm->cur_arfr_type;
  291. }
  292. static void btc8192e2ant_retry_limit(struct btc_coexist *btcoexist,
  293. bool force_exec, u8 type)
  294. {
  295. coex_dm->cur_retry_limit_type = type;
  296. if (force_exec || (coex_dm->pre_retry_limit_type !=
  297. coex_dm->cur_retry_limit_type)) {
  298. switch (coex_dm->cur_retry_limit_type) {
  299. case 0: /* normal mode */
  300. btcoexist->btc_write_2byte(btcoexist, 0x42a,
  301. coex_dm->backup_retry_limit);
  302. break;
  303. case 1: /* retry limit = 8 */
  304. btcoexist->btc_write_2byte(btcoexist, 0x42a, 0x0808);
  305. break;
  306. default:
  307. break;
  308. }
  309. }
  310. coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type;
  311. }
  312. static void btc8192e2ant_ampdu_maxtime(struct btc_coexist *btcoexist,
  313. bool force_exec, u8 type)
  314. {
  315. coex_dm->cur_ampdu_time_type = type;
  316. if (force_exec || (coex_dm->pre_ampdu_time_type !=
  317. coex_dm->cur_ampdu_time_type)) {
  318. switch (coex_dm->cur_ampdu_time_type) {
  319. case 0: /* normal mode */
  320. btcoexist->btc_write_1byte(btcoexist, 0x456,
  321. coex_dm->backup_ampdu_maxtime);
  322. break;
  323. case 1: /* AMPDU time = 0x38 * 32us */
  324. btcoexist->btc_write_1byte(btcoexist, 0x456, 0x38);
  325. break;
  326. default:
  327. break;
  328. }
  329. }
  330. coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type;
  331. }
  332. static void btc8192e2ant_limited_tx(struct btc_coexist *btcoexist,
  333. bool force_exec, u8 ra_mask_type,
  334. u8 arfr_type, u8 retry_limit_type,
  335. u8 ampdu_time_type)
  336. {
  337. u32 dis_ra_mask = 0x0;
  338. coex_dm->cur_ra_mask_type = ra_mask_type;
  339. dis_ra_mask =
  340. btc8192e2ant_decide_ra_mask(btcoexist, coex_dm->cur_ss_type,
  341. ra_mask_type);
  342. btc8192e2ant_update_ra_mask(btcoexist, force_exec, dis_ra_mask);
  343. btc8192e2ant_auto_rate_fallback_retry(btcoexist, force_exec, arfr_type);
  344. btc8192e2ant_retry_limit(btcoexist, force_exec, retry_limit_type);
  345. btc8192e2ant_ampdu_maxtime(btcoexist, force_exec, ampdu_time_type);
  346. }
  347. static void btc8192e2ant_limited_rx(struct btc_coexist *btcoexist,
  348. bool force_exec, bool rej_ap_agg_pkt,
  349. bool bt_ctrl_agg_buf_size,
  350. u8 agg_buf_size)
  351. {
  352. bool reject_rx_agg = rej_ap_agg_pkt;
  353. bool bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size;
  354. u8 rx_agg_size = agg_buf_size;
  355. /*********************************************
  356. * Rx Aggregation related setting
  357. *********************************************/
  358. btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT,
  359. &reject_rx_agg);
  360. /* decide BT control aggregation buf size or not */
  361. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE,
  362. &bt_ctrl_rx_agg_size);
  363. /* aggregation buf size, only work
  364. * when BT control Rx aggregation size.
  365. */
  366. btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size);
  367. /* real update aggregation setting */
  368. btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
  369. }
  370. static void btc8192e2ant_monitor_bt_ctr(struct btc_coexist *btcoexist)
  371. {
  372. struct rtl_priv *rtlpriv = btcoexist->adapter;
  373. u32 reg_hp_txrx, reg_lp_txrx, u32tmp;
  374. u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0;
  375. reg_hp_txrx = 0x770;
  376. reg_lp_txrx = 0x774;
  377. u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx);
  378. reg_hp_tx = u32tmp & MASKLWORD;
  379. reg_hp_rx = (u32tmp & MASKHWORD) >> 16;
  380. u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx);
  381. reg_lp_tx = u32tmp & MASKLWORD;
  382. reg_lp_rx = (u32tmp & MASKHWORD) >> 16;
  383. coex_sta->high_priority_tx = reg_hp_tx;
  384. coex_sta->high_priority_rx = reg_hp_rx;
  385. coex_sta->low_priority_tx = reg_lp_tx;
  386. coex_sta->low_priority_rx = reg_lp_rx;
  387. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  388. "[BTCoex] High Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
  389. reg_hp_txrx, reg_hp_tx, reg_hp_tx, reg_hp_rx, reg_hp_rx);
  390. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  391. "[BTCoex] Low Priority Tx/Rx (reg 0x%x) = 0x%x(%d)/0x%x(%d)\n",
  392. reg_lp_txrx, reg_lp_tx, reg_lp_tx, reg_lp_rx, reg_lp_rx);
  393. /* reset counter */
  394. btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc);
  395. }
  396. static void btc8192e2ant_query_bt_info(struct btc_coexist *btcoexist)
  397. {
  398. struct rtl_priv *rtlpriv = btcoexist->adapter;
  399. u8 h2c_parameter[1] = {0};
  400. coex_sta->c2h_bt_info_req_sent = true;
  401. h2c_parameter[0] |= BIT0; /* trigger */
  402. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  403. "[BTCoex], Query Bt Info, FW write 0x61 = 0x%x\n",
  404. h2c_parameter[0]);
  405. btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter);
  406. }
  407. static void btc8192e2ant_update_bt_link_info(struct btc_coexist *btcoexist)
  408. {
  409. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  410. bool bt_hs_on = false;
  411. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  412. bt_link_info->bt_link_exist = coex_sta->bt_link_exist;
  413. bt_link_info->sco_exist = coex_sta->sco_exist;
  414. bt_link_info->a2dp_exist = coex_sta->a2dp_exist;
  415. bt_link_info->pan_exist = coex_sta->pan_exist;
  416. bt_link_info->hid_exist = coex_sta->hid_exist;
  417. /* work around for HS mode. */
  418. if (bt_hs_on) {
  419. bt_link_info->pan_exist = true;
  420. bt_link_info->bt_link_exist = true;
  421. }
  422. /* check if Sco only */
  423. if (bt_link_info->sco_exist &&
  424. !bt_link_info->a2dp_exist &&
  425. !bt_link_info->pan_exist &&
  426. !bt_link_info->hid_exist)
  427. bt_link_info->sco_only = true;
  428. else
  429. bt_link_info->sco_only = false;
  430. /* check if A2dp only */
  431. if (!bt_link_info->sco_exist &&
  432. bt_link_info->a2dp_exist &&
  433. !bt_link_info->pan_exist &&
  434. !bt_link_info->hid_exist)
  435. bt_link_info->a2dp_only = true;
  436. else
  437. bt_link_info->a2dp_only = false;
  438. /* check if Pan only */
  439. if (!bt_link_info->sco_exist &&
  440. !bt_link_info->a2dp_exist &&
  441. bt_link_info->pan_exist &&
  442. !bt_link_info->hid_exist)
  443. bt_link_info->pan_only = true;
  444. else
  445. bt_link_info->pan_only = false;
  446. /* check if Hid only */
  447. if (!bt_link_info->sco_exist &&
  448. !bt_link_info->a2dp_exist &&
  449. !bt_link_info->pan_exist &&
  450. bt_link_info->hid_exist)
  451. bt_link_info->hid_only = true;
  452. else
  453. bt_link_info->hid_only = false;
  454. }
  455. static u8 btc8192e2ant_action_algorithm(struct btc_coexist *btcoexist)
  456. {
  457. struct rtl_priv *rtlpriv = btcoexist->adapter;
  458. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  459. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  460. bool bt_hs_on = false;
  461. u8 algorithm = BT_8192E_2ANT_COEX_ALGO_UNDEFINED;
  462. u8 num_of_diff_profile = 0;
  463. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  464. if (!bt_link_info->bt_link_exist) {
  465. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  466. "No BT link exists!!!\n");
  467. return algorithm;
  468. }
  469. if (bt_link_info->sco_exist)
  470. num_of_diff_profile++;
  471. if (bt_link_info->hid_exist)
  472. num_of_diff_profile++;
  473. if (bt_link_info->pan_exist)
  474. num_of_diff_profile++;
  475. if (bt_link_info->a2dp_exist)
  476. num_of_diff_profile++;
  477. if (num_of_diff_profile == 1) {
  478. if (bt_link_info->sco_exist) {
  479. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  480. "SCO only\n");
  481. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  482. } else {
  483. if (bt_link_info->hid_exist) {
  484. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  485. "HID only\n");
  486. algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
  487. } else if (bt_link_info->a2dp_exist) {
  488. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  489. "A2DP only\n");
  490. algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP;
  491. } else if (bt_link_info->pan_exist) {
  492. if (bt_hs_on) {
  493. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  494. DBG_LOUD,
  495. "PAN(HS) only\n");
  496. algorithm =
  497. BT_8192E_2ANT_COEX_ALGO_PANHS;
  498. } else {
  499. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  500. DBG_LOUD,
  501. "PAN(EDR) only\n");
  502. algorithm =
  503. BT_8192E_2ANT_COEX_ALGO_PANEDR;
  504. }
  505. }
  506. }
  507. } else if (num_of_diff_profile == 2) {
  508. if (bt_link_info->sco_exist) {
  509. if (bt_link_info->hid_exist) {
  510. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  511. "SCO + HID\n");
  512. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  513. } else if (bt_link_info->a2dp_exist) {
  514. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  515. "SCO + A2DP ==> SCO\n");
  516. algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  517. } else if (bt_link_info->pan_exist) {
  518. if (bt_hs_on) {
  519. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  520. DBG_LOUD,
  521. "SCO + PAN(HS)\n");
  522. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  523. } else {
  524. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  525. DBG_LOUD,
  526. "SCO + PAN(EDR)\n");
  527. algorithm =
  528. BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
  529. }
  530. }
  531. } else {
  532. if (bt_link_info->hid_exist &&
  533. bt_link_info->a2dp_exist) {
  534. if (stack_info->num_of_hid >= 2) {
  535. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  536. DBG_LOUD,
  537. "HID*2 + A2DP\n");
  538. algorithm =
  539. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
  540. } else {
  541. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  542. DBG_LOUD,
  543. "HID + A2DP\n");
  544. algorithm =
  545. BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
  546. }
  547. } else if (bt_link_info->hid_exist &&
  548. bt_link_info->pan_exist) {
  549. if (bt_hs_on) {
  550. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  551. DBG_LOUD,
  552. "HID + PAN(HS)\n");
  553. algorithm = BT_8192E_2ANT_COEX_ALGO_HID;
  554. } else {
  555. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  556. DBG_LOUD,
  557. "HID + PAN(EDR)\n");
  558. algorithm =
  559. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  560. }
  561. } else if (bt_link_info->pan_exist &&
  562. bt_link_info->a2dp_exist) {
  563. if (bt_hs_on) {
  564. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  565. DBG_LOUD,
  566. "A2DP + PAN(HS)\n");
  567. algorithm =
  568. BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS;
  569. } else {
  570. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  571. DBG_LOUD,
  572. "A2DP + PAN(EDR)\n");
  573. algorithm =
  574. BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP;
  575. }
  576. }
  577. }
  578. } else if (num_of_diff_profile == 3) {
  579. if (bt_link_info->sco_exist) {
  580. if (bt_link_info->hid_exist &&
  581. bt_link_info->a2dp_exist) {
  582. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  583. "SCO + HID + A2DP ==> HID\n");
  584. algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  585. } else if (bt_link_info->hid_exist &&
  586. bt_link_info->pan_exist) {
  587. if (bt_hs_on) {
  588. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  589. DBG_LOUD,
  590. "SCO + HID + PAN(HS)\n");
  591. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  592. } else {
  593. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  594. DBG_LOUD,
  595. "SCO + HID + PAN(EDR)\n");
  596. algorithm =
  597. BT_8192E_2ANT_COEX_ALGO_SCO_PAN;
  598. }
  599. } else if (bt_link_info->pan_exist &&
  600. bt_link_info->a2dp_exist) {
  601. if (bt_hs_on) {
  602. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  603. DBG_LOUD,
  604. "SCO + A2DP + PAN(HS)\n");
  605. algorithm = BT_8192E_2ANT_COEX_ALGO_SCO;
  606. } else {
  607. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  608. DBG_LOUD,
  609. "SCO + A2DP + PAN(EDR)\n");
  610. algorithm =
  611. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  612. }
  613. }
  614. } else {
  615. if (bt_link_info->hid_exist &&
  616. bt_link_info->pan_exist &&
  617. bt_link_info->a2dp_exist) {
  618. if (bt_hs_on) {
  619. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  620. DBG_LOUD,
  621. "HID + A2DP + PAN(HS)\n");
  622. algorithm =
  623. BT_8192E_2ANT_COEX_ALGO_HID_A2DP;
  624. } else {
  625. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  626. DBG_LOUD,
  627. "HID + A2DP + PAN(EDR)\n");
  628. algorithm =
  629. BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR;
  630. }
  631. }
  632. }
  633. } else if (num_of_diff_profile >= 3) {
  634. if (bt_link_info->sco_exist) {
  635. if (bt_link_info->hid_exist &&
  636. bt_link_info->pan_exist &&
  637. bt_link_info->a2dp_exist) {
  638. if (bt_hs_on) {
  639. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  640. DBG_LOUD,
  641. "ErrorSCO+HID+A2DP+PAN(HS)\n");
  642. } else {
  643. RT_TRACE(rtlpriv, COMP_BT_COEXIST,
  644. DBG_LOUD,
  645. "SCO+HID+A2DP+PAN(EDR)\n");
  646. algorithm =
  647. BT_8192E_2ANT_COEX_ALGO_PANEDR_HID;
  648. }
  649. }
  650. }
  651. }
  652. return algorithm;
  653. }
  654. static void btc8192e2ant_set_fw_dac_swing_level(struct btc_coexist *btcoexist,
  655. u8 dac_swing_lvl)
  656. {
  657. struct rtl_priv *rtlpriv = btcoexist->adapter;
  658. u8 h2c_parameter[1] = {0};
  659. /* There are several type of dacswing
  660. * 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6
  661. */
  662. h2c_parameter[0] = dac_swing_lvl;
  663. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  664. "[BTCoex], Set Dac Swing Level = 0x%x\n", dac_swing_lvl);
  665. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  666. "[BTCoex], FW write 0x64 = 0x%x\n", h2c_parameter[0]);
  667. btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter);
  668. }
  669. static void btc8192e2ant_set_fw_dec_bt_pwr(struct btc_coexist *btcoexist,
  670. u8 dec_bt_pwr_lvl)
  671. {
  672. struct rtl_priv *rtlpriv = btcoexist->adapter;
  673. u8 h2c_parameter[1] = {0};
  674. h2c_parameter[0] = dec_bt_pwr_lvl;
  675. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  676. "[BTCoex] decrease Bt Power level = %d, FW write 0x62 = 0x%x\n",
  677. dec_bt_pwr_lvl, h2c_parameter[0]);
  678. btcoexist->btc_fill_h2c(btcoexist, 0x62, 1, h2c_parameter);
  679. }
  680. static void btc8192e2ant_dec_bt_pwr(struct btc_coexist *btcoexist,
  681. bool force_exec, u8 dec_bt_pwr_lvl)
  682. {
  683. struct rtl_priv *rtlpriv = btcoexist->adapter;
  684. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  685. "[BTCoex], %s Dec BT power level = %d\n",
  686. force_exec ? "force to" : "", dec_bt_pwr_lvl);
  687. coex_dm->cur_dec_bt_pwr = dec_bt_pwr_lvl;
  688. if (!force_exec) {
  689. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  690. "[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n",
  691. coex_dm->pre_dec_bt_pwr, coex_dm->cur_dec_bt_pwr);
  692. }
  693. btc8192e2ant_set_fw_dec_bt_pwr(btcoexist, coex_dm->cur_dec_bt_pwr);
  694. coex_dm->pre_dec_bt_pwr = coex_dm->cur_dec_bt_pwr;
  695. }
  696. static void btc8192e2ant_set_bt_auto_report(struct btc_coexist *btcoexist,
  697. bool enable_auto_report)
  698. {
  699. struct rtl_priv *rtlpriv = btcoexist->adapter;
  700. u8 h2c_parameter[1] = {0};
  701. h2c_parameter[0] = 0;
  702. if (enable_auto_report)
  703. h2c_parameter[0] |= BIT0;
  704. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  705. "[BTCoex], BT FW auto report : %s, FW write 0x68 = 0x%x\n",
  706. (enable_auto_report ? "Enabled!!" : "Disabled!!"),
  707. h2c_parameter[0]);
  708. btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter);
  709. }
  710. static void btc8192e2ant_bt_auto_report(struct btc_coexist *btcoexist,
  711. bool force_exec,
  712. bool enable_auto_report)
  713. {
  714. struct rtl_priv *rtlpriv = btcoexist->adapter;
  715. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  716. "[BTCoex], %s BT Auto report = %s\n",
  717. (force_exec ? "force to" : ""),
  718. ((enable_auto_report) ? "Enabled" : "Disabled"));
  719. coex_dm->cur_bt_auto_report = enable_auto_report;
  720. if (!force_exec) {
  721. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  722. "[BTCoex] bPreBtAutoReport=%d, bCurBtAutoReport=%d\n",
  723. coex_dm->pre_bt_auto_report,
  724. coex_dm->cur_bt_auto_report);
  725. if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report)
  726. return;
  727. }
  728. btc8192e2ant_set_bt_auto_report(btcoexist,
  729. coex_dm->cur_bt_auto_report);
  730. coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report;
  731. }
  732. static void btc8192e2ant_fw_dac_swing_lvl(struct btc_coexist *btcoexist,
  733. bool force_exec, u8 fw_dac_swing_lvl)
  734. {
  735. struct rtl_priv *rtlpriv = btcoexist->adapter;
  736. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  737. "[BTCoex], %s set FW Dac Swing level = %d\n",
  738. (force_exec ? "force to" : ""), fw_dac_swing_lvl);
  739. coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl;
  740. if (!force_exec) {
  741. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  742. "[BTCoex] preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n",
  743. coex_dm->pre_fw_dac_swing_lvl,
  744. coex_dm->cur_fw_dac_swing_lvl);
  745. if (coex_dm->pre_fw_dac_swing_lvl ==
  746. coex_dm->cur_fw_dac_swing_lvl)
  747. return;
  748. }
  749. btc8192e2ant_set_fw_dac_swing_level(btcoexist,
  750. coex_dm->cur_fw_dac_swing_lvl);
  751. coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl;
  752. }
  753. static void btc8192e2ant_set_sw_rf_rx_lpf_corner(struct btc_coexist *btcoexist,
  754. bool rx_rf_shrink_on)
  755. {
  756. struct rtl_priv *rtlpriv = btcoexist->adapter;
  757. if (rx_rf_shrink_on) {
  758. /* Shrink RF Rx LPF corner */
  759. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  760. "[BTCoex], Shrink RF Rx LPF corner!!\n");
  761. btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
  762. 0xfffff, 0xffffc);
  763. } else {
  764. /* Resume RF Rx LPF corner
  765. * After initialized, we can use coex_dm->btRf0x1eBackup
  766. */
  767. if (btcoexist->initilized) {
  768. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  769. "[BTCoex], Resume RF Rx LPF corner!!\n");
  770. btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1e,
  771. 0xfffff,
  772. coex_dm->bt_rf0x1e_backup);
  773. }
  774. }
  775. }
  776. static void btc8192e2ant_rf_shrink(struct btc_coexist *btcoexist,
  777. bool force_exec, bool rx_rf_shrink_on)
  778. {
  779. struct rtl_priv *rtlpriv = btcoexist->adapter;
  780. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  781. "[BTCoex], %s turn Rx RF Shrink = %s\n",
  782. (force_exec ? "force to" : ""),
  783. ((rx_rf_shrink_on) ? "ON" : "OFF"));
  784. coex_dm->cur_rf_rx_lpf_shrink = rx_rf_shrink_on;
  785. if (!force_exec) {
  786. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  787. "[BTCoex]bPreRfRxLpfShrink=%d,bCurRfRxLpfShrink=%d\n",
  788. coex_dm->pre_rf_rx_lpf_shrink,
  789. coex_dm->cur_rf_rx_lpf_shrink);
  790. if (coex_dm->pre_rf_rx_lpf_shrink ==
  791. coex_dm->cur_rf_rx_lpf_shrink)
  792. return;
  793. }
  794. btc8192e2ant_set_sw_rf_rx_lpf_corner(btcoexist,
  795. coex_dm->cur_rf_rx_lpf_shrink);
  796. coex_dm->pre_rf_rx_lpf_shrink = coex_dm->cur_rf_rx_lpf_shrink;
  797. }
  798. static void btc8192e2ant_set_dac_swing_reg(struct btc_coexist *btcoexist,
  799. u32 level)
  800. {
  801. struct rtl_priv *rtlpriv = btcoexist->adapter;
  802. u8 val = (u8)level;
  803. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  804. "[BTCoex], Write SwDacSwing = 0x%x\n", level);
  805. btcoexist->btc_write_1byte_bitmask(btcoexist, 0x883, 0x3e, val);
  806. }
  807. static void btc8192e2ant_set_sw_full_swing(struct btc_coexist *btcoexist,
  808. bool sw_dac_swing_on,
  809. u32 sw_dac_swing_lvl)
  810. {
  811. if (sw_dac_swing_on)
  812. btc8192e2ant_set_dac_swing_reg(btcoexist, sw_dac_swing_lvl);
  813. else
  814. btc8192e2ant_set_dac_swing_reg(btcoexist, 0x18);
  815. }
  816. static void btc8192e2ant_dac_swing(struct btc_coexist *btcoexist,
  817. bool force_exec, bool dac_swing_on,
  818. u32 dac_swing_lvl)
  819. {
  820. struct rtl_priv *rtlpriv = btcoexist->adapter;
  821. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  822. "[BTCoex], %s turn DacSwing=%s, dac_swing_lvl = 0x%x\n",
  823. (force_exec ? "force to" : ""),
  824. ((dac_swing_on) ? "ON" : "OFF"), dac_swing_lvl);
  825. coex_dm->cur_dac_swing_on = dac_swing_on;
  826. coex_dm->cur_dac_swing_lvl = dac_swing_lvl;
  827. if (!force_exec) {
  828. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  829. "[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl = 0x%x, ",
  830. coex_dm->pre_dac_swing_on,
  831. coex_dm->pre_dac_swing_lvl);
  832. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  833. "bCurDacSwingOn=%d, curDacSwingLvl = 0x%x\n",
  834. coex_dm->cur_dac_swing_on,
  835. coex_dm->cur_dac_swing_lvl);
  836. if ((coex_dm->pre_dac_swing_on == coex_dm->cur_dac_swing_on) &&
  837. (coex_dm->pre_dac_swing_lvl == coex_dm->cur_dac_swing_lvl))
  838. return;
  839. }
  840. mdelay(30);
  841. btc8192e2ant_set_sw_full_swing(btcoexist, dac_swing_on, dac_swing_lvl);
  842. coex_dm->pre_dac_swing_on = coex_dm->cur_dac_swing_on;
  843. coex_dm->pre_dac_swing_lvl = coex_dm->cur_dac_swing_lvl;
  844. }
  845. static void btc8192e2ant_set_agc_table(struct btc_coexist *btcoexist,
  846. bool agc_table_en)
  847. {
  848. struct rtl_priv *rtlpriv = btcoexist->adapter;
  849. /* BB AGC Gain Table */
  850. if (agc_table_en) {
  851. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  852. "[BTCoex], BB Agc Table On!\n");
  853. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x0a1A0001);
  854. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x091B0001);
  855. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x081C0001);
  856. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x071D0001);
  857. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x061E0001);
  858. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0x051F0001);
  859. } else {
  860. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  861. "[BTCoex], BB Agc Table Off!\n");
  862. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xaa1A0001);
  863. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa91B0001);
  864. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa81C0001);
  865. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa71D0001);
  866. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa61E0001);
  867. btcoexist->btc_write_4byte(btcoexist, 0xc78, 0xa51F0001);
  868. }
  869. }
  870. static void btc8192e2ant_agc_table(struct btc_coexist *btcoexist,
  871. bool force_exec, bool agc_table_en)
  872. {
  873. struct rtl_priv *rtlpriv = btcoexist->adapter;
  874. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  875. "[BTCoex], %s %s Agc Table\n",
  876. (force_exec ? "force to" : ""),
  877. ((agc_table_en) ? "Enable" : "Disable"));
  878. coex_dm->cur_agc_table_en = agc_table_en;
  879. if (!force_exec) {
  880. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  881. "[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n",
  882. coex_dm->pre_agc_table_en,
  883. coex_dm->cur_agc_table_en);
  884. if (coex_dm->pre_agc_table_en == coex_dm->cur_agc_table_en)
  885. return;
  886. }
  887. btc8192e2ant_set_agc_table(btcoexist, agc_table_en);
  888. coex_dm->pre_agc_table_en = coex_dm->cur_agc_table_en;
  889. }
  890. static void btc8192e2ant_set_coex_table(struct btc_coexist *btcoexist,
  891. u32 val0x6c0, u32 val0x6c4,
  892. u32 val0x6c8, u8 val0x6cc)
  893. {
  894. struct rtl_priv *rtlpriv = btcoexist->adapter;
  895. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  896. "[BTCoex], set coex table, set 0x6c0 = 0x%x\n", val0x6c0);
  897. btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0);
  898. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  899. "[BTCoex], set coex table, set 0x6c4 = 0x%x\n", val0x6c4);
  900. btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4);
  901. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  902. "[BTCoex], set coex table, set 0x6c8 = 0x%x\n", val0x6c8);
  903. btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8);
  904. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  905. "[BTCoex], set coex table, set 0x6cc = 0x%x\n", val0x6cc);
  906. btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc);
  907. }
  908. static void btc8192e2ant_coex_table(struct btc_coexist *btcoexist,
  909. bool force_exec, u32 val0x6c0, u32 val0x6c4,
  910. u32 val0x6c8, u8 val0x6cc)
  911. {
  912. struct rtl_priv *rtlpriv = btcoexist->adapter;
  913. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  914. "[BTCoex], %s write Coex Table 0x6c0 = 0x%x, ",
  915. (force_exec ? "force to" : ""), val0x6c0);
  916. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  917. "0x6c4 = 0x%x, 0x6c8 = 0x%x, 0x6cc = 0x%x\n",
  918. val0x6c4, val0x6c8, val0x6cc);
  919. coex_dm->cur_val0x6c0 = val0x6c0;
  920. coex_dm->cur_val0x6c4 = val0x6c4;
  921. coex_dm->cur_val0x6c8 = val0x6c8;
  922. coex_dm->cur_val0x6cc = val0x6cc;
  923. if (!force_exec) {
  924. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  925. "[BTCoex], preVal0x6c0 = 0x%x, preVal0x6c4 = 0x%x, ",
  926. coex_dm->pre_val0x6c0, coex_dm->pre_val0x6c4);
  927. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  928. "preVal0x6c8 = 0x%x, preVal0x6cc = 0x%x !!\n",
  929. coex_dm->pre_val0x6c8, coex_dm->pre_val0x6cc);
  930. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  931. "[BTCoex], curVal0x6c0 = 0x%x, curVal0x6c4 = 0x%x\n",
  932. coex_dm->cur_val0x6c0, coex_dm->cur_val0x6c4);
  933. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  934. "curVal0x6c8 = 0x%x, curVal0x6cc = 0x%x !!\n",
  935. coex_dm->cur_val0x6c8, coex_dm->cur_val0x6cc);
  936. if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) &&
  937. (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) &&
  938. (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) &&
  939. (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc))
  940. return;
  941. }
  942. btc8192e2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8,
  943. val0x6cc);
  944. coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0;
  945. coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4;
  946. coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8;
  947. coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc;
  948. }
  949. static void btc8192e2ant_coex_table_with_type(struct btc_coexist *btcoexist,
  950. bool force_exec, u8 type)
  951. {
  952. switch (type) {
  953. case 0:
  954. btc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
  955. 0x5a5a5a5a, 0xffffff, 0x3);
  956. break;
  957. case 1:
  958. btc8192e2ant_coex_table(btcoexist, force_exec, 0x5a5a5a5a,
  959. 0x5a5a5a5a, 0xffffff, 0x3);
  960. break;
  961. case 2:
  962. btc8192e2ant_coex_table(btcoexist, force_exec, 0x55555555,
  963. 0x5ffb5ffb, 0xffffff, 0x3);
  964. break;
  965. case 3:
  966. btc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
  967. 0x5fdb5fdb, 0xffffff, 0x3);
  968. break;
  969. case 4:
  970. btc8192e2ant_coex_table(btcoexist, force_exec, 0xdfffdfff,
  971. 0x5ffb5ffb, 0xffffff, 0x3);
  972. break;
  973. default:
  974. break;
  975. }
  976. }
  977. static void btc8192e2ant_set_fw_ignore_wlan_act(struct btc_coexist *btcoexist,
  978. bool enable)
  979. {
  980. struct rtl_priv *rtlpriv = btcoexist->adapter;
  981. u8 h2c_parameter[1] = {0};
  982. if (enable)
  983. h2c_parameter[0] |= BIT0; /* function enable */
  984. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  985. "[BTCoex]set FW for BT Ignore Wlan_Act, FW write 0x63 = 0x%x\n",
  986. h2c_parameter[0]);
  987. btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter);
  988. }
  989. static void btc8192e2ant_ignore_wlan_act(struct btc_coexist *btcoexist,
  990. bool force_exec, bool enable)
  991. {
  992. struct rtl_priv *rtlpriv = btcoexist->adapter;
  993. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  994. "[BTCoex], %s turn Ignore WlanAct %s\n",
  995. (force_exec ? "force to" : ""), (enable ? "ON" : "OFF"));
  996. coex_dm->cur_ignore_wlan_act = enable;
  997. if (!force_exec) {
  998. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  999. "[BTCoex], bPreIgnoreWlanAct = %d ",
  1000. coex_dm->pre_ignore_wlan_act);
  1001. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1002. "bCurIgnoreWlanAct = %d!!\n",
  1003. coex_dm->cur_ignore_wlan_act);
  1004. if (coex_dm->pre_ignore_wlan_act ==
  1005. coex_dm->cur_ignore_wlan_act)
  1006. return;
  1007. }
  1008. btc8192e2ant_set_fw_ignore_wlan_act(btcoexist, enable);
  1009. coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act;
  1010. }
  1011. static void btc8192e2ant_set_fw_ps_tdma(struct btc_coexist *btcoexist, u8 byte1,
  1012. u8 byte2, u8 byte3, u8 byte4, u8 byte5)
  1013. {
  1014. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1015. u8 h2c_parameter[5] = {0};
  1016. h2c_parameter[0] = byte1;
  1017. h2c_parameter[1] = byte2;
  1018. h2c_parameter[2] = byte3;
  1019. h2c_parameter[3] = byte4;
  1020. h2c_parameter[4] = byte5;
  1021. coex_dm->ps_tdma_para[0] = byte1;
  1022. coex_dm->ps_tdma_para[1] = byte2;
  1023. coex_dm->ps_tdma_para[2] = byte3;
  1024. coex_dm->ps_tdma_para[3] = byte4;
  1025. coex_dm->ps_tdma_para[4] = byte5;
  1026. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1027. "[BTCoex], FW write 0x60(5bytes) = 0x%x%08x\n",
  1028. h2c_parameter[0],
  1029. h2c_parameter[1] << 24 | h2c_parameter[2] << 16 |
  1030. h2c_parameter[3] << 8 | h2c_parameter[4]);
  1031. btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter);
  1032. }
  1033. static void btc8192e2ant_sw_mechanism1(struct btc_coexist *btcoexist,
  1034. bool shrink_rx_lpf, bool low_penalty_ra,
  1035. bool limited_dig, bool btlan_constrain)
  1036. {
  1037. btc8192e2ant_rf_shrink(btcoexist, NORMAL_EXEC, shrink_rx_lpf);
  1038. }
  1039. static void btc8192e2ant_sw_mechanism2(struct btc_coexist *btcoexist,
  1040. bool agc_table_shift, bool adc_backoff,
  1041. bool sw_dac_swing, u32 dac_swing_lvl)
  1042. {
  1043. btc8192e2ant_agc_table(btcoexist, NORMAL_EXEC, agc_table_shift);
  1044. btc8192e2ant_dac_swing(btcoexist, NORMAL_EXEC, sw_dac_swing,
  1045. dac_swing_lvl);
  1046. }
  1047. static void btc8192e2ant_ps_tdma(struct btc_coexist *btcoexist,
  1048. bool force_exec, bool turn_on, u8 type)
  1049. {
  1050. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1051. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1052. "[BTCoex], %s turn %s PS TDMA, type=%d\n",
  1053. (force_exec ? "force to" : ""),
  1054. (turn_on ? "ON" : "OFF"), type);
  1055. coex_dm->cur_ps_tdma_on = turn_on;
  1056. coex_dm->cur_ps_tdma = type;
  1057. if (!force_exec) {
  1058. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1059. "[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n",
  1060. coex_dm->pre_ps_tdma_on, coex_dm->cur_ps_tdma_on);
  1061. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1062. "[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n",
  1063. coex_dm->pre_ps_tdma, coex_dm->cur_ps_tdma);
  1064. if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) &&
  1065. (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma))
  1066. return;
  1067. }
  1068. if (turn_on) {
  1069. switch (type) {
  1070. case 1:
  1071. default:
  1072. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1073. 0x1a, 0xe1, 0x90);
  1074. break;
  1075. case 2:
  1076. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1077. 0x12, 0xe1, 0x90);
  1078. break;
  1079. case 3:
  1080. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1081. 0x3, 0xf1, 0x90);
  1082. break;
  1083. case 4:
  1084. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x10,
  1085. 0x3, 0xf1, 0x90);
  1086. break;
  1087. case 5:
  1088. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1089. 0x1a, 0x60, 0x90);
  1090. break;
  1091. case 6:
  1092. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1093. 0x12, 0x60, 0x90);
  1094. break;
  1095. case 7:
  1096. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1097. 0x3, 0x70, 0x90);
  1098. break;
  1099. case 8:
  1100. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xa3, 0x10,
  1101. 0x3, 0x70, 0x90);
  1102. break;
  1103. case 9:
  1104. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1105. 0x1a, 0xe1, 0x10);
  1106. break;
  1107. case 10:
  1108. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1109. 0x12, 0xe1, 0x10);
  1110. break;
  1111. case 11:
  1112. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1113. 0x3, 0xf1, 0x10);
  1114. break;
  1115. case 12:
  1116. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x10,
  1117. 0x3, 0xf1, 0x10);
  1118. break;
  1119. case 13:
  1120. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1121. 0x1a, 0xe0, 0x10);
  1122. break;
  1123. case 14:
  1124. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1125. 0x12, 0xe0, 0x10);
  1126. break;
  1127. case 15:
  1128. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1c,
  1129. 0x3, 0xf0, 0x10);
  1130. break;
  1131. case 16:
  1132. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x12,
  1133. 0x3, 0xf0, 0x10);
  1134. break;
  1135. case 17:
  1136. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0x61, 0x20,
  1137. 0x03, 0x10, 0x10);
  1138. break;
  1139. case 18:
  1140. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x5,
  1141. 0x5, 0xe1, 0x90);
  1142. break;
  1143. case 19:
  1144. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
  1145. 0x25, 0xe1, 0x90);
  1146. break;
  1147. case 20:
  1148. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x25,
  1149. 0x25, 0x60, 0x90);
  1150. break;
  1151. case 21:
  1152. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x15,
  1153. 0x03, 0x70, 0x90);
  1154. break;
  1155. case 71:
  1156. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0xe3, 0x1a,
  1157. 0x1a, 0xe1, 0x90);
  1158. break;
  1159. }
  1160. } else {
  1161. /* disable PS tdma */
  1162. switch (type) {
  1163. default:
  1164. case 0:
  1165. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0x8, 0x0, 0x0,
  1166. 0x0, 0x0);
  1167. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x4);
  1168. break;
  1169. case 1:
  1170. btc8192e2ant_set_fw_ps_tdma(btcoexist, 0x0, 0x0, 0x0,
  1171. 0x8, 0x0);
  1172. mdelay(5);
  1173. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
  1174. break;
  1175. }
  1176. }
  1177. /* update pre state */
  1178. coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on;
  1179. coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma;
  1180. }
  1181. static void btc8192e2ant_set_switch_ss_type(struct btc_coexist *btcoexist,
  1182. u8 ss_type)
  1183. {
  1184. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1185. u8 mimops = BTC_MIMO_PS_DYNAMIC;
  1186. u32 dis_ra_mask = 0x0;
  1187. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1188. "[BTCoex], REAL set SS Type = %d\n", ss_type);
  1189. dis_ra_mask = btc8192e2ant_decide_ra_mask(btcoexist, ss_type,
  1190. coex_dm->cur_ra_mask_type);
  1191. btc8192e2ant_update_ra_mask(btcoexist, FORCE_EXEC, dis_ra_mask);
  1192. if (ss_type == 1) {
  1193. btc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
  1194. /* switch ofdm path */
  1195. btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x11);
  1196. btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x1);
  1197. btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81111111);
  1198. /* switch cck patch */
  1199. btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x1);
  1200. btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x81);
  1201. mimops = BTC_MIMO_PS_STATIC;
  1202. } else if (ss_type == 2) {
  1203. btc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 0);
  1204. btcoexist->btc_write_1byte(btcoexist, 0xc04, 0x33);
  1205. btcoexist->btc_write_1byte(btcoexist, 0xd04, 0x3);
  1206. btcoexist->btc_write_4byte(btcoexist, 0x90c, 0x81121313);
  1207. btcoexist->btc_write_1byte_bitmask(btcoexist, 0xe77, 0x4, 0x0);
  1208. btcoexist->btc_write_1byte(btcoexist, 0xa07, 0x41);
  1209. mimops = BTC_MIMO_PS_DYNAMIC;
  1210. }
  1211. /* set rx 1ss or 2ss */
  1212. btcoexist->btc_set(btcoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimops);
  1213. }
  1214. static void btc8192e2ant_switch_ss_type(struct btc_coexist *btcoexist,
  1215. bool force_exec, u8 new_ss_type)
  1216. {
  1217. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1218. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1219. "[BTCoex], %s Switch SS Type = %d\n",
  1220. (force_exec ? "force to" : ""), new_ss_type);
  1221. coex_dm->cur_ss_type = new_ss_type;
  1222. if (!force_exec) {
  1223. if (coex_dm->pre_ss_type == coex_dm->cur_ss_type)
  1224. return;
  1225. }
  1226. btc8192e2ant_set_switch_ss_type(btcoexist, coex_dm->cur_ss_type);
  1227. coex_dm->pre_ss_type = coex_dm->cur_ss_type;
  1228. }
  1229. static void btc8192e2ant_coex_all_off(struct btc_coexist *btcoexist)
  1230. {
  1231. /* fw all off */
  1232. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1233. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1234. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1235. /* sw all off */
  1236. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
  1237. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
  1238. /* hw all off */
  1239. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
  1240. }
  1241. static void btc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
  1242. {
  1243. /* force to reset coex mechanism */
  1244. btc8192e2ant_ps_tdma(btcoexist, FORCE_EXEC, false, 1);
  1245. btc8192e2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 6);
  1246. btc8192e2ant_dec_bt_pwr(btcoexist, FORCE_EXEC, 0);
  1247. btc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
  1248. btc8192e2ant_switch_ss_type(btcoexist, FORCE_EXEC, 2);
  1249. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
  1250. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
  1251. }
  1252. static void btc8192e2ant_action_bt_inquiry(struct btc_coexist *btcoexist)
  1253. {
  1254. bool low_pwr_disable = true;
  1255. btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
  1256. &low_pwr_disable);
  1257. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1258. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1259. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 3);
  1260. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1261. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1262. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false, false);
  1263. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false, 0x18);
  1264. }
  1265. static bool btc8192e2ant_is_common_action(struct btc_coexist *btcoexist)
  1266. {
  1267. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1268. struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info;
  1269. bool common = false, wifi_connected = false, wifi_busy = false;
  1270. bool bt_hs_on = false, low_pwr_disable = false;
  1271. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  1272. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  1273. &wifi_connected);
  1274. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  1275. if (bt_link_info->sco_exist || bt_link_info->hid_exist)
  1276. btc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 1, 0, 0, 0);
  1277. else
  1278. btc8192e2ant_limited_tx(btcoexist, NORMAL_EXEC, 0, 0, 0, 0);
  1279. if (!wifi_connected) {
  1280. low_pwr_disable = false;
  1281. btcoexist->btc_set(btcoexist, BTC_SET_ACT_DISABLE_LOW_POWER,
  1282. &low_pwr_disable);
  1283. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1284. "[BTCoex], Wifi non-connected idle!!\n");
  1285. if ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  1286. coex_dm->bt_status) ||
  1287. (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  1288. coex_dm->bt_status)) {
  1289. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
  1290. btc8192e2ant_coex_table_with_type(btcoexist,
  1291. NORMAL_EXEC, 1);
  1292. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
  1293. } else {
  1294. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1295. btc8192e2ant_coex_table_with_type(btcoexist,
  1296. NORMAL_EXEC, 0);
  1297. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1298. }
  1299. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1300. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1301. btc8192e2ant_sw_mechanism1(btcoexist, false, false, false,
  1302. false);
  1303. btc8192e2ant_sw_mechanism2(btcoexist, false, false, false,
  1304. 0x18);
  1305. common = true;
  1306. } else {
  1307. if (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  1308. coex_dm->bt_status) {
  1309. low_pwr_disable = false;
  1310. btcoexist->btc_set(btcoexist,
  1311. BTC_SET_ACT_DISABLE_LOW_POWER,
  1312. &low_pwr_disable);
  1313. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1314. "Wifi connected + BT non connected-idle!!\n");
  1315. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
  1316. btc8192e2ant_coex_table_with_type(btcoexist,
  1317. NORMAL_EXEC, 1);
  1318. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 0);
  1319. btc8192e2ant_fw_dac_swing_lvl(btcoexist,
  1320. NORMAL_EXEC, 6);
  1321. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1322. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1323. false, false);
  1324. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1325. false, 0x18);
  1326. common = true;
  1327. } else if (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  1328. coex_dm->bt_status) {
  1329. low_pwr_disable = true;
  1330. btcoexist->btc_set(btcoexist,
  1331. BTC_SET_ACT_DISABLE_LOW_POWER,
  1332. &low_pwr_disable);
  1333. if (bt_hs_on)
  1334. return false;
  1335. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1336. "Wifi connected + BT connected-idle!!\n");
  1337. btc8192e2ant_switch_ss_type(btcoexist,
  1338. NORMAL_EXEC, 2);
  1339. btc8192e2ant_coex_table_with_type(btcoexist,
  1340. NORMAL_EXEC, 1);
  1341. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1342. false, 0);
  1343. btc8192e2ant_fw_dac_swing_lvl(btcoexist,
  1344. NORMAL_EXEC, 6);
  1345. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1346. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1347. false, false);
  1348. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1349. false, 0x18);
  1350. common = true;
  1351. } else {
  1352. low_pwr_disable = true;
  1353. btcoexist->btc_set(btcoexist,
  1354. BTC_SET_ACT_DISABLE_LOW_POWER,
  1355. &low_pwr_disable);
  1356. if (wifi_busy) {
  1357. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1358. "Wifi Connected-Busy + BT Busy!!\n");
  1359. common = false;
  1360. } else {
  1361. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1362. "Wifi Connected-Idle + BT Busy!!\n");
  1363. btc8192e2ant_switch_ss_type(btcoexist,
  1364. NORMAL_EXEC, 1);
  1365. btc8192e2ant_coex_table_with_type(btcoexist,
  1366. NORMAL_EXEC,
  1367. 2);
  1368. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1369. true, 21);
  1370. btc8192e2ant_fw_dac_swing_lvl(btcoexist,
  1371. NORMAL_EXEC, 6);
  1372. btc8192e2ant_dec_bt_pwr(btcoexist,
  1373. NORMAL_EXEC, 0);
  1374. btc8192e2ant_sw_mechanism1(btcoexist, false,
  1375. false, false, false);
  1376. btc8192e2ant_sw_mechanism2(btcoexist, false,
  1377. false, false, 0x18);
  1378. common = true;
  1379. }
  1380. }
  1381. }
  1382. return common;
  1383. }
  1384. static void btc8192e2ant_tdma_duration_adjust(struct btc_coexist *btcoexist,
  1385. bool sco_hid, bool tx_pause,
  1386. u8 max_interval)
  1387. {
  1388. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1389. static int up, dn, m, n, wait_cnt;
  1390. /* 0: no change, +1: increase WiFi duration,
  1391. * -1: decrease WiFi duration
  1392. */
  1393. int result;
  1394. u8 retry_cnt = 0;
  1395. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1396. "[BTCoex], TdmaDurationAdjust()\n");
  1397. if (!coex_dm->auto_tdma_adjust) {
  1398. coex_dm->auto_tdma_adjust = true;
  1399. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1400. "[BTCoex], first run TdmaDurationAdjust()!!\n");
  1401. if (sco_hid) {
  1402. if (tx_pause) {
  1403. if (max_interval == 1) {
  1404. btc8192e2ant_ps_tdma(btcoexist,
  1405. NORMAL_EXEC,
  1406. true, 13);
  1407. coex_dm->tdma_adj_type = 13;
  1408. } else if (max_interval == 2) {
  1409. btc8192e2ant_ps_tdma(btcoexist,
  1410. NORMAL_EXEC,
  1411. true, 14);
  1412. coex_dm->tdma_adj_type = 14;
  1413. } else {
  1414. btc8192e2ant_ps_tdma(btcoexist,
  1415. NORMAL_EXEC,
  1416. true, 15);
  1417. coex_dm->tdma_adj_type = 15;
  1418. }
  1419. } else {
  1420. if (max_interval == 1) {
  1421. btc8192e2ant_ps_tdma(btcoexist,
  1422. NORMAL_EXEC,
  1423. true, 9);
  1424. coex_dm->tdma_adj_type = 9;
  1425. } else if (max_interval == 2) {
  1426. btc8192e2ant_ps_tdma(btcoexist,
  1427. NORMAL_EXEC,
  1428. true, 10);
  1429. coex_dm->tdma_adj_type = 10;
  1430. } else {
  1431. btc8192e2ant_ps_tdma(btcoexist,
  1432. NORMAL_EXEC,
  1433. true, 11);
  1434. coex_dm->tdma_adj_type = 11;
  1435. }
  1436. }
  1437. } else {
  1438. if (tx_pause) {
  1439. if (max_interval == 1) {
  1440. btc8192e2ant_ps_tdma(btcoexist,
  1441. NORMAL_EXEC,
  1442. true, 5);
  1443. coex_dm->tdma_adj_type = 5;
  1444. } else if (max_interval == 2) {
  1445. btc8192e2ant_ps_tdma(btcoexist,
  1446. NORMAL_EXEC,
  1447. true, 6);
  1448. coex_dm->tdma_adj_type = 6;
  1449. } else {
  1450. btc8192e2ant_ps_tdma(btcoexist,
  1451. NORMAL_EXEC,
  1452. true, 7);
  1453. coex_dm->tdma_adj_type = 7;
  1454. }
  1455. } else {
  1456. if (max_interval == 1) {
  1457. btc8192e2ant_ps_tdma(btcoexist,
  1458. NORMAL_EXEC,
  1459. true, 1);
  1460. coex_dm->tdma_adj_type = 1;
  1461. } else if (max_interval == 2) {
  1462. btc8192e2ant_ps_tdma(btcoexist,
  1463. NORMAL_EXEC,
  1464. true, 2);
  1465. coex_dm->tdma_adj_type = 2;
  1466. } else {
  1467. btc8192e2ant_ps_tdma(btcoexist,
  1468. NORMAL_EXEC,
  1469. true, 3);
  1470. coex_dm->tdma_adj_type = 3;
  1471. }
  1472. }
  1473. }
  1474. up = 0;
  1475. dn = 0;
  1476. m = 1;
  1477. n = 3;
  1478. result = 0;
  1479. wait_cnt = 0;
  1480. } else {
  1481. /* accquire the BT TRx retry count from BT_Info byte2 */
  1482. retry_cnt = coex_sta->bt_retry_cnt;
  1483. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1484. "[BTCoex], retry_cnt = %d\n", retry_cnt);
  1485. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1486. "[BTCoex], up=%d, dn=%d, m=%d, n=%d, wait_cnt=%d\n",
  1487. up, dn, m, n, wait_cnt);
  1488. result = 0;
  1489. wait_cnt++;
  1490. /* no retry in the last 2-second duration */
  1491. if (retry_cnt == 0) {
  1492. up++;
  1493. dn--;
  1494. if (dn <= 0)
  1495. dn = 0;
  1496. if (up >= n) {
  1497. wait_cnt = 0;
  1498. n = 3;
  1499. up = 0;
  1500. dn = 0;
  1501. result = 1;
  1502. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1503. "[BTCoex]Increase wifi duration!!\n");
  1504. }
  1505. } else if (retry_cnt <= 3) {
  1506. up--;
  1507. dn++;
  1508. if (up <= 0)
  1509. up = 0;
  1510. if (dn == 2) {
  1511. if (wait_cnt <= 2)
  1512. m++;
  1513. else
  1514. m = 1;
  1515. if (m >= 20)
  1516. m = 20;
  1517. n = 3 * m;
  1518. up = 0;
  1519. dn = 0;
  1520. wait_cnt = 0;
  1521. result = -1;
  1522. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1523. "Reduce wifi duration for retry<3\n");
  1524. }
  1525. } else {
  1526. if (wait_cnt == 1)
  1527. m++;
  1528. else
  1529. m = 1;
  1530. if (m >= 20)
  1531. m = 20;
  1532. n = 3*m;
  1533. up = 0;
  1534. dn = 0;
  1535. wait_cnt = 0;
  1536. result = -1;
  1537. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1538. "Decrease wifi duration for retryCounter>3!!\n");
  1539. }
  1540. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1541. "[BTCoex], max Interval = %d\n", max_interval);
  1542. }
  1543. /* if current PsTdma not match with
  1544. * the recorded one (when scan, dhcp...),
  1545. * then we have to adjust it back to the previous record one.
  1546. */
  1547. if (coex_dm->cur_ps_tdma != coex_dm->tdma_adj_type) {
  1548. bool scan = false, link = false, roam = false;
  1549. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1550. "[BTCoex], PsTdma type dismatch!!!, ");
  1551. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1552. "curPsTdma=%d, recordPsTdma=%d\n",
  1553. coex_dm->cur_ps_tdma, coex_dm->tdma_adj_type);
  1554. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
  1555. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
  1556. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
  1557. if (!scan && !link && !roam)
  1558. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  1559. true, coex_dm->tdma_adj_type);
  1560. else
  1561. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1562. "[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n");
  1563. }
  1564. }
  1565. /* SCO only or SCO+PAN(HS) */
  1566. static void btc8192e2ant_action_sco(struct btc_coexist *btcoexist)
  1567. {
  1568. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  1569. u32 wifi_bw;
  1570. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1571. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1572. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1573. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1574. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
  1575. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1576. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1577. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1578. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1579. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
  1580. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1581. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1582. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1583. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1584. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1585. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1586. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1587. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1588. }
  1589. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1590. /* sw mechanism */
  1591. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1592. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1593. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1594. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1595. false, false);
  1596. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1597. false, 0x6);
  1598. } else {
  1599. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1600. false, false);
  1601. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1602. false, 0x6);
  1603. }
  1604. } else {
  1605. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1606. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1607. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1608. false, false);
  1609. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1610. false, 0x6);
  1611. } else {
  1612. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1613. false, false);
  1614. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1615. false, 0x6);
  1616. }
  1617. }
  1618. }
  1619. static void btc8192e2ant_action_sco_pan(struct btc_coexist *btcoexist)
  1620. {
  1621. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_STAY_LOW;
  1622. u32 wifi_bw;
  1623. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1624. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1625. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1626. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1627. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4);
  1628. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1629. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1630. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1631. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1632. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
  1633. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1634. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1635. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1636. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  1637. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1638. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1639. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1640. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  1641. }
  1642. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1643. /* sw mechanism */
  1644. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1645. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1646. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1647. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1648. false, false);
  1649. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1650. false, 0x6);
  1651. } else {
  1652. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1653. false, false);
  1654. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1655. false, 0x6);
  1656. }
  1657. } else {
  1658. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1659. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1660. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1661. false, false);
  1662. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1663. false, 0x6);
  1664. } else {
  1665. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1666. false, false);
  1667. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1668. false, 0x6);
  1669. }
  1670. }
  1671. }
  1672. static void btc8192e2ant_action_hid(struct btc_coexist *btcoexist)
  1673. {
  1674. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1675. u32 wifi_bw;
  1676. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1677. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1678. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1679. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1680. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1681. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1682. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  1683. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1684. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1685. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1686. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 13);
  1687. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1688. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1689. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1690. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1691. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1692. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1693. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1694. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 9);
  1695. }
  1696. /* sw mechanism */
  1697. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1698. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1699. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1700. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1701. false, false);
  1702. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1703. false, 0x18);
  1704. } else {
  1705. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  1706. false, false);
  1707. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1708. false, 0x18);
  1709. }
  1710. } else {
  1711. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1712. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1713. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1714. false, false);
  1715. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1716. false, 0x18);
  1717. } else {
  1718. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  1719. false, false);
  1720. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1721. false, 0x18);
  1722. }
  1723. }
  1724. }
  1725. /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */
  1726. static void btc8192e2ant_action_a2dp(struct btc_coexist *btcoexist)
  1727. {
  1728. struct rtl_priv *rtlpriv = btcoexist->adapter;
  1729. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1730. u32 wifi_bw;
  1731. bool long_dist = false;
  1732. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1733. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1734. if ((bt_rssi_state == BTC_RSSI_STATE_LOW ||
  1735. bt_rssi_state == BTC_RSSI_STATE_STAY_LOW) &&
  1736. (wifi_rssi_state == BTC_RSSI_STATE_LOW ||
  1737. wifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1738. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  1739. "[BTCoex], A2dp, wifi/bt rssi both LOW!!\n");
  1740. long_dist = true;
  1741. }
  1742. if (long_dist) {
  1743. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 2);
  1744. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, true,
  1745. 0x4);
  1746. } else {
  1747. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1748. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false,
  1749. 0x8);
  1750. }
  1751. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1752. if (long_dist)
  1753. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0);
  1754. else
  1755. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1756. if (long_dist) {
  1757. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 17);
  1758. coex_dm->auto_tdma_adjust = false;
  1759. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1760. } else {
  1761. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1762. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1763. btc8192e2ant_tdma_duration_adjust(btcoexist, false,
  1764. true, 1);
  1765. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1766. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1767. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1768. btc8192e2ant_tdma_duration_adjust(btcoexist, false,
  1769. false, 1);
  1770. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1771. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1772. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1773. btc8192e2ant_tdma_duration_adjust(btcoexist, false,
  1774. false, 1);
  1775. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1776. }
  1777. }
  1778. /* sw mechanism */
  1779. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1780. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1781. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1782. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1783. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1784. false, false);
  1785. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1786. false, 0x18);
  1787. } else {
  1788. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1789. false, false);
  1790. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1791. false, 0x18);
  1792. }
  1793. } else {
  1794. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1795. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1796. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1797. false, false);
  1798. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1799. false, 0x18);
  1800. } else {
  1801. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1802. false, false);
  1803. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1804. false, 0x18);
  1805. }
  1806. }
  1807. }
  1808. static void btc8192e2ant_action_a2dp_pan_hs(struct btc_coexist *btcoexist)
  1809. {
  1810. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1811. u32 wifi_bw;
  1812. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1813. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1814. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1815. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1816. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1817. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1818. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1819. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1820. btc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 2);
  1821. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1822. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1823. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1824. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 2);
  1825. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1826. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1827. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1828. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 2);
  1829. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1830. }
  1831. /* sw mechanism */
  1832. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1833. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1834. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1835. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1836. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1837. false, false);
  1838. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1839. true, 0x6);
  1840. } else {
  1841. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1842. false, false);
  1843. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1844. true, 0x6);
  1845. }
  1846. } else {
  1847. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1848. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1849. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1850. false, false);
  1851. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1852. true, 0x6);
  1853. } else {
  1854. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1855. false, false);
  1856. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1857. true, 0x6);
  1858. }
  1859. }
  1860. }
  1861. static void btc8192e2ant_action_pan_edr(struct btc_coexist *btcoexist)
  1862. {
  1863. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1864. u32 wifi_bw;
  1865. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1866. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1867. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1868. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1869. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1870. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1871. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1872. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1873. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1874. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 5);
  1875. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1876. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1877. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1878. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
  1879. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1880. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1881. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1882. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 1);
  1883. }
  1884. /* sw mechanism */
  1885. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1886. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1887. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1888. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1889. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1890. false, false);
  1891. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1892. false, 0x18);
  1893. } else {
  1894. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1895. false, false);
  1896. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1897. false, 0x18);
  1898. }
  1899. } else {
  1900. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1901. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1902. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1903. false, false);
  1904. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1905. false, 0x18);
  1906. } else {
  1907. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1908. false, false);
  1909. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1910. false, 0x18);
  1911. }
  1912. }
  1913. }
  1914. /* PAN(HS) only */
  1915. static void btc8192e2ant_action_pan_hs(struct btc_coexist *btcoexist)
  1916. {
  1917. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1918. u32 wifi_bw;
  1919. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1920. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1921. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1922. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1923. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1924. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1925. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1926. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1927. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1928. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1929. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1930. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1931. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1932. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1933. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1934. }
  1935. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, false, 1);
  1936. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1937. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1938. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1939. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1940. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1941. false, false);
  1942. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1943. false, 0x18);
  1944. } else {
  1945. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1946. false, false);
  1947. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1948. false, 0x18);
  1949. }
  1950. } else {
  1951. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1952. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1953. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1954. false, false);
  1955. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1956. false, 0x18);
  1957. } else {
  1958. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  1959. false, false);
  1960. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  1961. false, 0x18);
  1962. }
  1963. }
  1964. }
  1965. /* PAN(EDR)+A2DP */
  1966. static void btc8192e2ant_action_pan_edr_a2dp(struct btc_coexist *btcoexist)
  1967. {
  1968. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  1969. u32 wifi_bw;
  1970. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  1971. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  1972. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  1973. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  1974. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  1975. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2);
  1976. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  1977. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  1978. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  1979. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  1980. btc8192e2ant_tdma_duration_adjust(btcoexist, false, true, 3);
  1981. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  1982. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  1983. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  1984. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 3);
  1985. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1986. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1987. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  1988. btc8192e2ant_tdma_duration_adjust(btcoexist, false, false, 3);
  1989. }
  1990. /* sw mechanism */
  1991. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  1992. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  1993. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  1994. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  1995. false, false);
  1996. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  1997. false, 0x18);
  1998. } else {
  1999. btc8192e2ant_sw_mechanism1(btcoexist, true, false,
  2000. false, false);
  2001. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2002. false, 0x18);
  2003. }
  2004. } else {
  2005. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2006. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2007. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  2008. false, false);
  2009. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2010. false, 0x18);
  2011. } else {
  2012. btc8192e2ant_sw_mechanism1(btcoexist, false, false,
  2013. false, false);
  2014. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2015. false, 0x18);
  2016. }
  2017. }
  2018. }
  2019. static void btc8192e2ant_action_pan_edr_hid(struct btc_coexist *btcoexist)
  2020. {
  2021. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  2022. u32 wifi_bw;
  2023. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2024. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2025. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2026. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2027. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2028. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  2029. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  2030. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2031. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2032. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2033. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 14);
  2034. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2035. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2036. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2037. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC, true, 10);
  2038. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2039. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2040. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2041. btc8192e2ant_ps_tdma(btcoexist, NORMAL_EXEC,
  2042. true, 10);
  2043. }
  2044. /* sw mechanism */
  2045. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2046. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2047. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2048. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2049. false, false);
  2050. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2051. false, 0x18);
  2052. } else {
  2053. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2054. false, false);
  2055. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2056. false, 0x18);
  2057. }
  2058. } else {
  2059. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2060. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2061. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2062. false, false);
  2063. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2064. false, 0x18);
  2065. } else {
  2066. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2067. false, false);
  2068. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2069. false, 0x18);
  2070. }
  2071. }
  2072. }
  2073. /* HID+A2DP+PAN(EDR) */
  2074. static void btc8192e2ant_action_hid_a2dp_pan_edr(struct btc_coexist *btcoexist)
  2075. {
  2076. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  2077. u32 wifi_bw;
  2078. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2079. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2080. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2081. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2082. btc8192e2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 6);
  2083. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2084. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  2085. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2086. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2087. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2088. btc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 3);
  2089. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2090. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2091. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2092. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
  2093. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2094. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2095. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2096. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 3);
  2097. }
  2098. /* sw mechanism */
  2099. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2100. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2101. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2102. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2103. false, false);
  2104. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2105. false, 0x18);
  2106. } else {
  2107. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2108. false, false);
  2109. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2110. false, 0x18);
  2111. }
  2112. } else {
  2113. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2114. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2115. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2116. false, false);
  2117. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2118. false, 0x18);
  2119. } else {
  2120. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2121. false, false);
  2122. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2123. false, 0x18);
  2124. }
  2125. }
  2126. }
  2127. static void btc8192e2ant_action_hid_a2dp(struct btc_coexist *btcoexist)
  2128. {
  2129. u8 wifi_rssi_state, bt_rssi_state = BTC_RSSI_STATE_HIGH;
  2130. u32 wifi_bw;
  2131. wifi_rssi_state = btc8192e2ant_wifi_rssi_state(btcoexist, 0, 2, 15, 0);
  2132. bt_rssi_state = btc8192e2ant_bt_rssi_state(btcoexist, 3, 34, 42);
  2133. btc8192e2ant_switch_ss_type(btcoexist, NORMAL_EXEC, 1);
  2134. btc8192e2ant_limited_rx(btcoexist, NORMAL_EXEC, false, false, 0x8);
  2135. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2136. btc8192e2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 3);
  2137. if ((bt_rssi_state == BTC_RSSI_STATE_LOW) ||
  2138. (bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) {
  2139. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0);
  2140. btc8192e2ant_tdma_duration_adjust(btcoexist, true, true, 2);
  2141. } else if ((bt_rssi_state == BTC_RSSI_STATE_MEDIUM) ||
  2142. (bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) {
  2143. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2);
  2144. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
  2145. } else if ((bt_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2146. (bt_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2147. btc8192e2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 4);
  2148. btc8192e2ant_tdma_duration_adjust(btcoexist, true, false, 2);
  2149. }
  2150. /* sw mechanism */
  2151. if (BTC_WIFI_BW_HT40 == wifi_bw) {
  2152. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2153. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2154. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2155. false, false);
  2156. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2157. false, 0x18);
  2158. } else {
  2159. btc8192e2ant_sw_mechanism1(btcoexist, true, true,
  2160. false, false);
  2161. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2162. false, 0x18);
  2163. }
  2164. } else {
  2165. if ((wifi_rssi_state == BTC_RSSI_STATE_HIGH) ||
  2166. (wifi_rssi_state == BTC_RSSI_STATE_STAY_HIGH)) {
  2167. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2168. false, false);
  2169. btc8192e2ant_sw_mechanism2(btcoexist, true, false,
  2170. false, 0x18);
  2171. } else {
  2172. btc8192e2ant_sw_mechanism1(btcoexist, false, true,
  2173. false, false);
  2174. btc8192e2ant_sw_mechanism2(btcoexist, false, false,
  2175. false, 0x18);
  2176. }
  2177. }
  2178. }
  2179. static void btc8192e2ant_run_coexist_mechanism(struct btc_coexist *btcoexist)
  2180. {
  2181. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2182. u8 algorithm = 0;
  2183. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2184. "[BTCoex], RunCoexistMechanism()===>\n");
  2185. if (btcoexist->manual_control) {
  2186. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2187. "[BTCoex], return for Manual CTRL <===\n");
  2188. return;
  2189. }
  2190. if (coex_sta->under_ips) {
  2191. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2192. "[BTCoex], wifi is under IPS !!!\n");
  2193. return;
  2194. }
  2195. algorithm = btc8192e2ant_action_algorithm(btcoexist);
  2196. if (coex_sta->c2h_bt_inquiry_page &&
  2197. (BT_8192E_2ANT_COEX_ALGO_PANHS != algorithm)) {
  2198. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2199. "[BTCoex], BT is under inquiry/page scan !!\n");
  2200. btc8192e2ant_action_bt_inquiry(btcoexist);
  2201. return;
  2202. }
  2203. coex_dm->cur_algorithm = algorithm;
  2204. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2205. "[BTCoex], Algorithm = %d\n", coex_dm->cur_algorithm);
  2206. if (btc8192e2ant_is_common_action(btcoexist)) {
  2207. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2208. "[BTCoex], Action 2-Ant common\n");
  2209. coex_dm->auto_tdma_adjust = false;
  2210. } else {
  2211. if (coex_dm->cur_algorithm != coex_dm->pre_algorithm) {
  2212. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2213. "[BTCoex] preAlgorithm=%d, curAlgorithm=%d\n",
  2214. coex_dm->pre_algorithm,
  2215. coex_dm->cur_algorithm);
  2216. coex_dm->auto_tdma_adjust = false;
  2217. }
  2218. switch (coex_dm->cur_algorithm) {
  2219. case BT_8192E_2ANT_COEX_ALGO_SCO:
  2220. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2221. "Action 2-Ant, algorithm = SCO\n");
  2222. btc8192e2ant_action_sco(btcoexist);
  2223. break;
  2224. case BT_8192E_2ANT_COEX_ALGO_SCO_PAN:
  2225. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2226. "Action 2-Ant, algorithm = SCO+PAN(EDR)\n");
  2227. btc8192e2ant_action_sco_pan(btcoexist);
  2228. break;
  2229. case BT_8192E_2ANT_COEX_ALGO_HID:
  2230. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2231. "Action 2-Ant, algorithm = HID\n");
  2232. btc8192e2ant_action_hid(btcoexist);
  2233. break;
  2234. case BT_8192E_2ANT_COEX_ALGO_A2DP:
  2235. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2236. "Action 2-Ant, algorithm = A2DP\n");
  2237. btc8192e2ant_action_a2dp(btcoexist);
  2238. break;
  2239. case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS:
  2240. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2241. "Action 2-Ant, algorithm = A2DP+PAN(HS)\n");
  2242. btc8192e2ant_action_a2dp_pan_hs(btcoexist);
  2243. break;
  2244. case BT_8192E_2ANT_COEX_ALGO_PANEDR:
  2245. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2246. "Action 2-Ant, algorithm = PAN(EDR)\n");
  2247. btc8192e2ant_action_pan_edr(btcoexist);
  2248. break;
  2249. case BT_8192E_2ANT_COEX_ALGO_PANHS:
  2250. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2251. "Action 2-Ant, algorithm = HS mode\n");
  2252. btc8192e2ant_action_pan_hs(btcoexist);
  2253. break;
  2254. case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP:
  2255. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2256. "Action 2-Ant, algorithm = PAN+A2DP\n");
  2257. btc8192e2ant_action_pan_edr_a2dp(btcoexist);
  2258. break;
  2259. case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID:
  2260. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2261. "Action 2-Ant, algorithm = PAN(EDR)+HID\n");
  2262. btc8192e2ant_action_pan_edr_hid(btcoexist);
  2263. break;
  2264. case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR:
  2265. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2266. "Action 2-Ant, algorithm = HID+A2DP+PAN\n");
  2267. btc8192e2ant_action_hid_a2dp_pan_edr(btcoexist);
  2268. break;
  2269. case BT_8192E_2ANT_COEX_ALGO_HID_A2DP:
  2270. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2271. "Action 2-Ant, algorithm = HID+A2DP\n");
  2272. btc8192e2ant_action_hid_a2dp(btcoexist);
  2273. break;
  2274. default:
  2275. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2276. "Action 2-Ant, algorithm = unknown!!\n");
  2277. /* btc8192e2ant_coex_all_off(btcoexist); */
  2278. break;
  2279. }
  2280. coex_dm->pre_algorithm = coex_dm->cur_algorithm;
  2281. }
  2282. }
  2283. static void btc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist,
  2284. bool backup)
  2285. {
  2286. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2287. u16 u16tmp = 0;
  2288. u8 u8tmp = 0;
  2289. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2290. "[BTCoex], 2Ant Init HW Config!!\n");
  2291. if (backup) {
  2292. /* backup rf 0x1e value */
  2293. coex_dm->bt_rf0x1e_backup =
  2294. btcoexist->btc_get_rf_reg(btcoexist, BTC_RF_A,
  2295. 0x1e, 0xfffff);
  2296. coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist,
  2297. 0x430);
  2298. coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist,
  2299. 0x434);
  2300. coex_dm->backup_retry_limit = btcoexist->btc_read_2byte(
  2301. btcoexist,
  2302. 0x42a);
  2303. coex_dm->backup_ampdu_maxtime = btcoexist->btc_read_1byte(
  2304. btcoexist,
  2305. 0x456);
  2306. }
  2307. /* antenna sw ctrl to bt */
  2308. btcoexist->btc_write_1byte(btcoexist, 0x4f, 0x6);
  2309. btcoexist->btc_write_1byte(btcoexist, 0x944, 0x24);
  2310. btcoexist->btc_write_4byte(btcoexist, 0x930, 0x700700);
  2311. btcoexist->btc_write_1byte(btcoexist, 0x92c, 0x20);
  2312. if (btcoexist->chip_interface == BTC_INTF_USB)
  2313. btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30430004);
  2314. else
  2315. btcoexist->btc_write_4byte(btcoexist, 0x64, 0x30030004);
  2316. btc8192e2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0);
  2317. /* antenna switch control parameter */
  2318. btcoexist->btc_write_4byte(btcoexist, 0x858, 0x55555555);
  2319. /* coex parameters */
  2320. btcoexist->btc_write_1byte(btcoexist, 0x778, 0x3);
  2321. /* 0x790[5:0] = 0x5 */
  2322. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x790);
  2323. u8tmp &= 0xc0;
  2324. u8tmp |= 0x5;
  2325. btcoexist->btc_write_1byte(btcoexist, 0x790, u8tmp);
  2326. /* enable counter statistics */
  2327. btcoexist->btc_write_1byte(btcoexist, 0x76e, 0x4);
  2328. /* enable PTA */
  2329. btcoexist->btc_write_1byte(btcoexist, 0x40, 0x20);
  2330. /* enable mailbox interface */
  2331. u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x40);
  2332. u16tmp |= BIT9;
  2333. btcoexist->btc_write_2byte(btcoexist, 0x40, u16tmp);
  2334. /* enable PTA I2C mailbox */
  2335. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x101);
  2336. u8tmp |= BIT4;
  2337. btcoexist->btc_write_1byte(btcoexist, 0x101, u8tmp);
  2338. /* enable bt clock when wifi is disabled. */
  2339. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x93);
  2340. u8tmp |= BIT0;
  2341. btcoexist->btc_write_1byte(btcoexist, 0x93, u8tmp);
  2342. /* enable bt clock when suspend. */
  2343. u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x7);
  2344. u8tmp |= BIT0;
  2345. btcoexist->btc_write_1byte(btcoexist, 0x7, u8tmp);
  2346. }
  2347. /************************************************************
  2348. * extern function start with ex_btc8192e2ant_
  2349. ************************************************************/
  2350. void ex_btc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist)
  2351. {
  2352. btc8192e2ant_init_hwconfig(btcoexist, true);
  2353. }
  2354. void ex_btc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist)
  2355. {
  2356. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2357. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2358. "[BTCoex], Coex Mechanism Init!!\n");
  2359. btc8192e2ant_init_coex_dm(btcoexist);
  2360. }
  2361. void ex_btc8192e2ant_display_coex_info(struct btc_coexist *btcoexist)
  2362. {
  2363. struct btc_board_info *board_info = &btcoexist->board_info;
  2364. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  2365. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2366. u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0;
  2367. u16 u16tmp[4];
  2368. u32 u32tmp[4];
  2369. bool roam = false, scan = false, link = false, wifi_under_5g = false;
  2370. bool bt_hs_on = false, wifi_busy = false;
  2371. int wifi_rssi = 0, bt_hs_rssi = 0;
  2372. u32 wifi_bw, wifi_traffic_dir;
  2373. u8 wifi_dot11_chnl, wifi_hs_chnl;
  2374. u32 fw_ver = 0, bt_patch_ver = 0;
  2375. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2376. "\r\n ============[BT Coexist info]============");
  2377. if (btcoexist->manual_control) {
  2378. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2379. "\r\n ===========[Under Manual Control]===========");
  2380. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2381. "\r\n ==========================================");
  2382. }
  2383. if (!board_info->bt_exist) {
  2384. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n BT not exists !!!");
  2385. return;
  2386. }
  2387. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2388. "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:",
  2389. board_info->pg_ant_num, board_info->btdm_ant_num);
  2390. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %d",
  2391. "BT stack/ hci ext ver",
  2392. ((stack_info->profile_notified) ? "Yes" : "No"),
  2393. stack_info->hci_version);
  2394. btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver);
  2395. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
  2396. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2397. "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)",
  2398. "CoexVer/ FwVer/ PatchVer",
  2399. glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
  2400. fw_ver, bt_patch_ver, bt_patch_ver);
  2401. btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on);
  2402. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_DOT11_CHNL,
  2403. &wifi_dot11_chnl);
  2404. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifi_hs_chnl);
  2405. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d(%d)",
  2406. "Dot11 channel / HsMode(HsChnl)",
  2407. wifi_dot11_chnl, bt_hs_on, wifi_hs_chnl);
  2408. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %3ph ",
  2409. "H2C Wifi inform bt chnl Info", coex_dm->wifi_chnl_info);
  2410. btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi);
  2411. btcoexist->btc_get(btcoexist, BTC_GET_S4_HS_RSSI, &bt_hs_rssi);
  2412. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
  2413. "Wifi rssi/ HS rssi", wifi_rssi, bt_hs_rssi);
  2414. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan);
  2415. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link);
  2416. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam);
  2417. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ",
  2418. "Wifi link/ roam/ scan", link, roam, scan);
  2419. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g);
  2420. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2421. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy);
  2422. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
  2423. &wifi_traffic_dir);
  2424. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s / %s/ %s ",
  2425. "Wifi status", (wifi_under_5g ? "5G" : "2.4G"),
  2426. ((BTC_WIFI_BW_LEGACY == wifi_bw) ? "Legacy" :
  2427. (((BTC_WIFI_BW_HT40 == wifi_bw) ? "HT40" : "HT20"))),
  2428. ((!wifi_busy) ? "idle" :
  2429. ((BTC_WIFI_TRAFFIC_TX == wifi_traffic_dir) ?
  2430. "uplink" : "downlink")));
  2431. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = [%s/ %d/ %d] ",
  2432. "BT [status/ rssi/ retryCnt]",
  2433. ((btcoexist->bt_info.bt_disabled) ? ("disabled") :
  2434. ((coex_sta->c2h_bt_inquiry_page) ?
  2435. ("inquiry/page scan") :
  2436. ((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE ==
  2437. coex_dm->bt_status) ? "non-connected idle" :
  2438. ((BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE ==
  2439. coex_dm->bt_status) ? "connected-idle" : "busy")))),
  2440. coex_sta->bt_rssi, coex_sta->bt_retry_cnt);
  2441. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d / %d / %d / %d",
  2442. "SCO/HID/PAN/A2DP", stack_info->sco_exist,
  2443. stack_info->hid_exist, stack_info->pan_exist,
  2444. stack_info->a2dp_exist);
  2445. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_BT_LINK_INFO);
  2446. bt_info_ext = coex_sta->bt_info_ext;
  2447. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s",
  2448. "BT Info A2DP rate",
  2449. (bt_info_ext&BIT0) ? "Basic rate" : "EDR rate");
  2450. for (i = 0; i < BT_INFO_SRC_8192E_2ANT_MAX; i++) {
  2451. if (coex_sta->bt_info_c2h_cnt[i]) {
  2452. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2453. "\r\n %-35s = %7ph(%d)",
  2454. glbt_info_src_8192e_2ant[i],
  2455. coex_sta->bt_info_c2h[i],
  2456. coex_sta->bt_info_c2h_cnt[i]);
  2457. }
  2458. }
  2459. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %s/%s",
  2460. "PS state, IPS/LPS",
  2461. ((coex_sta->under_ips ? "IPS ON" : "IPS OFF")),
  2462. ((coex_sta->under_lps ? "LPS ON" : "LPS OFF")));
  2463. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD);
  2464. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "SS Type",
  2465. coex_dm->cur_ss_type);
  2466. /* Sw mechanism */
  2467. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
  2468. "============[Sw mechanism]============");
  2469. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d ",
  2470. "SM1[ShRf/ LpRA/ LimDig]", coex_dm->cur_rf_rx_lpf_shrink,
  2471. coex_dm->cur_low_penalty_ra, coex_dm->limited_dig);
  2472. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d/ %d(0x%x) ",
  2473. "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]",
  2474. coex_dm->cur_agc_table_en, coex_dm->cur_adc_back_off,
  2475. coex_dm->cur_dac_swing_on, coex_dm->cur_dac_swing_lvl);
  2476. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x ", "Rate Mask",
  2477. btcoexist->bt_info.ra_mask);
  2478. /* Fw mechanism */
  2479. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
  2480. "============[Fw mechanism]============");
  2481. ps_tdma_case = coex_dm->cur_ps_tdma;
  2482. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2483. "\r\n %-35s = %5ph case-%d (auto:%d)",
  2484. "PS TDMA", coex_dm->ps_tdma_para,
  2485. ps_tdma_case, coex_dm->auto_tdma_adjust);
  2486. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d ",
  2487. "DecBtPwr/ IgnWlanAct",
  2488. coex_dm->cur_dec_bt_pwr, coex_dm->cur_ignore_wlan_act);
  2489. /* Hw setting */
  2490. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s",
  2491. "============[Hw setting]============");
  2492. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x",
  2493. "RF-A, 0x1e initVal", coex_dm->bt_rf0x1e_backup);
  2494. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
  2495. "backup ARFR1/ARFR2/RL/AMaxTime", coex_dm->backup_arfr_cnt1,
  2496. coex_dm->backup_arfr_cnt2, coex_dm->backup_retry_limit,
  2497. coex_dm->backup_ampdu_maxtime);
  2498. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x430);
  2499. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x434);
  2500. u16tmp[0] = btcoexist->btc_read_2byte(btcoexist, 0x42a);
  2501. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x456);
  2502. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x",
  2503. "0x430/0x434/0x42a/0x456",
  2504. u32tmp[0], u32tmp[1], u16tmp[0], u8tmp[0]);
  2505. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc04);
  2506. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xd04);
  2507. u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x90c);
  2508. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x",
  2509. "0xc04/ 0xd04/ 0x90c", u32tmp[0], u32tmp[1], u32tmp[2]);
  2510. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778);
  2511. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0x778",
  2512. u8tmp[0]);
  2513. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x92c);
  2514. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x930);
  2515. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
  2516. "0x92c/ 0x930", (u8tmp[0]), u32tmp[0]);
  2517. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x40);
  2518. u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x4f);
  2519. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
  2520. "0x40/ 0x4f", u8tmp[0], u8tmp[1]);
  2521. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550);
  2522. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522);
  2523. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x/ 0x%x",
  2524. "0x550(bcn ctrl)/0x522", u32tmp[0], u8tmp[0]);
  2525. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xc50);
  2526. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = 0x%x", "0xc50(dig)",
  2527. u32tmp[0]);
  2528. u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0);
  2529. u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4);
  2530. u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8);
  2531. u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x6cc);
  2532. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  2533. "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x",
  2534. "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)",
  2535. u32tmp[0], u32tmp[1], u32tmp[2], u8tmp[0]);
  2536. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
  2537. "0x770(hp rx[31:16]/tx[15:0])",
  2538. coex_sta->high_priority_rx, coex_sta->high_priority_tx);
  2539. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "\r\n %-35s = %d/ %d",
  2540. "0x774(lp rx[31:16]/tx[15:0])",
  2541. coex_sta->low_priority_rx, coex_sta->low_priority_tx);
  2542. #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 1)
  2543. btc8192e2ant_monitor_bt_ctr(btcoexist);
  2544. #endif
  2545. btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS);
  2546. }
  2547. void ex_btc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type)
  2548. {
  2549. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2550. if (BTC_IPS_ENTER == type) {
  2551. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2552. "[BTCoex], IPS ENTER notify\n");
  2553. coex_sta->under_ips = true;
  2554. btc8192e2ant_coex_all_off(btcoexist);
  2555. } else if (BTC_IPS_LEAVE == type) {
  2556. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2557. "[BTCoex], IPS LEAVE notify\n");
  2558. coex_sta->under_ips = false;
  2559. }
  2560. }
  2561. void ex_btc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type)
  2562. {
  2563. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2564. if (BTC_LPS_ENABLE == type) {
  2565. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2566. "[BTCoex], LPS ENABLE notify\n");
  2567. coex_sta->under_lps = true;
  2568. } else if (BTC_LPS_DISABLE == type) {
  2569. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2570. "[BTCoex], LPS DISABLE notify\n");
  2571. coex_sta->under_lps = false;
  2572. }
  2573. }
  2574. void ex_btc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type)
  2575. {
  2576. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2577. if (BTC_SCAN_START == type)
  2578. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2579. "[BTCoex], SCAN START notify\n");
  2580. else if (BTC_SCAN_FINISH == type)
  2581. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2582. "[BTCoex], SCAN FINISH notify\n");
  2583. }
  2584. void ex_btc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type)
  2585. {
  2586. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2587. if (BTC_ASSOCIATE_START == type)
  2588. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2589. "[BTCoex], CONNECT START notify\n");
  2590. else if (BTC_ASSOCIATE_FINISH == type)
  2591. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2592. "[BTCoex], CONNECT FINISH notify\n");
  2593. }
  2594. void ex_btc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
  2595. u8 type)
  2596. {
  2597. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2598. u8 h2c_parameter[3] = {0};
  2599. u32 wifi_bw;
  2600. u8 wifi_center_chnl;
  2601. if (btcoexist->manual_control ||
  2602. btcoexist->stop_coex_dm ||
  2603. btcoexist->bt_info.bt_disabled)
  2604. return;
  2605. if (BTC_MEDIA_CONNECT == type)
  2606. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2607. "[BTCoex], MEDIA connect notify\n");
  2608. else
  2609. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2610. "[BTCoex], MEDIA disconnect notify\n");
  2611. /* only 2.4G we need to inform bt the chnl mask */
  2612. btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL,
  2613. &wifi_center_chnl);
  2614. if ((BTC_MEDIA_CONNECT == type) &&
  2615. (wifi_center_chnl <= 14)) {
  2616. h2c_parameter[0] = 0x1;
  2617. h2c_parameter[1] = wifi_center_chnl;
  2618. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw);
  2619. if (BTC_WIFI_BW_HT40 == wifi_bw)
  2620. h2c_parameter[2] = 0x30;
  2621. else
  2622. h2c_parameter[2] = 0x20;
  2623. }
  2624. coex_dm->wifi_chnl_info[0] = h2c_parameter[0];
  2625. coex_dm->wifi_chnl_info[1] = h2c_parameter[1];
  2626. coex_dm->wifi_chnl_info[2] = h2c_parameter[2];
  2627. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2628. "[BTCoex], FW write 0x66 = 0x%x\n",
  2629. h2c_parameter[0] << 16 | h2c_parameter[1] << 8 |
  2630. h2c_parameter[2]);
  2631. btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter);
  2632. }
  2633. void ex_btc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
  2634. u8 type)
  2635. {
  2636. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2637. if (type == BTC_PACKET_DHCP)
  2638. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2639. "[BTCoex], DHCP Packet notify\n");
  2640. }
  2641. void ex_btc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
  2642. u8 *tmp_buf, u8 length)
  2643. {
  2644. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2645. u8 bt_info = 0;
  2646. u8 i, rsp_source = 0;
  2647. bool bt_busy = false, limited_dig = false;
  2648. bool wifi_connected = false;
  2649. coex_sta->c2h_bt_info_req_sent = false;
  2650. rsp_source = tmp_buf[0] & 0xf;
  2651. if (rsp_source >= BT_INFO_SRC_8192E_2ANT_MAX)
  2652. rsp_source = BT_INFO_SRC_8192E_2ANT_WIFI_FW;
  2653. coex_sta->bt_info_c2h_cnt[rsp_source]++;
  2654. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2655. "[BTCoex], Bt info[%d], length=%d, hex data = [",
  2656. rsp_source, length);
  2657. for (i = 0; i < length; i++) {
  2658. coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i];
  2659. if (i == 1)
  2660. bt_info = tmp_buf[i];
  2661. if (i == length-1)
  2662. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2663. "0x%02x]\n", tmp_buf[i]);
  2664. else
  2665. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2666. "0x%02x, ", tmp_buf[i]);
  2667. }
  2668. if (BT_INFO_SRC_8192E_2ANT_WIFI_FW != rsp_source) {
  2669. /* [3:0] */
  2670. coex_sta->bt_retry_cnt =
  2671. coex_sta->bt_info_c2h[rsp_source][2] & 0xf;
  2672. coex_sta->bt_rssi =
  2673. coex_sta->bt_info_c2h[rsp_source][3] * 2 + 10;
  2674. coex_sta->bt_info_ext =
  2675. coex_sta->bt_info_c2h[rsp_source][4];
  2676. /* Here we need to resend some wifi info to BT
  2677. * because bt is reset and loss of the info.
  2678. */
  2679. if ((coex_sta->bt_info_ext & BIT1)) {
  2680. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2681. "bit1, send wifi BW&Chnl to BT!!\n");
  2682. btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED,
  2683. &wifi_connected);
  2684. if (wifi_connected)
  2685. ex_btc8192e2ant_media_status_notify(
  2686. btcoexist,
  2687. BTC_MEDIA_CONNECT);
  2688. else
  2689. ex_btc8192e2ant_media_status_notify(
  2690. btcoexist,
  2691. BTC_MEDIA_DISCONNECT);
  2692. }
  2693. if ((coex_sta->bt_info_ext & BIT3)) {
  2694. if (!btcoexist->manual_control &&
  2695. !btcoexist->stop_coex_dm) {
  2696. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2697. "bit3, BT NOT ignore Wlan active!\n");
  2698. btc8192e2ant_ignore_wlan_act(btcoexist,
  2699. FORCE_EXEC,
  2700. false);
  2701. }
  2702. } else {
  2703. /* BT already NOT ignore Wlan active,
  2704. * do nothing here.
  2705. */
  2706. }
  2707. #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
  2708. if ((coex_sta->bt_info_ext & BIT4)) {
  2709. /* BT auto report already enabled, do nothing */
  2710. } else {
  2711. btc8192e2ant_bt_auto_report(btcoexist, FORCE_EXEC,
  2712. true);
  2713. }
  2714. #endif
  2715. }
  2716. /* check BIT2 first ==> check if bt is under inquiry or page scan */
  2717. if (bt_info & BT_INFO_8192E_2ANT_B_INQ_PAGE)
  2718. coex_sta->c2h_bt_inquiry_page = true;
  2719. else
  2720. coex_sta->c2h_bt_inquiry_page = false;
  2721. /* set link exist status */
  2722. if (!(bt_info&BT_INFO_8192E_2ANT_B_CONNECTION)) {
  2723. coex_sta->bt_link_exist = false;
  2724. coex_sta->pan_exist = false;
  2725. coex_sta->a2dp_exist = false;
  2726. coex_sta->hid_exist = false;
  2727. coex_sta->sco_exist = false;
  2728. } else {/* connection exists */
  2729. coex_sta->bt_link_exist = true;
  2730. if (bt_info & BT_INFO_8192E_2ANT_B_FTP)
  2731. coex_sta->pan_exist = true;
  2732. else
  2733. coex_sta->pan_exist = false;
  2734. if (bt_info & BT_INFO_8192E_2ANT_B_A2DP)
  2735. coex_sta->a2dp_exist = true;
  2736. else
  2737. coex_sta->a2dp_exist = false;
  2738. if (bt_info & BT_INFO_8192E_2ANT_B_HID)
  2739. coex_sta->hid_exist = true;
  2740. else
  2741. coex_sta->hid_exist = false;
  2742. if (bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO)
  2743. coex_sta->sco_exist = true;
  2744. else
  2745. coex_sta->sco_exist = false;
  2746. }
  2747. btc8192e2ant_update_bt_link_info(btcoexist);
  2748. if (!(bt_info & BT_INFO_8192E_2ANT_B_CONNECTION)) {
  2749. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE;
  2750. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2751. "[BTCoex], BT Non-Connected idle!!!\n");
  2752. } else if (bt_info == BT_INFO_8192E_2ANT_B_CONNECTION) {
  2753. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE;
  2754. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2755. "[BTCoex], bt_infoNotify(), BT Connected-idle!!!\n");
  2756. } else if ((bt_info & BT_INFO_8192E_2ANT_B_SCO_ESCO) ||
  2757. (bt_info & BT_INFO_8192E_2ANT_B_SCO_BUSY)) {
  2758. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_SCO_BUSY;
  2759. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2760. "[BTCoex], bt_infoNotify(), BT SCO busy!!!\n");
  2761. } else if (bt_info & BT_INFO_8192E_2ANT_B_ACL_BUSY) {
  2762. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_ACL_BUSY;
  2763. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2764. "[BTCoex], bt_infoNotify(), BT ACL busy!!!\n");
  2765. } else {
  2766. coex_dm->bt_status = BT_8192E_2ANT_BT_STATUS_MAX;
  2767. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2768. "[BTCoex]bt_infoNotify(), BT Non-Defined state!!!\n");
  2769. }
  2770. if ((BT_8192E_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) ||
  2771. (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) ||
  2772. (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) {
  2773. bt_busy = true;
  2774. limited_dig = true;
  2775. } else {
  2776. bt_busy = false;
  2777. limited_dig = false;
  2778. }
  2779. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy);
  2780. coex_dm->limited_dig = limited_dig;
  2781. btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_LIMITED_DIG, &limited_dig);
  2782. btc8192e2ant_run_coexist_mechanism(btcoexist);
  2783. }
  2784. void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist)
  2785. {
  2786. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2787. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD, "[BTCoex], Halt notify\n");
  2788. btc8192e2ant_ignore_wlan_act(btcoexist, FORCE_EXEC, true);
  2789. ex_btc8192e2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT);
  2790. }
  2791. void ex_btc8192e2ant_periodical(struct btc_coexist *btcoexist)
  2792. {
  2793. struct rtl_priv *rtlpriv = btcoexist->adapter;
  2794. static u8 dis_ver_info_cnt;
  2795. u32 fw_ver = 0, bt_patch_ver = 0;
  2796. struct btc_board_info *board_info = &btcoexist->board_info;
  2797. struct btc_stack_info *stack_info = &btcoexist->stack_info;
  2798. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2799. "=======================Periodical=======================\n");
  2800. if (dis_ver_info_cnt <= 5) {
  2801. dis_ver_info_cnt += 1;
  2802. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2803. "************************************************\n");
  2804. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2805. "Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n",
  2806. board_info->pg_ant_num, board_info->btdm_ant_num,
  2807. board_info->btdm_ant_pos);
  2808. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2809. "BT stack/ hci ext ver = %s / %d\n",
  2810. ((stack_info->profile_notified) ? "Yes" : "No"),
  2811. stack_info->hci_version);
  2812. btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER,
  2813. &bt_patch_ver);
  2814. btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver);
  2815. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2816. "CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n",
  2817. glcoex_ver_date_8192e_2ant, glcoex_ver_8192e_2ant,
  2818. fw_ver, bt_patch_ver, bt_patch_ver);
  2819. RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
  2820. "************************************************\n");
  2821. }
  2822. #if (BT_AUTO_REPORT_ONLY_8192E_2ANT == 0)
  2823. btc8192e2ant_query_bt_info(btcoexist);
  2824. btc8192e2ant_monitor_bt_ctr(btcoexist);
  2825. btc8192e2ant_monitor_bt_enable_disable(btcoexist);
  2826. #else
  2827. if (btc8192e2ant_is_wifi_status_changed(btcoexist) ||
  2828. coex_dm->auto_tdma_adjust)
  2829. btc8192e2ant_run_coexist_mechanism(btcoexist);
  2830. #endif
  2831. }