pcie.h 13 KB

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  1. /* @file mwifiex_pcie.h
  2. *
  3. * @brief This file contains definitions for PCI-E interface.
  4. * driver.
  5. *
  6. * Copyright (C) 2011-2014, Marvell International Ltd.
  7. *
  8. * This software file (the "File") is distributed by Marvell International
  9. * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  10. * (the "License"). You may use, redistribute and/or modify this File in
  11. * accordance with the terms and conditions of the License, a copy of which
  12. * is available by writing to the Free Software Foundation, Inc.,
  13. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  14. * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  15. *
  16. * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  17. * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  18. * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
  19. * this warranty disclaimer.
  20. */
  21. #ifndef _MWIFIEX_PCIE_H
  22. #define _MWIFIEX_PCIE_H
  23. #include <linux/completion.h>
  24. #include <linux/pci.h>
  25. #include <linux/interrupt.h>
  26. #include "decl.h"
  27. #include "main.h"
  28. #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
  29. #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
  30. #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
  31. #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
  32. #define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin"
  33. #define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin"
  34. #define PCIE_VENDOR_ID_MARVELL (0x11ab)
  35. #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b)
  36. #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
  37. #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
  38. #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
  39. #define PCIE8897_A0 0x1100
  40. #define PCIE8897_B0 0x1200
  41. #define PCIE8997_A0 0x10
  42. #define PCIE8997_A1 0x11
  43. #define CHIP_VER_PCIEUART 0x3
  44. #define CHIP_MAGIC_VALUE 0x24
  45. /* Constants for Buffer Descriptor (BD) rings */
  46. #define MWIFIEX_MAX_TXRX_BD 0x20
  47. #define MWIFIEX_TXBD_MASK 0x3F
  48. #define MWIFIEX_RXBD_MASK 0x3F
  49. #define MWIFIEX_MAX_EVT_BD 0x08
  50. #define MWIFIEX_EVTBD_MASK 0x0f
  51. /* PCIE INTERNAL REGISTERS */
  52. #define PCIE_SCRATCH_0_REG 0xC10
  53. #define PCIE_SCRATCH_1_REG 0xC14
  54. #define PCIE_CPU_INT_EVENT 0xC18
  55. #define PCIE_CPU_INT_STATUS 0xC1C
  56. #define PCIE_HOST_INT_STATUS 0xC30
  57. #define PCIE_HOST_INT_MASK 0xC34
  58. #define PCIE_HOST_INT_STATUS_MASK 0xC3C
  59. #define PCIE_SCRATCH_2_REG 0xC40
  60. #define PCIE_SCRATCH_3_REG 0xC44
  61. #define PCIE_SCRATCH_4_REG 0xCD0
  62. #define PCIE_SCRATCH_5_REG 0xCD4
  63. #define PCIE_SCRATCH_6_REG 0xCD8
  64. #define PCIE_SCRATCH_7_REG 0xCDC
  65. #define PCIE_SCRATCH_8_REG 0xCE0
  66. #define PCIE_SCRATCH_9_REG 0xCE4
  67. #define PCIE_SCRATCH_10_REG 0xCE8
  68. #define PCIE_SCRATCH_11_REG 0xCEC
  69. #define PCIE_SCRATCH_12_REG 0xCF0
  70. #define PCIE_SCRATCH_13_REG 0xCF4
  71. #define PCIE_SCRATCH_14_REG 0xCF8
  72. #define PCIE_SCRATCH_15_REG 0xCFC
  73. #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
  74. #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
  75. #define CPU_INTR_DNLD_RDY BIT(0)
  76. #define CPU_INTR_DOOR_BELL BIT(1)
  77. #define CPU_INTR_SLEEP_CFM_DONE BIT(2)
  78. #define CPU_INTR_RESET BIT(3)
  79. #define CPU_INTR_EVENT_DONE BIT(5)
  80. #define HOST_INTR_DNLD_DONE BIT(0)
  81. #define HOST_INTR_UPLD_RDY BIT(1)
  82. #define HOST_INTR_CMD_DONE BIT(2)
  83. #define HOST_INTR_EVENT_RDY BIT(3)
  84. #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \
  85. HOST_INTR_UPLD_RDY | \
  86. HOST_INTR_CMD_DONE | \
  87. HOST_INTR_EVENT_RDY)
  88. #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
  89. #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
  90. #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
  91. #define MWIFIEX_BD_FLAG_SOP BIT(0)
  92. #define MWIFIEX_BD_FLAG_EOP BIT(1)
  93. #define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
  94. #define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
  95. #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
  96. #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
  97. #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
  98. #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
  99. /* Max retry number of command write */
  100. #define MAX_WRITE_IOMEM_RETRY 2
  101. /* Define PCIE block size for firmware download */
  102. #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
  103. /* FW awake cookie after FW ready */
  104. #define FW_AWAKE_COOKIE (0xAA55AA55)
  105. #define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF
  106. #define MWIFIEX_SLEEP_COOKIE_SIZE 4
  107. #define MWIFIEX_MAX_DELAY_COUNT 100
  108. #define MWIFIEX_PCIE_FLR_HAPPENS 0xFEDCBABA
  109. struct mwifiex_pcie_card_reg {
  110. u16 cmd_addr_lo;
  111. u16 cmd_addr_hi;
  112. u16 fw_status;
  113. u16 cmd_size;
  114. u16 cmdrsp_addr_lo;
  115. u16 cmdrsp_addr_hi;
  116. u16 tx_rdptr;
  117. u16 tx_wrptr;
  118. u16 rx_rdptr;
  119. u16 rx_wrptr;
  120. u16 evt_rdptr;
  121. u16 evt_wrptr;
  122. u16 drv_rdy;
  123. u16 tx_start_ptr;
  124. u32 tx_mask;
  125. u32 tx_wrap_mask;
  126. u32 rx_mask;
  127. u32 rx_wrap_mask;
  128. u32 tx_rollover_ind;
  129. u32 rx_rollover_ind;
  130. u32 evt_rollover_ind;
  131. u8 ring_flag_sop;
  132. u8 ring_flag_eop;
  133. u8 ring_flag_xs_sop;
  134. u8 ring_flag_xs_eop;
  135. u32 ring_tx_start_ptr;
  136. u8 pfu_enabled;
  137. u8 sleep_cookie;
  138. u16 fw_dump_ctrl;
  139. u16 fw_dump_start;
  140. u16 fw_dump_end;
  141. u8 fw_dump_host_ready;
  142. u8 fw_dump_read_done;
  143. u8 msix_support;
  144. };
  145. static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
  146. .cmd_addr_lo = PCIE_SCRATCH_0_REG,
  147. .cmd_addr_hi = PCIE_SCRATCH_1_REG,
  148. .cmd_size = PCIE_SCRATCH_2_REG,
  149. .fw_status = PCIE_SCRATCH_3_REG,
  150. .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
  151. .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
  152. .tx_rdptr = PCIE_SCRATCH_6_REG,
  153. .tx_wrptr = PCIE_SCRATCH_7_REG,
  154. .rx_rdptr = PCIE_SCRATCH_8_REG,
  155. .rx_wrptr = PCIE_SCRATCH_9_REG,
  156. .evt_rdptr = PCIE_SCRATCH_10_REG,
  157. .evt_wrptr = PCIE_SCRATCH_11_REG,
  158. .drv_rdy = PCIE_SCRATCH_12_REG,
  159. .tx_start_ptr = 0,
  160. .tx_mask = MWIFIEX_TXBD_MASK,
  161. .tx_wrap_mask = 0,
  162. .rx_mask = MWIFIEX_RXBD_MASK,
  163. .rx_wrap_mask = 0,
  164. .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
  165. .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
  166. .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
  167. .ring_flag_sop = 0,
  168. .ring_flag_eop = 0,
  169. .ring_flag_xs_sop = 0,
  170. .ring_flag_xs_eop = 0,
  171. .ring_tx_start_ptr = 0,
  172. .pfu_enabled = 0,
  173. .sleep_cookie = 1,
  174. .msix_support = 0,
  175. };
  176. static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
  177. .cmd_addr_lo = PCIE_SCRATCH_0_REG,
  178. .cmd_addr_hi = PCIE_SCRATCH_1_REG,
  179. .cmd_size = PCIE_SCRATCH_2_REG,
  180. .fw_status = PCIE_SCRATCH_3_REG,
  181. .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
  182. .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
  183. .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
  184. .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
  185. .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
  186. .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
  187. .evt_rdptr = PCIE_SCRATCH_10_REG,
  188. .evt_wrptr = PCIE_SCRATCH_11_REG,
  189. .drv_rdy = PCIE_SCRATCH_12_REG,
  190. .tx_start_ptr = 16,
  191. .tx_mask = 0x03FF0000,
  192. .tx_wrap_mask = 0x07FF0000,
  193. .rx_mask = 0x000003FF,
  194. .rx_wrap_mask = 0x000007FF,
  195. .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
  196. .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
  197. .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
  198. .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
  199. .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
  200. .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
  201. .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
  202. .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
  203. .pfu_enabled = 1,
  204. .sleep_cookie = 0,
  205. .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
  206. .fw_dump_start = PCIE_SCRATCH_14_REG,
  207. .fw_dump_end = 0xcff,
  208. .fw_dump_host_ready = 0xee,
  209. .fw_dump_read_done = 0xfe,
  210. .msix_support = 0,
  211. };
  212. static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
  213. .cmd_addr_lo = PCIE_SCRATCH_0_REG,
  214. .cmd_addr_hi = PCIE_SCRATCH_1_REG,
  215. .cmd_size = PCIE_SCRATCH_2_REG,
  216. .fw_status = PCIE_SCRATCH_3_REG,
  217. .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
  218. .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
  219. .tx_rdptr = 0xC1A4,
  220. .tx_wrptr = 0xC174,
  221. .rx_rdptr = 0xC174,
  222. .rx_wrptr = 0xC1A4,
  223. .evt_rdptr = PCIE_SCRATCH_10_REG,
  224. .evt_wrptr = PCIE_SCRATCH_11_REG,
  225. .drv_rdy = PCIE_SCRATCH_12_REG,
  226. .tx_start_ptr = 16,
  227. .tx_mask = 0x0FFF0000,
  228. .tx_wrap_mask = 0x1FFF0000,
  229. .rx_mask = 0x00000FFF,
  230. .rx_wrap_mask = 0x00001FFF,
  231. .tx_rollover_ind = BIT(28),
  232. .rx_rollover_ind = BIT(12),
  233. .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
  234. .ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
  235. .ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
  236. .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
  237. .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
  238. .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
  239. .pfu_enabled = 1,
  240. .sleep_cookie = 0,
  241. .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
  242. .fw_dump_start = PCIE_SCRATCH_14_REG,
  243. .fw_dump_end = 0xcff,
  244. .fw_dump_host_ready = 0xcc,
  245. .fw_dump_read_done = 0xdd,
  246. .msix_support = 0,
  247. };
  248. static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
  249. {"ITCM", NULL, 0, 0xF0},
  250. {"DTCM", NULL, 0, 0xF1},
  251. {"SQRAM", NULL, 0, 0xF2},
  252. {"IRAM", NULL, 0, 0xF3},
  253. {"APU", NULL, 0, 0xF4},
  254. {"CIU", NULL, 0, 0xF5},
  255. {"ICU", NULL, 0, 0xF6},
  256. {"MAC", NULL, 0, 0xF7},
  257. };
  258. static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
  259. {"DUMP", NULL, 0, 0xDD},
  260. };
  261. struct mwifiex_pcie_device {
  262. const struct mwifiex_pcie_card_reg *reg;
  263. u16 blksz_fw_dl;
  264. u16 tx_buf_size;
  265. bool can_dump_fw;
  266. struct memory_type_mapping *mem_type_mapping_tbl;
  267. u8 num_mem_types;
  268. bool can_ext_scan;
  269. };
  270. static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
  271. .reg = &mwifiex_reg_8766,
  272. .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
  273. .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
  274. .can_dump_fw = false,
  275. .can_ext_scan = true,
  276. };
  277. static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
  278. .reg = &mwifiex_reg_8897,
  279. .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
  280. .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
  281. .can_dump_fw = true,
  282. .mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
  283. .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
  284. .can_ext_scan = true,
  285. };
  286. static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
  287. .reg = &mwifiex_reg_8997,
  288. .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
  289. .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
  290. .can_dump_fw = true,
  291. .mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
  292. .num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
  293. .can_ext_scan = true,
  294. };
  295. struct mwifiex_evt_buf_desc {
  296. u64 paddr;
  297. u16 len;
  298. u16 flags;
  299. } __packed;
  300. struct mwifiex_pcie_buf_desc {
  301. u64 paddr;
  302. u16 len;
  303. u16 flags;
  304. } __packed;
  305. struct mwifiex_pfu_buf_desc {
  306. u16 flags;
  307. u16 offset;
  308. u16 frag_len;
  309. u16 len;
  310. u64 paddr;
  311. u32 reserved;
  312. } __packed;
  313. #define MWIFIEX_NUM_MSIX_VECTORS 4
  314. struct mwifiex_msix_context {
  315. struct pci_dev *dev;
  316. u16 msg_id;
  317. };
  318. struct pcie_service_card {
  319. struct pci_dev *dev;
  320. struct mwifiex_adapter *adapter;
  321. struct mwifiex_pcie_device pcie;
  322. struct completion fw_done;
  323. u8 txbd_flush;
  324. u32 txbd_wrptr;
  325. u32 txbd_rdptr;
  326. u32 txbd_ring_size;
  327. u8 *txbd_ring_vbase;
  328. dma_addr_t txbd_ring_pbase;
  329. void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
  330. struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
  331. u32 rxbd_wrptr;
  332. u32 rxbd_rdptr;
  333. u32 rxbd_ring_size;
  334. u8 *rxbd_ring_vbase;
  335. dma_addr_t rxbd_ring_pbase;
  336. void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
  337. struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
  338. u32 evtbd_wrptr;
  339. u32 evtbd_rdptr;
  340. u32 evtbd_ring_size;
  341. u8 *evtbd_ring_vbase;
  342. dma_addr_t evtbd_ring_pbase;
  343. void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
  344. struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
  345. struct sk_buff *cmd_buf;
  346. struct sk_buff *cmdrsp_buf;
  347. u8 *sleep_cookie_vbase;
  348. dma_addr_t sleep_cookie_pbase;
  349. void __iomem *pci_mmap;
  350. void __iomem *pci_mmap1;
  351. int msi_enable;
  352. int msix_enable;
  353. #ifdef CONFIG_PCI
  354. struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
  355. #endif
  356. struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
  357. struct mwifiex_msix_context share_irq_ctx;
  358. struct work_struct work;
  359. unsigned long work_flags;
  360. };
  361. static inline int
  362. mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
  363. {
  364. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  365. switch (card->dev->device) {
  366. case PCIE_DEVICE_ID_MARVELL_88W8766P:
  367. if (((card->txbd_wrptr & reg->tx_mask) ==
  368. (rdptr & reg->tx_mask)) &&
  369. ((card->txbd_wrptr & reg->tx_rollover_ind) !=
  370. (rdptr & reg->tx_rollover_ind)))
  371. return 1;
  372. break;
  373. case PCIE_DEVICE_ID_MARVELL_88W8897:
  374. case PCIE_DEVICE_ID_MARVELL_88W8997:
  375. if (((card->txbd_wrptr & reg->tx_mask) ==
  376. (rdptr & reg->tx_mask)) &&
  377. ((card->txbd_wrptr & reg->tx_rollover_ind) ==
  378. (rdptr & reg->tx_rollover_ind)))
  379. return 1;
  380. break;
  381. }
  382. return 0;
  383. }
  384. static inline int
  385. mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
  386. {
  387. const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
  388. switch (card->dev->device) {
  389. case PCIE_DEVICE_ID_MARVELL_88W8766P:
  390. if (((card->txbd_wrptr & reg->tx_mask) !=
  391. (card->txbd_rdptr & reg->tx_mask)) ||
  392. ((card->txbd_wrptr & reg->tx_rollover_ind) !=
  393. (card->txbd_rdptr & reg->tx_rollover_ind)))
  394. return 1;
  395. break;
  396. case PCIE_DEVICE_ID_MARVELL_88W8897:
  397. case PCIE_DEVICE_ID_MARVELL_88W8997:
  398. if (((card->txbd_wrptr & reg->tx_mask) !=
  399. (card->txbd_rdptr & reg->tx_mask)) ||
  400. ((card->txbd_wrptr & reg->tx_rollover_ind) ==
  401. (card->txbd_rdptr & reg->tx_rollover_ind)))
  402. return 1;
  403. break;
  404. }
  405. return 0;
  406. }
  407. #endif /* _MWIFIEX_PCIE_H */