switchib.c 17 KB

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  1. /*
  2. * drivers/net/ethernet/mellanox/mlxsw/switchib.c
  3. * Copyright (c) 2016 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2016 Elad Raz <eladr@mellanox.com>
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the distribution.
  14. * 3. Neither the names of the copyright holders nor the names of its
  15. * contributors may be used to endorse or promote products derived from
  16. * this software without specific prior written permission.
  17. *
  18. * Alternatively, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") version 2 as published by the Free
  20. * Software Foundation.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32. * POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/module.h>
  36. #include <linux/types.h>
  37. #include <linux/pci.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/slab.h>
  41. #include <linux/device.h>
  42. #include <linux/skbuff.h>
  43. #include <linux/if_vlan.h>
  44. #include <net/switchdev.h>
  45. #include "pci.h"
  46. #include "core.h"
  47. #include "reg.h"
  48. #include "port.h"
  49. #include "trap.h"
  50. #include "txheader.h"
  51. #include "ib.h"
  52. static const char mlxsw_sib_driver_name[] = "mlxsw_switchib";
  53. static const char mlxsw_sib2_driver_name[] = "mlxsw_switchib2";
  54. struct mlxsw_sib_port;
  55. struct mlxsw_sib {
  56. struct mlxsw_sib_port **ports;
  57. struct mlxsw_core *core;
  58. const struct mlxsw_bus_info *bus_info;
  59. };
  60. struct mlxsw_sib_port {
  61. struct mlxsw_sib *mlxsw_sib;
  62. u8 local_port;
  63. struct {
  64. u8 module;
  65. } mapping;
  66. };
  67. /* tx_v1_hdr_version
  68. * Tx header version.
  69. * Must be set to 1.
  70. */
  71. MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4);
  72. /* tx_v1_hdr_ctl
  73. * Packet control type.
  74. * 0 - Ethernet control (e.g. EMADs, LACP)
  75. * 1 - Ethernet data
  76. */
  77. MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2);
  78. /* tx_v1_hdr_proto
  79. * Packet protocol type. Must be set to 1 (Ethernet).
  80. */
  81. MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3);
  82. /* tx_v1_hdr_swid
  83. * Switch partition ID. Must be set to 0.
  84. */
  85. MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3);
  86. /* tx_v1_hdr_control_tclass
  87. * Indicates if the packet should use the control TClass and not one
  88. * of the data TClasses.
  89. */
  90. MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1);
  91. /* tx_v1_hdr_port_mid
  92. * Destination local port for unicast packets.
  93. * Destination multicast ID for multicast packets.
  94. *
  95. * Control packets are directed to a specific egress port, while data
  96. * packets are transmitted through the CPU port (0) into the switch partition,
  97. * where forwarding rules are applied.
  98. */
  99. MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16);
  100. /* tx_v1_hdr_type
  101. * 0 - Data packets
  102. * 6 - Control packets
  103. */
  104. MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4);
  105. static void
  106. mlxsw_sib_tx_v1_hdr_construct(struct sk_buff *skb,
  107. const struct mlxsw_tx_info *tx_info)
  108. {
  109. char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
  110. memset(txhdr, 0, MLXSW_TXHDR_LEN);
  111. mlxsw_tx_v1_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
  112. mlxsw_tx_v1_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
  113. mlxsw_tx_v1_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
  114. mlxsw_tx_v1_hdr_swid_set(txhdr, 0);
  115. mlxsw_tx_v1_hdr_control_tclass_set(txhdr, 1);
  116. mlxsw_tx_v1_hdr_port_mid_set(txhdr, tx_info->local_port);
  117. mlxsw_tx_v1_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
  118. }
  119. static int
  120. mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port *mlxsw_sib_port,
  121. bool is_up)
  122. {
  123. struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
  124. char paos_pl[MLXSW_REG_PAOS_LEN];
  125. mlxsw_reg_paos_pack(paos_pl, mlxsw_sib_port->local_port,
  126. is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
  127. MLXSW_PORT_ADMIN_STATUS_DOWN);
  128. return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(paos), paos_pl);
  129. }
  130. static int mlxsw_sib_port_mtu_set(struct mlxsw_sib_port *mlxsw_sib_port,
  131. u16 mtu)
  132. {
  133. struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
  134. char pmtu_pl[MLXSW_REG_PMTU_LEN];
  135. int max_mtu;
  136. int err;
  137. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, 0);
  138. err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
  139. if (err)
  140. return err;
  141. max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
  142. if (mtu > max_mtu)
  143. return -EINVAL;
  144. mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, mtu);
  145. return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
  146. }
  147. static int mlxsw_sib_port_set(struct mlxsw_sib_port *mlxsw_sib_port, u8 port)
  148. {
  149. struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
  150. char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
  151. int err;
  152. mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sib_port->local_port);
  153. mlxsw_reg_plib_ib_port_set(plib_pl, port);
  154. err = mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(plib), plib_pl);
  155. return err;
  156. }
  157. static int mlxsw_sib_port_swid_set(struct mlxsw_sib_port *mlxsw_sib_port,
  158. u8 swid)
  159. {
  160. struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
  161. char pspa_pl[MLXSW_REG_PSPA_LEN];
  162. mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sib_port->local_port);
  163. return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pspa), pspa_pl);
  164. }
  165. static int mlxsw_sib_port_module_info_get(struct mlxsw_sib *mlxsw_sib,
  166. u8 local_port, u8 *p_module,
  167. u8 *p_width)
  168. {
  169. char pmlp_pl[MLXSW_REG_PMLP_LEN];
  170. int err;
  171. mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
  172. err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmlp), pmlp_pl);
  173. if (err)
  174. return err;
  175. *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
  176. *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
  177. return 0;
  178. }
  179. static int mlxsw_sib_port_speed_set(struct mlxsw_sib_port *mlxsw_sib_port,
  180. u16 speed, u16 width)
  181. {
  182. struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
  183. char ptys_pl[MLXSW_REG_PTYS_LEN];
  184. mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sib_port->local_port, speed,
  185. width);
  186. return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(ptys), ptys_pl);
  187. }
  188. static bool mlxsw_sib_port_created(struct mlxsw_sib *mlxsw_sib, u8 local_port)
  189. {
  190. return mlxsw_sib->ports[local_port] != NULL;
  191. }
  192. static int __mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
  193. u8 module, u8 width)
  194. {
  195. struct mlxsw_sib_port *mlxsw_sib_port;
  196. int err;
  197. mlxsw_sib_port = kzalloc(sizeof(*mlxsw_sib_port), GFP_KERNEL);
  198. if (!mlxsw_sib_port)
  199. return -ENOMEM;
  200. mlxsw_sib_port->mlxsw_sib = mlxsw_sib;
  201. mlxsw_sib_port->local_port = local_port;
  202. mlxsw_sib_port->mapping.module = module;
  203. err = mlxsw_sib_port_swid_set(mlxsw_sib_port, 0);
  204. if (err) {
  205. dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set SWID\n",
  206. mlxsw_sib_port->local_port);
  207. goto err_port_swid_set;
  208. }
  209. /* Expose the IB port number as it's front panel name */
  210. err = mlxsw_sib_port_set(mlxsw_sib_port, module + 1);
  211. if (err) {
  212. dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set IB port\n",
  213. mlxsw_sib_port->local_port);
  214. goto err_port_ib_set;
  215. }
  216. /* Supports all speeds from SDR to FDR (bitmask) and support bus width
  217. * of 1x, 2x and 4x (3 bits bitmask)
  218. */
  219. err = mlxsw_sib_port_speed_set(mlxsw_sib_port,
  220. MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
  221. BIT(3) - 1);
  222. if (err) {
  223. dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set speed\n",
  224. mlxsw_sib_port->local_port);
  225. goto err_port_speed_set;
  226. }
  227. /* Change to the maximum MTU the device supports, the SMA will take
  228. * care of the active MTU
  229. */
  230. err = mlxsw_sib_port_mtu_set(mlxsw_sib_port, MLXSW_IB_DEFAULT_MTU);
  231. if (err) {
  232. dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set MTU\n",
  233. mlxsw_sib_port->local_port);
  234. goto err_port_mtu_set;
  235. }
  236. err = mlxsw_sib_port_admin_status_set(mlxsw_sib_port, true);
  237. if (err) {
  238. dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
  239. mlxsw_sib_port->local_port);
  240. goto err_port_admin_set;
  241. }
  242. mlxsw_core_port_ib_set(mlxsw_sib->core, mlxsw_sib_port->local_port,
  243. mlxsw_sib_port);
  244. mlxsw_sib->ports[local_port] = mlxsw_sib_port;
  245. return 0;
  246. err_port_admin_set:
  247. err_port_mtu_set:
  248. err_port_speed_set:
  249. err_port_ib_set:
  250. mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
  251. err_port_swid_set:
  252. kfree(mlxsw_sib_port);
  253. return err;
  254. }
  255. static int mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
  256. u8 module, u8 width)
  257. {
  258. int err;
  259. err = mlxsw_core_port_init(mlxsw_sib->core, local_port);
  260. if (err) {
  261. dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to init core port\n",
  262. local_port);
  263. return err;
  264. }
  265. err = __mlxsw_sib_port_create(mlxsw_sib, local_port, module, width);
  266. if (err)
  267. goto err_port_create;
  268. return 0;
  269. err_port_create:
  270. mlxsw_core_port_fini(mlxsw_sib->core, local_port);
  271. return err;
  272. }
  273. static void __mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
  274. {
  275. struct mlxsw_sib_port *mlxsw_sib_port = mlxsw_sib->ports[local_port];
  276. mlxsw_core_port_clear(mlxsw_sib->core, local_port, mlxsw_sib);
  277. mlxsw_sib->ports[local_port] = NULL;
  278. mlxsw_sib_port_admin_status_set(mlxsw_sib_port, false);
  279. mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
  280. kfree(mlxsw_sib_port);
  281. }
  282. static void mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
  283. {
  284. __mlxsw_sib_port_remove(mlxsw_sib, local_port);
  285. mlxsw_core_port_fini(mlxsw_sib->core, local_port);
  286. }
  287. static void mlxsw_sib_ports_remove(struct mlxsw_sib *mlxsw_sib)
  288. {
  289. int i;
  290. for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++)
  291. if (mlxsw_sib_port_created(mlxsw_sib, i))
  292. mlxsw_sib_port_remove(mlxsw_sib, i);
  293. kfree(mlxsw_sib->ports);
  294. }
  295. static int mlxsw_sib_ports_create(struct mlxsw_sib *mlxsw_sib)
  296. {
  297. size_t alloc_size;
  298. u8 module, width;
  299. int i;
  300. int err;
  301. alloc_size = sizeof(struct mlxsw_sib_port *) * MLXSW_PORT_MAX_IB_PORTS;
  302. mlxsw_sib->ports = kzalloc(alloc_size, GFP_KERNEL);
  303. if (!mlxsw_sib->ports)
  304. return -ENOMEM;
  305. for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) {
  306. err = mlxsw_sib_port_module_info_get(mlxsw_sib, i, &module,
  307. &width);
  308. if (err)
  309. goto err_port_module_info_get;
  310. if (!width)
  311. continue;
  312. err = mlxsw_sib_port_create(mlxsw_sib, i, module, width);
  313. if (err)
  314. goto err_port_create;
  315. }
  316. return 0;
  317. err_port_create:
  318. err_port_module_info_get:
  319. for (i--; i >= 1; i--)
  320. if (mlxsw_sib_port_created(mlxsw_sib, i))
  321. mlxsw_sib_port_remove(mlxsw_sib, i);
  322. kfree(mlxsw_sib->ports);
  323. return err;
  324. }
  325. static void
  326. mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port *mlxsw_sib_port,
  327. enum mlxsw_reg_pude_oper_status status)
  328. {
  329. if (status == MLXSW_PORT_OPER_STATUS_UP)
  330. pr_info("ib link for port %d - up\n",
  331. mlxsw_sib_port->mapping.module + 1);
  332. else
  333. pr_info("ib link for port %d - down\n",
  334. mlxsw_sib_port->mapping.module + 1);
  335. }
  336. static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg,
  337. char *pude_pl, void *priv)
  338. {
  339. struct mlxsw_sib *mlxsw_sib = priv;
  340. struct mlxsw_sib_port *mlxsw_sib_port;
  341. enum mlxsw_reg_pude_oper_status status;
  342. u8 local_port;
  343. local_port = mlxsw_reg_pude_local_port_get(pude_pl);
  344. mlxsw_sib_port = mlxsw_sib->ports[local_port];
  345. if (!mlxsw_sib_port) {
  346. dev_warn(mlxsw_sib->bus_info->dev, "Port %d: Link event received for non-existent port\n",
  347. local_port);
  348. return;
  349. }
  350. status = mlxsw_reg_pude_oper_status_get(pude_pl);
  351. mlxsw_sib_pude_ib_event_func(mlxsw_sib_port, status);
  352. }
  353. static const struct mlxsw_listener mlxsw_sib_listener[] = {
  354. MLXSW_EVENTL(mlxsw_sib_pude_event_func, PUDE, EMAD),
  355. };
  356. static int mlxsw_sib_taps_init(struct mlxsw_sib *mlxsw_sib)
  357. {
  358. int i;
  359. int err;
  360. for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
  361. err = mlxsw_core_trap_register(mlxsw_sib->core,
  362. &mlxsw_sib_listener[i],
  363. mlxsw_sib);
  364. if (err)
  365. goto err_rx_listener_register;
  366. }
  367. return 0;
  368. err_rx_listener_register:
  369. for (i--; i >= 0; i--) {
  370. mlxsw_core_trap_unregister(mlxsw_sib->core,
  371. &mlxsw_sib_listener[i],
  372. mlxsw_sib);
  373. }
  374. return err;
  375. }
  376. static void mlxsw_sib_traps_fini(struct mlxsw_sib *mlxsw_sib)
  377. {
  378. int i;
  379. for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
  380. mlxsw_core_trap_unregister(mlxsw_sib->core,
  381. &mlxsw_sib_listener[i], mlxsw_sib);
  382. }
  383. }
  384. static int mlxsw_sib_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
  385. {
  386. char htgt_pl[MLXSW_REG_HTGT_LEN];
  387. mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
  388. MLXSW_REG_HTGT_INVALID_POLICER,
  389. MLXSW_REG_HTGT_DEFAULT_PRIORITY,
  390. MLXSW_REG_HTGT_DEFAULT_TC);
  391. mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
  392. mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
  393. MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD);
  394. return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
  395. }
  396. static int mlxsw_sib_init(struct mlxsw_core *mlxsw_core,
  397. const struct mlxsw_bus_info *mlxsw_bus_info)
  398. {
  399. struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
  400. int err;
  401. mlxsw_sib->core = mlxsw_core;
  402. mlxsw_sib->bus_info = mlxsw_bus_info;
  403. err = mlxsw_sib_ports_create(mlxsw_sib);
  404. if (err) {
  405. dev_err(mlxsw_sib->bus_info->dev, "Failed to create ports\n");
  406. return err;
  407. }
  408. err = mlxsw_sib_taps_init(mlxsw_sib);
  409. if (err) {
  410. dev_err(mlxsw_sib->bus_info->dev, "Failed to set traps\n");
  411. goto err_traps_init_err;
  412. }
  413. return 0;
  414. err_traps_init_err:
  415. mlxsw_sib_ports_remove(mlxsw_sib);
  416. return err;
  417. }
  418. static void mlxsw_sib_fini(struct mlxsw_core *mlxsw_core)
  419. {
  420. struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
  421. mlxsw_sib_traps_fini(mlxsw_sib);
  422. mlxsw_sib_ports_remove(mlxsw_sib);
  423. }
  424. static struct mlxsw_config_profile mlxsw_sib_config_profile = {
  425. .used_max_system_port = 1,
  426. .max_system_port = 48000,
  427. .used_max_ib_mc = 1,
  428. .max_ib_mc = 27,
  429. .used_max_pkey = 1,
  430. .max_pkey = 32,
  431. .swid_config = {
  432. {
  433. .used_type = 1,
  434. .type = MLXSW_PORT_SWID_TYPE_IB,
  435. }
  436. },
  437. .resource_query_enable = 0,
  438. };
  439. static struct mlxsw_driver mlxsw_sib_driver = {
  440. .kind = mlxsw_sib_driver_name,
  441. .priv_size = sizeof(struct mlxsw_sib),
  442. .init = mlxsw_sib_init,
  443. .fini = mlxsw_sib_fini,
  444. .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
  445. .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
  446. .txhdr_len = MLXSW_TXHDR_LEN,
  447. .profile = &mlxsw_sib_config_profile,
  448. };
  449. static struct mlxsw_driver mlxsw_sib2_driver = {
  450. .kind = mlxsw_sib2_driver_name,
  451. .priv_size = sizeof(struct mlxsw_sib),
  452. .init = mlxsw_sib_init,
  453. .fini = mlxsw_sib_fini,
  454. .basic_trap_groups_set = mlxsw_sib_basic_trap_groups_set,
  455. .txhdr_construct = mlxsw_sib_tx_v1_hdr_construct,
  456. .txhdr_len = MLXSW_TXHDR_LEN,
  457. .profile = &mlxsw_sib_config_profile,
  458. };
  459. static const struct pci_device_id mlxsw_sib_pci_id_table[] = {
  460. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB), 0},
  461. {0, },
  462. };
  463. static struct pci_driver mlxsw_sib_pci_driver = {
  464. .name = mlxsw_sib_driver_name,
  465. .id_table = mlxsw_sib_pci_id_table,
  466. };
  467. static const struct pci_device_id mlxsw_sib2_pci_id_table[] = {
  468. {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB2), 0},
  469. {0, },
  470. };
  471. static struct pci_driver mlxsw_sib2_pci_driver = {
  472. .name = mlxsw_sib2_driver_name,
  473. .id_table = mlxsw_sib2_pci_id_table,
  474. };
  475. static int __init mlxsw_sib_module_init(void)
  476. {
  477. int err;
  478. err = mlxsw_core_driver_register(&mlxsw_sib_driver);
  479. if (err)
  480. return err;
  481. err = mlxsw_core_driver_register(&mlxsw_sib2_driver);
  482. if (err)
  483. goto err_sib2_driver_register;
  484. err = mlxsw_pci_driver_register(&mlxsw_sib_pci_driver);
  485. if (err)
  486. goto err_sib_pci_driver_register;
  487. err = mlxsw_pci_driver_register(&mlxsw_sib2_pci_driver);
  488. if (err)
  489. goto err_sib2_pci_driver_register;
  490. return 0;
  491. err_sib2_pci_driver_register:
  492. mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
  493. err_sib_pci_driver_register:
  494. mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
  495. err_sib2_driver_register:
  496. mlxsw_core_driver_unregister(&mlxsw_sib_driver);
  497. return err;
  498. }
  499. static void __exit mlxsw_sib_module_exit(void)
  500. {
  501. mlxsw_pci_driver_unregister(&mlxsw_sib2_pci_driver);
  502. mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
  503. mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
  504. mlxsw_core_driver_unregister(&mlxsw_sib_driver);
  505. }
  506. module_init(mlxsw_sib_module_init);
  507. module_exit(mlxsw_sib_module_exit);
  508. MODULE_LICENSE("Dual BSD/GPL");
  509. MODULE_AUTHOR("Elad Raz <eladr@@mellanox.com>");
  510. MODULE_DESCRIPTION("Mellanox SwitchIB and SwitchIB-2 driver");
  511. MODULE_ALIAS("mlxsw_switchib2");
  512. MODULE_DEVICE_TABLE(pci, mlxsw_sib_pci_id_table);
  513. MODULE_DEVICE_TABLE(pci, mlxsw_sib2_pci_id_table);