spectrum_buffers.c 28 KB

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  1. /*
  2. * drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c
  3. * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright
  12. * notice, this list of conditions and the following disclaimer in the
  13. * documentation and/or other materials provided with the distribution.
  14. * 3. Neither the names of the copyright holders nor the names of its
  15. * contributors may be used to endorse or promote products derived from
  16. * this software without specific prior written permission.
  17. *
  18. * Alternatively, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") version 2 as published by the Free
  20. * Software Foundation.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  26. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  29. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  30. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  31. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32. * POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/types.h>
  36. #include <linux/dcbnl.h>
  37. #include <linux/if_ether.h>
  38. #include <linux/list.h>
  39. #include "spectrum.h"
  40. #include "core.h"
  41. #include "port.h"
  42. #include "reg.h"
  43. static struct mlxsw_sp_sb_pr *mlxsw_sp_sb_pr_get(struct mlxsw_sp *mlxsw_sp,
  44. u8 pool,
  45. enum mlxsw_reg_sbxx_dir dir)
  46. {
  47. return &mlxsw_sp->sb.prs[dir][pool];
  48. }
  49. static struct mlxsw_sp_sb_cm *mlxsw_sp_sb_cm_get(struct mlxsw_sp *mlxsw_sp,
  50. u8 local_port, u8 pg_buff,
  51. enum mlxsw_reg_sbxx_dir dir)
  52. {
  53. return &mlxsw_sp->sb.ports[local_port].cms[dir][pg_buff];
  54. }
  55. static struct mlxsw_sp_sb_pm *mlxsw_sp_sb_pm_get(struct mlxsw_sp *mlxsw_sp,
  56. u8 local_port, u8 pool,
  57. enum mlxsw_reg_sbxx_dir dir)
  58. {
  59. return &mlxsw_sp->sb.ports[local_port].pms[dir][pool];
  60. }
  61. static int mlxsw_sp_sb_pr_write(struct mlxsw_sp *mlxsw_sp, u8 pool,
  62. enum mlxsw_reg_sbxx_dir dir,
  63. enum mlxsw_reg_sbpr_mode mode, u32 size)
  64. {
  65. char sbpr_pl[MLXSW_REG_SBPR_LEN];
  66. struct mlxsw_sp_sb_pr *pr;
  67. int err;
  68. mlxsw_reg_sbpr_pack(sbpr_pl, pool, dir, mode, size);
  69. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpr), sbpr_pl);
  70. if (err)
  71. return err;
  72. pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
  73. pr->mode = mode;
  74. pr->size = size;
  75. return 0;
  76. }
  77. static int mlxsw_sp_sb_cm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  78. u8 pg_buff, enum mlxsw_reg_sbxx_dir dir,
  79. u32 min_buff, u32 max_buff, u8 pool)
  80. {
  81. char sbcm_pl[MLXSW_REG_SBCM_LEN];
  82. int err;
  83. mlxsw_reg_sbcm_pack(sbcm_pl, local_port, pg_buff, dir,
  84. min_buff, max_buff, pool);
  85. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbcm), sbcm_pl);
  86. if (err)
  87. return err;
  88. if (pg_buff < MLXSW_SP_SB_TC_COUNT) {
  89. struct mlxsw_sp_sb_cm *cm;
  90. cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, pg_buff, dir);
  91. cm->min_buff = min_buff;
  92. cm->max_buff = max_buff;
  93. cm->pool = pool;
  94. }
  95. return 0;
  96. }
  97. static int mlxsw_sp_sb_pm_write(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  98. u8 pool, enum mlxsw_reg_sbxx_dir dir,
  99. u32 min_buff, u32 max_buff)
  100. {
  101. char sbpm_pl[MLXSW_REG_SBPM_LEN];
  102. struct mlxsw_sp_sb_pm *pm;
  103. int err;
  104. mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, false,
  105. min_buff, max_buff);
  106. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl);
  107. if (err)
  108. return err;
  109. pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool, dir);
  110. pm->min_buff = min_buff;
  111. pm->max_buff = max_buff;
  112. return 0;
  113. }
  114. static int mlxsw_sp_sb_pm_occ_clear(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  115. u8 pool, enum mlxsw_reg_sbxx_dir dir,
  116. struct list_head *bulk_list)
  117. {
  118. char sbpm_pl[MLXSW_REG_SBPM_LEN];
  119. mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, true, 0, 0);
  120. return mlxsw_reg_trans_query(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl,
  121. bulk_list, NULL, 0);
  122. }
  123. static void mlxsw_sp_sb_pm_occ_query_cb(struct mlxsw_core *mlxsw_core,
  124. char *sbpm_pl, size_t sbpm_pl_len,
  125. unsigned long cb_priv)
  126. {
  127. struct mlxsw_sp_sb_pm *pm = (struct mlxsw_sp_sb_pm *) cb_priv;
  128. mlxsw_reg_sbpm_unpack(sbpm_pl, &pm->occ.cur, &pm->occ.max);
  129. }
  130. static int mlxsw_sp_sb_pm_occ_query(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  131. u8 pool, enum mlxsw_reg_sbxx_dir dir,
  132. struct list_head *bulk_list)
  133. {
  134. char sbpm_pl[MLXSW_REG_SBPM_LEN];
  135. struct mlxsw_sp_sb_pm *pm;
  136. pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port, pool, dir);
  137. mlxsw_reg_sbpm_pack(sbpm_pl, local_port, pool, dir, false, 0, 0);
  138. return mlxsw_reg_trans_query(mlxsw_sp->core, MLXSW_REG(sbpm), sbpm_pl,
  139. bulk_list,
  140. mlxsw_sp_sb_pm_occ_query_cb,
  141. (unsigned long) pm);
  142. }
  143. static const u16 mlxsw_sp_pbs[] = {
  144. [0] = 2 * ETH_FRAME_LEN,
  145. [9] = 2 * MLXSW_PORT_MAX_MTU,
  146. };
  147. #define MLXSW_SP_PBS_LEN ARRAY_SIZE(mlxsw_sp_pbs)
  148. #define MLXSW_SP_PB_UNUSED 8
  149. static int mlxsw_sp_port_pb_init(struct mlxsw_sp_port *mlxsw_sp_port)
  150. {
  151. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  152. char pbmc_pl[MLXSW_REG_PBMC_LEN];
  153. int i;
  154. mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port,
  155. 0xffff, 0xffff / 2);
  156. for (i = 0; i < MLXSW_SP_PBS_LEN; i++) {
  157. u16 size = mlxsw_sp_bytes_cells(mlxsw_sp, mlxsw_sp_pbs[i]);
  158. if (i == MLXSW_SP_PB_UNUSED)
  159. continue;
  160. mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, i, size);
  161. }
  162. mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl,
  163. MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX, 0);
  164. return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
  165. }
  166. static int mlxsw_sp_port_pb_prio_init(struct mlxsw_sp_port *mlxsw_sp_port)
  167. {
  168. char pptb_pl[MLXSW_REG_PPTB_LEN];
  169. int i;
  170. mlxsw_reg_pptb_pack(pptb_pl, mlxsw_sp_port->local_port);
  171. for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
  172. mlxsw_reg_pptb_prio_to_buff_pack(pptb_pl, i, 0);
  173. return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pptb),
  174. pptb_pl);
  175. }
  176. static int mlxsw_sp_port_headroom_init(struct mlxsw_sp_port *mlxsw_sp_port)
  177. {
  178. int err;
  179. err = mlxsw_sp_port_pb_init(mlxsw_sp_port);
  180. if (err)
  181. return err;
  182. return mlxsw_sp_port_pb_prio_init(mlxsw_sp_port);
  183. }
  184. static int mlxsw_sp_sb_ports_init(struct mlxsw_sp *mlxsw_sp)
  185. {
  186. unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
  187. mlxsw_sp->sb.ports = kcalloc(max_ports, sizeof(struct mlxsw_sp_sb_port),
  188. GFP_KERNEL);
  189. if (!mlxsw_sp->sb.ports)
  190. return -ENOMEM;
  191. return 0;
  192. }
  193. static void mlxsw_sp_sb_ports_fini(struct mlxsw_sp *mlxsw_sp)
  194. {
  195. kfree(mlxsw_sp->sb.ports);
  196. }
  197. #define MLXSW_SP_SB_PR_INGRESS_SIZE 12440000
  198. #define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
  199. #define MLXSW_SP_SB_PR_EGRESS_SIZE 13232000
  200. #define MLXSW_SP_SB_PR(_mode, _size) \
  201. { \
  202. .mode = _mode, \
  203. .size = _size, \
  204. }
  205. static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_ingress[] = {
  206. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
  207. MLXSW_SP_SB_PR_INGRESS_SIZE),
  208. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
  209. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
  210. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
  211. MLXSW_SP_SB_PR_INGRESS_MNG_SIZE),
  212. };
  213. #define MLXSW_SP_SB_PRS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_ingress)
  214. static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs_egress[] = {
  215. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, MLXSW_SP_SB_PR_EGRESS_SIZE),
  216. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
  217. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
  218. MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
  219. };
  220. #define MLXSW_SP_SB_PRS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_prs_egress)
  221. static int __mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
  222. enum mlxsw_reg_sbxx_dir dir,
  223. const struct mlxsw_sp_sb_pr *prs,
  224. size_t prs_len)
  225. {
  226. int i;
  227. int err;
  228. for (i = 0; i < prs_len; i++) {
  229. u32 size = mlxsw_sp_bytes_cells(mlxsw_sp, prs[i].size);
  230. err = mlxsw_sp_sb_pr_write(mlxsw_sp, i, dir, prs[i].mode, size);
  231. if (err)
  232. return err;
  233. }
  234. return 0;
  235. }
  236. static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp)
  237. {
  238. int err;
  239. err = __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_INGRESS,
  240. mlxsw_sp_sb_prs_ingress,
  241. MLXSW_SP_SB_PRS_INGRESS_LEN);
  242. if (err)
  243. return err;
  244. return __mlxsw_sp_sb_prs_init(mlxsw_sp, MLXSW_REG_SBXX_DIR_EGRESS,
  245. mlxsw_sp_sb_prs_egress,
  246. MLXSW_SP_SB_PRS_EGRESS_LEN);
  247. }
  248. #define MLXSW_SP_SB_CM(_min_buff, _max_buff, _pool) \
  249. { \
  250. .min_buff = _min_buff, \
  251. .max_buff = _max_buff, \
  252. .pool = _pool, \
  253. }
  254. static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
  255. MLXSW_SP_SB_CM(10000, 8, 0),
  256. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  257. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  258. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  259. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  260. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  261. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  262. MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
  263. MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
  264. MLXSW_SP_SB_CM(20000, 1, 3),
  265. };
  266. #define MLXSW_SP_SB_CMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_ingress)
  267. static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
  268. MLXSW_SP_SB_CM(1500, 9, 0),
  269. MLXSW_SP_SB_CM(1500, 9, 0),
  270. MLXSW_SP_SB_CM(1500, 9, 0),
  271. MLXSW_SP_SB_CM(1500, 9, 0),
  272. MLXSW_SP_SB_CM(1500, 9, 0),
  273. MLXSW_SP_SB_CM(1500, 9, 0),
  274. MLXSW_SP_SB_CM(1500, 9, 0),
  275. MLXSW_SP_SB_CM(1500, 9, 0),
  276. MLXSW_SP_SB_CM(0, 0, 0),
  277. MLXSW_SP_SB_CM(0, 0, 0),
  278. MLXSW_SP_SB_CM(0, 0, 0),
  279. MLXSW_SP_SB_CM(0, 0, 0),
  280. MLXSW_SP_SB_CM(0, 0, 0),
  281. MLXSW_SP_SB_CM(0, 0, 0),
  282. MLXSW_SP_SB_CM(0, 0, 0),
  283. MLXSW_SP_SB_CM(0, 0, 0),
  284. MLXSW_SP_SB_CM(1, 0xff, 0),
  285. };
  286. #define MLXSW_SP_SB_CMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_cms_egress)
  287. #define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 0)
  288. static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
  289. MLXSW_SP_CPU_PORT_SB_CM,
  290. MLXSW_SP_CPU_PORT_SB_CM,
  291. MLXSW_SP_CPU_PORT_SB_CM,
  292. MLXSW_SP_CPU_PORT_SB_CM,
  293. MLXSW_SP_CPU_PORT_SB_CM,
  294. MLXSW_SP_CPU_PORT_SB_CM,
  295. MLXSW_SP_CPU_PORT_SB_CM,
  296. MLXSW_SP_SB_CM(10000, 0, 0),
  297. MLXSW_SP_CPU_PORT_SB_CM,
  298. MLXSW_SP_CPU_PORT_SB_CM,
  299. MLXSW_SP_CPU_PORT_SB_CM,
  300. MLXSW_SP_CPU_PORT_SB_CM,
  301. MLXSW_SP_CPU_PORT_SB_CM,
  302. MLXSW_SP_CPU_PORT_SB_CM,
  303. MLXSW_SP_CPU_PORT_SB_CM,
  304. MLXSW_SP_CPU_PORT_SB_CM,
  305. MLXSW_SP_CPU_PORT_SB_CM,
  306. MLXSW_SP_CPU_PORT_SB_CM,
  307. MLXSW_SP_CPU_PORT_SB_CM,
  308. MLXSW_SP_CPU_PORT_SB_CM,
  309. MLXSW_SP_CPU_PORT_SB_CM,
  310. MLXSW_SP_CPU_PORT_SB_CM,
  311. MLXSW_SP_CPU_PORT_SB_CM,
  312. MLXSW_SP_CPU_PORT_SB_CM,
  313. MLXSW_SP_CPU_PORT_SB_CM,
  314. MLXSW_SP_CPU_PORT_SB_CM,
  315. MLXSW_SP_CPU_PORT_SB_CM,
  316. MLXSW_SP_CPU_PORT_SB_CM,
  317. MLXSW_SP_CPU_PORT_SB_CM,
  318. MLXSW_SP_CPU_PORT_SB_CM,
  319. MLXSW_SP_CPU_PORT_SB_CM,
  320. MLXSW_SP_CPU_PORT_SB_CM,
  321. };
  322. #define MLXSW_SP_CPU_PORT_SB_MCS_LEN \
  323. ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms)
  324. static int __mlxsw_sp_sb_cms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  325. enum mlxsw_reg_sbxx_dir dir,
  326. const struct mlxsw_sp_sb_cm *cms,
  327. size_t cms_len)
  328. {
  329. int i;
  330. int err;
  331. for (i = 0; i < cms_len; i++) {
  332. const struct mlxsw_sp_sb_cm *cm;
  333. u32 min_buff;
  334. if (i == 8 && dir == MLXSW_REG_SBXX_DIR_INGRESS)
  335. continue; /* PG number 8 does not exist, skip it */
  336. cm = &cms[i];
  337. /* All pools are initialized using dynamic thresholds,
  338. * therefore 'max_buff' isn't specified in cells.
  339. */
  340. min_buff = mlxsw_sp_bytes_cells(mlxsw_sp, cm->min_buff);
  341. err = mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, i, dir,
  342. min_buff, cm->max_buff, cm->pool);
  343. if (err)
  344. return err;
  345. }
  346. return 0;
  347. }
  348. static int mlxsw_sp_port_sb_cms_init(struct mlxsw_sp_port *mlxsw_sp_port)
  349. {
  350. int err;
  351. err = __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
  352. mlxsw_sp_port->local_port,
  353. MLXSW_REG_SBXX_DIR_INGRESS,
  354. mlxsw_sp_sb_cms_ingress,
  355. MLXSW_SP_SB_CMS_INGRESS_LEN);
  356. if (err)
  357. return err;
  358. return __mlxsw_sp_sb_cms_init(mlxsw_sp_port->mlxsw_sp,
  359. mlxsw_sp_port->local_port,
  360. MLXSW_REG_SBXX_DIR_EGRESS,
  361. mlxsw_sp_sb_cms_egress,
  362. MLXSW_SP_SB_CMS_EGRESS_LEN);
  363. }
  364. static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
  365. {
  366. return __mlxsw_sp_sb_cms_init(mlxsw_sp, 0, MLXSW_REG_SBXX_DIR_EGRESS,
  367. mlxsw_sp_cpu_port_sb_cms,
  368. MLXSW_SP_CPU_PORT_SB_MCS_LEN);
  369. }
  370. #define MLXSW_SP_SB_PM(_min_buff, _max_buff) \
  371. { \
  372. .min_buff = _min_buff, \
  373. .max_buff = _max_buff, \
  374. }
  375. static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_ingress[] = {
  376. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
  377. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
  378. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
  379. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
  380. };
  381. #define MLXSW_SP_SB_PMS_INGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_ingress)
  382. static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms_egress[] = {
  383. MLXSW_SP_SB_PM(0, 7),
  384. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
  385. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
  386. MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
  387. };
  388. #define MLXSW_SP_SB_PMS_EGRESS_LEN ARRAY_SIZE(mlxsw_sp_sb_pms_egress)
  389. static int __mlxsw_sp_port_sb_pms_init(struct mlxsw_sp *mlxsw_sp, u8 local_port,
  390. enum mlxsw_reg_sbxx_dir dir,
  391. const struct mlxsw_sp_sb_pm *pms,
  392. size_t pms_len)
  393. {
  394. int i;
  395. int err;
  396. for (i = 0; i < pms_len; i++) {
  397. const struct mlxsw_sp_sb_pm *pm;
  398. pm = &pms[i];
  399. err = mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, i, dir,
  400. pm->min_buff, pm->max_buff);
  401. if (err)
  402. return err;
  403. }
  404. return 0;
  405. }
  406. static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
  407. {
  408. int err;
  409. err = __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
  410. mlxsw_sp_port->local_port,
  411. MLXSW_REG_SBXX_DIR_INGRESS,
  412. mlxsw_sp_sb_pms_ingress,
  413. MLXSW_SP_SB_PMS_INGRESS_LEN);
  414. if (err)
  415. return err;
  416. return __mlxsw_sp_port_sb_pms_init(mlxsw_sp_port->mlxsw_sp,
  417. mlxsw_sp_port->local_port,
  418. MLXSW_REG_SBXX_DIR_EGRESS,
  419. mlxsw_sp_sb_pms_egress,
  420. MLXSW_SP_SB_PMS_EGRESS_LEN);
  421. }
  422. struct mlxsw_sp_sb_mm {
  423. u32 min_buff;
  424. u32 max_buff;
  425. u8 pool;
  426. };
  427. #define MLXSW_SP_SB_MM(_min_buff, _max_buff, _pool) \
  428. { \
  429. .min_buff = _min_buff, \
  430. .max_buff = _max_buff, \
  431. .pool = _pool, \
  432. }
  433. static const struct mlxsw_sp_sb_mm mlxsw_sp_sb_mms[] = {
  434. MLXSW_SP_SB_MM(20000, 0xff, 0),
  435. MLXSW_SP_SB_MM(20000, 0xff, 0),
  436. MLXSW_SP_SB_MM(20000, 0xff, 0),
  437. MLXSW_SP_SB_MM(20000, 0xff, 0),
  438. MLXSW_SP_SB_MM(20000, 0xff, 0),
  439. MLXSW_SP_SB_MM(20000, 0xff, 0),
  440. MLXSW_SP_SB_MM(20000, 0xff, 0),
  441. MLXSW_SP_SB_MM(20000, 0xff, 0),
  442. MLXSW_SP_SB_MM(20000, 0xff, 0),
  443. MLXSW_SP_SB_MM(20000, 0xff, 0),
  444. MLXSW_SP_SB_MM(20000, 0xff, 0),
  445. MLXSW_SP_SB_MM(20000, 0xff, 0),
  446. MLXSW_SP_SB_MM(20000, 0xff, 0),
  447. MLXSW_SP_SB_MM(20000, 0xff, 0),
  448. MLXSW_SP_SB_MM(20000, 0xff, 0),
  449. };
  450. #define MLXSW_SP_SB_MMS_LEN ARRAY_SIZE(mlxsw_sp_sb_mms)
  451. static int mlxsw_sp_sb_mms_init(struct mlxsw_sp *mlxsw_sp)
  452. {
  453. char sbmm_pl[MLXSW_REG_SBMM_LEN];
  454. int i;
  455. int err;
  456. for (i = 0; i < MLXSW_SP_SB_MMS_LEN; i++) {
  457. const struct mlxsw_sp_sb_mm *mc;
  458. u32 min_buff;
  459. mc = &mlxsw_sp_sb_mms[i];
  460. /* All pools are initialized using dynamic thresholds,
  461. * therefore 'max_buff' isn't specified in cells.
  462. */
  463. min_buff = mlxsw_sp_bytes_cells(mlxsw_sp, mc->min_buff);
  464. mlxsw_reg_sbmm_pack(sbmm_pl, i, min_buff, mc->max_buff,
  465. mc->pool);
  466. err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbmm), sbmm_pl);
  467. if (err)
  468. return err;
  469. }
  470. return 0;
  471. }
  472. int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp)
  473. {
  474. u64 sb_size;
  475. int err;
  476. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, CELL_SIZE))
  477. return -EIO;
  478. mlxsw_sp->sb.cell_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, CELL_SIZE);
  479. if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_BUFFER_SIZE))
  480. return -EIO;
  481. sb_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_BUFFER_SIZE);
  482. err = mlxsw_sp_sb_ports_init(mlxsw_sp);
  483. if (err)
  484. return err;
  485. err = mlxsw_sp_sb_prs_init(mlxsw_sp);
  486. if (err)
  487. goto err_sb_prs_init;
  488. err = mlxsw_sp_cpu_port_sb_cms_init(mlxsw_sp);
  489. if (err)
  490. goto err_sb_cpu_port_sb_cms_init;
  491. err = mlxsw_sp_sb_mms_init(mlxsw_sp);
  492. if (err)
  493. goto err_sb_mms_init;
  494. err = devlink_sb_register(priv_to_devlink(mlxsw_sp->core), 0, sb_size,
  495. MLXSW_SP_SB_POOL_COUNT,
  496. MLXSW_SP_SB_POOL_COUNT,
  497. MLXSW_SP_SB_TC_COUNT,
  498. MLXSW_SP_SB_TC_COUNT);
  499. if (err)
  500. goto err_devlink_sb_register;
  501. return 0;
  502. err_devlink_sb_register:
  503. err_sb_mms_init:
  504. err_sb_cpu_port_sb_cms_init:
  505. err_sb_prs_init:
  506. mlxsw_sp_sb_ports_fini(mlxsw_sp);
  507. return err;
  508. }
  509. void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp)
  510. {
  511. devlink_sb_unregister(priv_to_devlink(mlxsw_sp->core), 0);
  512. mlxsw_sp_sb_ports_fini(mlxsw_sp);
  513. }
  514. int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port)
  515. {
  516. int err;
  517. err = mlxsw_sp_port_headroom_init(mlxsw_sp_port);
  518. if (err)
  519. return err;
  520. err = mlxsw_sp_port_sb_cms_init(mlxsw_sp_port);
  521. if (err)
  522. return err;
  523. err = mlxsw_sp_port_sb_pms_init(mlxsw_sp_port);
  524. return err;
  525. }
  526. static u8 pool_get(u16 pool_index)
  527. {
  528. return pool_index % MLXSW_SP_SB_POOL_COUNT;
  529. }
  530. static u16 pool_index_get(u8 pool, enum mlxsw_reg_sbxx_dir dir)
  531. {
  532. u16 pool_index;
  533. pool_index = pool;
  534. if (dir == MLXSW_REG_SBXX_DIR_EGRESS)
  535. pool_index += MLXSW_SP_SB_POOL_COUNT;
  536. return pool_index;
  537. }
  538. static enum mlxsw_reg_sbxx_dir dir_get(u16 pool_index)
  539. {
  540. return pool_index < MLXSW_SP_SB_POOL_COUNT ?
  541. MLXSW_REG_SBXX_DIR_INGRESS : MLXSW_REG_SBXX_DIR_EGRESS;
  542. }
  543. int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
  544. unsigned int sb_index, u16 pool_index,
  545. struct devlink_sb_pool_info *pool_info)
  546. {
  547. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  548. u8 pool = pool_get(pool_index);
  549. enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
  550. struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
  551. pool_info->pool_type = (enum devlink_sb_pool_type) dir;
  552. pool_info->size = mlxsw_sp_cells_bytes(mlxsw_sp, pr->size);
  553. pool_info->threshold_type = (enum devlink_sb_threshold_type) pr->mode;
  554. return 0;
  555. }
  556. int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
  557. unsigned int sb_index, u16 pool_index, u32 size,
  558. enum devlink_sb_threshold_type threshold_type)
  559. {
  560. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  561. u32 pool_size = mlxsw_sp_bytes_cells(mlxsw_sp, size);
  562. u8 pool = pool_get(pool_index);
  563. enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
  564. enum mlxsw_reg_sbpr_mode mode;
  565. if (size > MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_BUFFER_SIZE))
  566. return -EINVAL;
  567. mode = (enum mlxsw_reg_sbpr_mode) threshold_type;
  568. return mlxsw_sp_sb_pr_write(mlxsw_sp, pool, dir, mode, pool_size);
  569. }
  570. #define MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET (-2) /* 3->1, 16->14 */
  571. static u32 mlxsw_sp_sb_threshold_out(struct mlxsw_sp *mlxsw_sp, u8 pool,
  572. enum mlxsw_reg_sbxx_dir dir, u32 max_buff)
  573. {
  574. struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
  575. if (pr->mode == MLXSW_REG_SBPR_MODE_DYNAMIC)
  576. return max_buff - MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
  577. return mlxsw_sp_cells_bytes(mlxsw_sp, max_buff);
  578. }
  579. static int mlxsw_sp_sb_threshold_in(struct mlxsw_sp *mlxsw_sp, u8 pool,
  580. enum mlxsw_reg_sbxx_dir dir, u32 threshold,
  581. u32 *p_max_buff)
  582. {
  583. struct mlxsw_sp_sb_pr *pr = mlxsw_sp_sb_pr_get(mlxsw_sp, pool, dir);
  584. if (pr->mode == MLXSW_REG_SBPR_MODE_DYNAMIC) {
  585. int val;
  586. val = threshold + MLXSW_SP_SB_THRESHOLD_TO_ALPHA_OFFSET;
  587. if (val < MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN ||
  588. val > MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX)
  589. return -EINVAL;
  590. *p_max_buff = val;
  591. } else {
  592. *p_max_buff = mlxsw_sp_bytes_cells(mlxsw_sp, threshold);
  593. }
  594. return 0;
  595. }
  596. int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
  597. unsigned int sb_index, u16 pool_index,
  598. u32 *p_threshold)
  599. {
  600. struct mlxsw_sp_port *mlxsw_sp_port =
  601. mlxsw_core_port_driver_priv(mlxsw_core_port);
  602. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  603. u8 local_port = mlxsw_sp_port->local_port;
  604. u8 pool = pool_get(pool_index);
  605. enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
  606. struct mlxsw_sp_sb_pm *pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port,
  607. pool, dir);
  608. *p_threshold = mlxsw_sp_sb_threshold_out(mlxsw_sp, pool, dir,
  609. pm->max_buff);
  610. return 0;
  611. }
  612. int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
  613. unsigned int sb_index, u16 pool_index,
  614. u32 threshold)
  615. {
  616. struct mlxsw_sp_port *mlxsw_sp_port =
  617. mlxsw_core_port_driver_priv(mlxsw_core_port);
  618. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  619. u8 local_port = mlxsw_sp_port->local_port;
  620. u8 pool = pool_get(pool_index);
  621. enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
  622. u32 max_buff;
  623. int err;
  624. err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool, dir,
  625. threshold, &max_buff);
  626. if (err)
  627. return err;
  628. return mlxsw_sp_sb_pm_write(mlxsw_sp, local_port, pool, dir,
  629. 0, max_buff);
  630. }
  631. int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
  632. unsigned int sb_index, u16 tc_index,
  633. enum devlink_sb_pool_type pool_type,
  634. u16 *p_pool_index, u32 *p_threshold)
  635. {
  636. struct mlxsw_sp_port *mlxsw_sp_port =
  637. mlxsw_core_port_driver_priv(mlxsw_core_port);
  638. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  639. u8 local_port = mlxsw_sp_port->local_port;
  640. u8 pg_buff = tc_index;
  641. enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
  642. struct mlxsw_sp_sb_cm *cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port,
  643. pg_buff, dir);
  644. *p_threshold = mlxsw_sp_sb_threshold_out(mlxsw_sp, cm->pool, dir,
  645. cm->max_buff);
  646. *p_pool_index = pool_index_get(cm->pool, dir);
  647. return 0;
  648. }
  649. int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
  650. unsigned int sb_index, u16 tc_index,
  651. enum devlink_sb_pool_type pool_type,
  652. u16 pool_index, u32 threshold)
  653. {
  654. struct mlxsw_sp_port *mlxsw_sp_port =
  655. mlxsw_core_port_driver_priv(mlxsw_core_port);
  656. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  657. u8 local_port = mlxsw_sp_port->local_port;
  658. u8 pg_buff = tc_index;
  659. enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
  660. u8 pool = pool_get(pool_index);
  661. u32 max_buff;
  662. int err;
  663. if (dir != dir_get(pool_index))
  664. return -EINVAL;
  665. err = mlxsw_sp_sb_threshold_in(mlxsw_sp, pool, dir,
  666. threshold, &max_buff);
  667. if (err)
  668. return err;
  669. return mlxsw_sp_sb_cm_write(mlxsw_sp, local_port, pg_buff, dir,
  670. 0, max_buff, pool);
  671. }
  672. #define MASKED_COUNT_MAX \
  673. (MLXSW_REG_SBSR_REC_MAX_COUNT / (MLXSW_SP_SB_TC_COUNT * 2))
  674. struct mlxsw_sp_sb_sr_occ_query_cb_ctx {
  675. u8 masked_count;
  676. u8 local_port_1;
  677. };
  678. static void mlxsw_sp_sb_sr_occ_query_cb(struct mlxsw_core *mlxsw_core,
  679. char *sbsr_pl, size_t sbsr_pl_len,
  680. unsigned long cb_priv)
  681. {
  682. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  683. struct mlxsw_sp_sb_sr_occ_query_cb_ctx cb_ctx;
  684. u8 masked_count;
  685. u8 local_port;
  686. int rec_index = 0;
  687. struct mlxsw_sp_sb_cm *cm;
  688. int i;
  689. memcpy(&cb_ctx, &cb_priv, sizeof(cb_ctx));
  690. masked_count = 0;
  691. for (local_port = cb_ctx.local_port_1;
  692. local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
  693. if (!mlxsw_sp->ports[local_port])
  694. continue;
  695. for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
  696. cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, i,
  697. MLXSW_REG_SBXX_DIR_INGRESS);
  698. mlxsw_reg_sbsr_rec_unpack(sbsr_pl, rec_index++,
  699. &cm->occ.cur, &cm->occ.max);
  700. }
  701. if (++masked_count == cb_ctx.masked_count)
  702. break;
  703. }
  704. masked_count = 0;
  705. for (local_port = cb_ctx.local_port_1;
  706. local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
  707. if (!mlxsw_sp->ports[local_port])
  708. continue;
  709. for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
  710. cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port, i,
  711. MLXSW_REG_SBXX_DIR_EGRESS);
  712. mlxsw_reg_sbsr_rec_unpack(sbsr_pl, rec_index++,
  713. &cm->occ.cur, &cm->occ.max);
  714. }
  715. if (++masked_count == cb_ctx.masked_count)
  716. break;
  717. }
  718. }
  719. int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
  720. unsigned int sb_index)
  721. {
  722. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  723. struct mlxsw_sp_sb_sr_occ_query_cb_ctx cb_ctx;
  724. unsigned long cb_priv;
  725. LIST_HEAD(bulk_list);
  726. char *sbsr_pl;
  727. u8 masked_count;
  728. u8 local_port_1;
  729. u8 local_port = 0;
  730. int i;
  731. int err;
  732. int err2;
  733. sbsr_pl = kmalloc(MLXSW_REG_SBSR_LEN, GFP_KERNEL);
  734. if (!sbsr_pl)
  735. return -ENOMEM;
  736. next_batch:
  737. local_port++;
  738. local_port_1 = local_port;
  739. masked_count = 0;
  740. mlxsw_reg_sbsr_pack(sbsr_pl, false);
  741. for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
  742. mlxsw_reg_sbsr_pg_buff_mask_set(sbsr_pl, i, 1);
  743. mlxsw_reg_sbsr_tclass_mask_set(sbsr_pl, i, 1);
  744. }
  745. for (; local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
  746. if (!mlxsw_sp->ports[local_port])
  747. continue;
  748. mlxsw_reg_sbsr_ingress_port_mask_set(sbsr_pl, local_port, 1);
  749. mlxsw_reg_sbsr_egress_port_mask_set(sbsr_pl, local_port, 1);
  750. for (i = 0; i < MLXSW_SP_SB_POOL_COUNT; i++) {
  751. err = mlxsw_sp_sb_pm_occ_query(mlxsw_sp, local_port, i,
  752. MLXSW_REG_SBXX_DIR_INGRESS,
  753. &bulk_list);
  754. if (err)
  755. goto out;
  756. err = mlxsw_sp_sb_pm_occ_query(mlxsw_sp, local_port, i,
  757. MLXSW_REG_SBXX_DIR_EGRESS,
  758. &bulk_list);
  759. if (err)
  760. goto out;
  761. }
  762. if (++masked_count == MASKED_COUNT_MAX)
  763. goto do_query;
  764. }
  765. do_query:
  766. cb_ctx.masked_count = masked_count;
  767. cb_ctx.local_port_1 = local_port_1;
  768. memcpy(&cb_priv, &cb_ctx, sizeof(cb_ctx));
  769. err = mlxsw_reg_trans_query(mlxsw_core, MLXSW_REG(sbsr), sbsr_pl,
  770. &bulk_list, mlxsw_sp_sb_sr_occ_query_cb,
  771. cb_priv);
  772. if (err)
  773. goto out;
  774. if (local_port < mlxsw_core_max_ports(mlxsw_core))
  775. goto next_batch;
  776. out:
  777. err2 = mlxsw_reg_trans_bulk_wait(&bulk_list);
  778. if (!err)
  779. err = err2;
  780. kfree(sbsr_pl);
  781. return err;
  782. }
  783. int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
  784. unsigned int sb_index)
  785. {
  786. struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
  787. LIST_HEAD(bulk_list);
  788. char *sbsr_pl;
  789. unsigned int masked_count;
  790. u8 local_port = 0;
  791. int i;
  792. int err;
  793. int err2;
  794. sbsr_pl = kmalloc(MLXSW_REG_SBSR_LEN, GFP_KERNEL);
  795. if (!sbsr_pl)
  796. return -ENOMEM;
  797. next_batch:
  798. local_port++;
  799. masked_count = 0;
  800. mlxsw_reg_sbsr_pack(sbsr_pl, true);
  801. for (i = 0; i < MLXSW_SP_SB_TC_COUNT; i++) {
  802. mlxsw_reg_sbsr_pg_buff_mask_set(sbsr_pl, i, 1);
  803. mlxsw_reg_sbsr_tclass_mask_set(sbsr_pl, i, 1);
  804. }
  805. for (; local_port < mlxsw_core_max_ports(mlxsw_core); local_port++) {
  806. if (!mlxsw_sp->ports[local_port])
  807. continue;
  808. mlxsw_reg_sbsr_ingress_port_mask_set(sbsr_pl, local_port, 1);
  809. mlxsw_reg_sbsr_egress_port_mask_set(sbsr_pl, local_port, 1);
  810. for (i = 0; i < MLXSW_SP_SB_POOL_COUNT; i++) {
  811. err = mlxsw_sp_sb_pm_occ_clear(mlxsw_sp, local_port, i,
  812. MLXSW_REG_SBXX_DIR_INGRESS,
  813. &bulk_list);
  814. if (err)
  815. goto out;
  816. err = mlxsw_sp_sb_pm_occ_clear(mlxsw_sp, local_port, i,
  817. MLXSW_REG_SBXX_DIR_EGRESS,
  818. &bulk_list);
  819. if (err)
  820. goto out;
  821. }
  822. if (++masked_count == MASKED_COUNT_MAX)
  823. goto do_query;
  824. }
  825. do_query:
  826. err = mlxsw_reg_trans_query(mlxsw_core, MLXSW_REG(sbsr), sbsr_pl,
  827. &bulk_list, NULL, 0);
  828. if (err)
  829. goto out;
  830. if (local_port < mlxsw_core_max_ports(mlxsw_core))
  831. goto next_batch;
  832. out:
  833. err2 = mlxsw_reg_trans_bulk_wait(&bulk_list);
  834. if (!err)
  835. err = err2;
  836. kfree(sbsr_pl);
  837. return err;
  838. }
  839. int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
  840. unsigned int sb_index, u16 pool_index,
  841. u32 *p_cur, u32 *p_max)
  842. {
  843. struct mlxsw_sp_port *mlxsw_sp_port =
  844. mlxsw_core_port_driver_priv(mlxsw_core_port);
  845. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  846. u8 local_port = mlxsw_sp_port->local_port;
  847. u8 pool = pool_get(pool_index);
  848. enum mlxsw_reg_sbxx_dir dir = dir_get(pool_index);
  849. struct mlxsw_sp_sb_pm *pm = mlxsw_sp_sb_pm_get(mlxsw_sp, local_port,
  850. pool, dir);
  851. *p_cur = mlxsw_sp_cells_bytes(mlxsw_sp, pm->occ.cur);
  852. *p_max = mlxsw_sp_cells_bytes(mlxsw_sp, pm->occ.max);
  853. return 0;
  854. }
  855. int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
  856. unsigned int sb_index, u16 tc_index,
  857. enum devlink_sb_pool_type pool_type,
  858. u32 *p_cur, u32 *p_max)
  859. {
  860. struct mlxsw_sp_port *mlxsw_sp_port =
  861. mlxsw_core_port_driver_priv(mlxsw_core_port);
  862. struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
  863. u8 local_port = mlxsw_sp_port->local_port;
  864. u8 pg_buff = tc_index;
  865. enum mlxsw_reg_sbxx_dir dir = (enum mlxsw_reg_sbxx_dir) pool_type;
  866. struct mlxsw_sp_sb_cm *cm = mlxsw_sp_sb_cm_get(mlxsw_sp, local_port,
  867. pg_buff, dir);
  868. *p_cur = mlxsw_sp_cells_bytes(mlxsw_sp, cm->occ.cur);
  869. *p_max = mlxsw_sp_cells_bytes(mlxsw_sp, cm->occ.max);
  870. return 0;
  871. }