et8ek8_mode.c 15 KB

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  1. /*
  2. * et8ek8_mode.c
  3. *
  4. * Copyright (C) 2008 Nokia Corporation
  5. *
  6. * Contact: Sakari Ailus <sakari.ailus@iki.fi>
  7. * Tuukka Toivonen <tuukkat76@gmail.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * version 2 as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  16. * General Public License for more details.
  17. */
  18. #include "et8ek8_reg.h"
  19. /*
  20. * Stingray sensor mode settings for Scooby
  21. */
  22. /* Mode1_poweron_Mode2_16VGA_2592x1968_12.07fps */
  23. static struct et8ek8_reglist mode1_poweron_mode2_16vga_2592x1968_12_07fps = {
  24. /* (without the +1)
  25. * SPCK = 80 MHz
  26. * CCP2 = 640 MHz
  27. * VCO = 640 MHz
  28. * VCOUNT = 84 (2016)
  29. * HCOUNT = 137 (3288)
  30. * CKREF_DIV = 2
  31. * CKVAR_DIV = 200
  32. * VCO_DIV = 0
  33. * SPCK_DIV = 7
  34. * MRCK_DIV = 7
  35. * LVDSCK_DIV = 0
  36. */
  37. .type = ET8EK8_REGLIST_POWERON,
  38. .mode = {
  39. .sensor_width = 2592,
  40. .sensor_height = 1968,
  41. .sensor_window_origin_x = 0,
  42. .sensor_window_origin_y = 0,
  43. .sensor_window_width = 2592,
  44. .sensor_window_height = 1968,
  45. .width = 3288,
  46. .height = 2016,
  47. .window_origin_x = 0,
  48. .window_origin_y = 0,
  49. .window_width = 2592,
  50. .window_height = 1968,
  51. .pixel_clock = 80000000,
  52. .ext_clock = 9600000,
  53. .timeperframe = {
  54. .numerator = 100,
  55. .denominator = 1207
  56. },
  57. .max_exp = 2012,
  58. /* .max_gain = 0, */
  59. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  60. .sensitivity = 65536
  61. },
  62. .regs = {
  63. /* Need to set firstly */
  64. { ET8EK8_REG_8BIT, 0x126C, 0xCC },
  65. /* Strobe and Data of CCP2 delay are minimized. */
  66. { ET8EK8_REG_8BIT, 0x1269, 0x00 },
  67. /* Refined value of Min H_COUNT */
  68. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  69. /* Frequency of SPCK setting (SPCK=MRCK) */
  70. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  71. { ET8EK8_REG_8BIT, 0x1241, 0x94 },
  72. { ET8EK8_REG_8BIT, 0x1242, 0x02 },
  73. { ET8EK8_REG_8BIT, 0x124B, 0x00 },
  74. { ET8EK8_REG_8BIT, 0x1255, 0xFF },
  75. { ET8EK8_REG_8BIT, 0x1256, 0x9F },
  76. { ET8EK8_REG_8BIT, 0x1258, 0x00 },
  77. /* From parallel out to serial out */
  78. { ET8EK8_REG_8BIT, 0x125D, 0x88 },
  79. /* From w/ embeded data to w/o embeded data */
  80. { ET8EK8_REG_8BIT, 0x125E, 0xC0 },
  81. /* CCP2 out is from STOP to ACTIVE */
  82. { ET8EK8_REG_8BIT, 0x1263, 0x98 },
  83. { ET8EK8_REG_8BIT, 0x1268, 0xC6 },
  84. { ET8EK8_REG_8BIT, 0x1434, 0x00 },
  85. { ET8EK8_REG_8BIT, 0x1163, 0x44 },
  86. { ET8EK8_REG_8BIT, 0x1166, 0x29 },
  87. { ET8EK8_REG_8BIT, 0x1140, 0x02 },
  88. { ET8EK8_REG_8BIT, 0x1011, 0x24 },
  89. { ET8EK8_REG_8BIT, 0x1151, 0x80 },
  90. { ET8EK8_REG_8BIT, 0x1152, 0x23 },
  91. /* Initial setting for improvement2 of lower frequency noise */
  92. { ET8EK8_REG_8BIT, 0x1014, 0x05 },
  93. { ET8EK8_REG_8BIT, 0x1033, 0x06 },
  94. { ET8EK8_REG_8BIT, 0x1034, 0x79 },
  95. { ET8EK8_REG_8BIT, 0x1423, 0x3F },
  96. { ET8EK8_REG_8BIT, 0x1424, 0x3F },
  97. { ET8EK8_REG_8BIT, 0x1426, 0x00 },
  98. /* Switch of Preset-White-balance (0d:disable / 1d:enable) */
  99. { ET8EK8_REG_8BIT, 0x1439, 0x00 },
  100. /* Switch of blemish correction (0d:disable / 1d:enable) */
  101. { ET8EK8_REG_8BIT, 0x161F, 0x60 },
  102. /* Switch of auto noise correction (0d:disable / 1d:enable) */
  103. { ET8EK8_REG_8BIT, 0x1634, 0x00 },
  104. { ET8EK8_REG_8BIT, 0x1646, 0x00 },
  105. { ET8EK8_REG_8BIT, 0x1648, 0x00 },
  106. { ET8EK8_REG_8BIT, 0x113E, 0x01 },
  107. { ET8EK8_REG_8BIT, 0x113F, 0x22 },
  108. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  109. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  110. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  111. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  112. { ET8EK8_REG_8BIT, 0x121B, 0x64 },
  113. { ET8EK8_REG_8BIT, 0x121D, 0x64 },
  114. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  115. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  116. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  117. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  118. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  119. { ET8EK8_REG_TERM, 0, 0}
  120. }
  121. };
  122. /* Mode1_16VGA_2592x1968_13.12fps_DPCM10-8 */
  123. static struct et8ek8_reglist mode1_16vga_2592x1968_13_12fps_dpcm10_8 = {
  124. /* (without the +1)
  125. * SPCK = 80 MHz
  126. * CCP2 = 560 MHz
  127. * VCO = 560 MHz
  128. * VCOUNT = 84 (2016)
  129. * HCOUNT = 128 (3072)
  130. * CKREF_DIV = 2
  131. * CKVAR_DIV = 175
  132. * VCO_DIV = 0
  133. * SPCK_DIV = 6
  134. * MRCK_DIV = 7
  135. * LVDSCK_DIV = 0
  136. */
  137. .type = ET8EK8_REGLIST_MODE,
  138. .mode = {
  139. .sensor_width = 2592,
  140. .sensor_height = 1968,
  141. .sensor_window_origin_x = 0,
  142. .sensor_window_origin_y = 0,
  143. .sensor_window_width = 2592,
  144. .sensor_window_height = 1968,
  145. .width = 3072,
  146. .height = 2016,
  147. .window_origin_x = 0,
  148. .window_origin_y = 0,
  149. .window_width = 2592,
  150. .window_height = 1968,
  151. .pixel_clock = 80000000,
  152. .ext_clock = 9600000,
  153. .timeperframe = {
  154. .numerator = 100,
  155. .denominator = 1292
  156. },
  157. .max_exp = 2012,
  158. /* .max_gain = 0, */
  159. .bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  160. .sensitivity = 65536
  161. },
  162. .regs = {
  163. { ET8EK8_REG_8BIT, 0x1239, 0x57 },
  164. { ET8EK8_REG_8BIT, 0x1238, 0x82 },
  165. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  166. { ET8EK8_REG_8BIT, 0x123A, 0x06 },
  167. { ET8EK8_REG_8BIT, 0x121B, 0x64 },
  168. { ET8EK8_REG_8BIT, 0x121D, 0x64 },
  169. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  170. { ET8EK8_REG_8BIT, 0x1220, 0x80 }, /* <-changed to v14 7E->80 */
  171. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  172. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  173. { ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/ */
  174. { ET8EK8_REG_TERM, 0, 0}
  175. }
  176. };
  177. /* Mode3_4VGA_1296x984_29.99fps_DPCM10-8 */
  178. static struct et8ek8_reglist mode3_4vga_1296x984_29_99fps_dpcm10_8 = {
  179. /* (without the +1)
  180. * SPCK = 96.5333333333333 MHz
  181. * CCP2 = 579.2 MHz
  182. * VCO = 579.2 MHz
  183. * VCOUNT = 84 (2016)
  184. * HCOUNT = 133 (3192)
  185. * CKREF_DIV = 2
  186. * CKVAR_DIV = 181
  187. * VCO_DIV = 0
  188. * SPCK_DIV = 5
  189. * MRCK_DIV = 7
  190. * LVDSCK_DIV = 0
  191. */
  192. .type = ET8EK8_REGLIST_MODE,
  193. .mode = {
  194. .sensor_width = 2592,
  195. .sensor_height = 1968,
  196. .sensor_window_origin_x = 0,
  197. .sensor_window_origin_y = 0,
  198. .sensor_window_width = 2592,
  199. .sensor_window_height = 1968,
  200. .width = 3192,
  201. .height = 1008,
  202. .window_origin_x = 0,
  203. .window_origin_y = 0,
  204. .window_width = 1296,
  205. .window_height = 984,
  206. .pixel_clock = 96533333,
  207. .ext_clock = 9600000,
  208. .timeperframe = {
  209. .numerator = 100,
  210. .denominator = 3000
  211. },
  212. .max_exp = 1004,
  213. /* .max_gain = 0, */
  214. .bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  215. .sensitivity = 65536
  216. },
  217. .regs = {
  218. { ET8EK8_REG_8BIT, 0x1239, 0x5A },
  219. { ET8EK8_REG_8BIT, 0x1238, 0x82 },
  220. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  221. { ET8EK8_REG_8BIT, 0x123A, 0x05 },
  222. { ET8EK8_REG_8BIT, 0x121B, 0x63 },
  223. { ET8EK8_REG_8BIT, 0x1220, 0x85 },
  224. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  225. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  226. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  227. { ET8EK8_REG_8BIT, 0x121D, 0x63 },
  228. { ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/ */
  229. { ET8EK8_REG_TERM, 0, 0}
  230. }
  231. };
  232. /* Mode4_SVGA_864x656_29.88fps */
  233. static struct et8ek8_reglist mode4_svga_864x656_29_88fps = {
  234. /* (without the +1)
  235. * SPCK = 80 MHz
  236. * CCP2 = 320 MHz
  237. * VCO = 640 MHz
  238. * VCOUNT = 84 (2016)
  239. * HCOUNT = 166 (3984)
  240. * CKREF_DIV = 2
  241. * CKVAR_DIV = 200
  242. * VCO_DIV = 0
  243. * SPCK_DIV = 7
  244. * MRCK_DIV = 7
  245. * LVDSCK_DIV = 1
  246. */
  247. .type = ET8EK8_REGLIST_MODE,
  248. .mode = {
  249. .sensor_width = 2592,
  250. .sensor_height = 1968,
  251. .sensor_window_origin_x = 0,
  252. .sensor_window_origin_y = 0,
  253. .sensor_window_width = 2592,
  254. .sensor_window_height = 1968,
  255. .width = 3984,
  256. .height = 672,
  257. .window_origin_x = 0,
  258. .window_origin_y = 0,
  259. .window_width = 864,
  260. .window_height = 656,
  261. .pixel_clock = 80000000,
  262. .ext_clock = 9600000,
  263. .timeperframe = {
  264. .numerator = 100,
  265. .denominator = 2988
  266. },
  267. .max_exp = 668,
  268. /* .max_gain = 0, */
  269. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  270. .sensitivity = 65536
  271. },
  272. .regs = {
  273. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  274. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  275. { ET8EK8_REG_8BIT, 0x123B, 0x71 },
  276. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  277. { ET8EK8_REG_8BIT, 0x121B, 0x62 },
  278. { ET8EK8_REG_8BIT, 0x121D, 0x62 },
  279. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  280. { ET8EK8_REG_8BIT, 0x1220, 0xA6 },
  281. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  282. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  283. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  284. { ET8EK8_REG_TERM, 0, 0}
  285. }
  286. };
  287. /* Mode5_VGA_648x492_29.93fps */
  288. static struct et8ek8_reglist mode5_vga_648x492_29_93fps = {
  289. /* (without the +1)
  290. * SPCK = 80 MHz
  291. * CCP2 = 320 MHz
  292. * VCO = 640 MHz
  293. * VCOUNT = 84 (2016)
  294. * HCOUNT = 221 (5304)
  295. * CKREF_DIV = 2
  296. * CKVAR_DIV = 200
  297. * VCO_DIV = 0
  298. * SPCK_DIV = 7
  299. * MRCK_DIV = 7
  300. * LVDSCK_DIV = 1
  301. */
  302. .type = ET8EK8_REGLIST_MODE,
  303. .mode = {
  304. .sensor_width = 2592,
  305. .sensor_height = 1968,
  306. .sensor_window_origin_x = 0,
  307. .sensor_window_origin_y = 0,
  308. .sensor_window_width = 2592,
  309. .sensor_window_height = 1968,
  310. .width = 5304,
  311. .height = 504,
  312. .window_origin_x = 0,
  313. .window_origin_y = 0,
  314. .window_width = 648,
  315. .window_height = 492,
  316. .pixel_clock = 80000000,
  317. .ext_clock = 9600000,
  318. .timeperframe = {
  319. .numerator = 100,
  320. .denominator = 2993
  321. },
  322. .max_exp = 500,
  323. /* .max_gain = 0, */
  324. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  325. .sensitivity = 65536
  326. },
  327. .regs = {
  328. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  329. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  330. { ET8EK8_REG_8BIT, 0x123B, 0x71 },
  331. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  332. { ET8EK8_REG_8BIT, 0x121B, 0x61 },
  333. { ET8EK8_REG_8BIT, 0x121D, 0x61 },
  334. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  335. { ET8EK8_REG_8BIT, 0x1220, 0xDD },
  336. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  337. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  338. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  339. { ET8EK8_REG_TERM, 0, 0}
  340. }
  341. };
  342. /* Mode2_16VGA_2592x1968_3.99fps */
  343. static struct et8ek8_reglist mode2_16vga_2592x1968_3_99fps = {
  344. /* (without the +1)
  345. * SPCK = 80 MHz
  346. * CCP2 = 640 MHz
  347. * VCO = 640 MHz
  348. * VCOUNT = 254 (6096)
  349. * HCOUNT = 137 (3288)
  350. * CKREF_DIV = 2
  351. * CKVAR_DIV = 200
  352. * VCO_DIV = 0
  353. * SPCK_DIV = 7
  354. * MRCK_DIV = 7
  355. * LVDSCK_DIV = 0
  356. */
  357. .type = ET8EK8_REGLIST_MODE,
  358. .mode = {
  359. .sensor_width = 2592,
  360. .sensor_height = 1968,
  361. .sensor_window_origin_x = 0,
  362. .sensor_window_origin_y = 0,
  363. .sensor_window_width = 2592,
  364. .sensor_window_height = 1968,
  365. .width = 3288,
  366. .height = 6096,
  367. .window_origin_x = 0,
  368. .window_origin_y = 0,
  369. .window_width = 2592,
  370. .window_height = 1968,
  371. .pixel_clock = 80000000,
  372. .ext_clock = 9600000,
  373. .timeperframe = {
  374. .numerator = 100,
  375. .denominator = 399
  376. },
  377. .max_exp = 6092,
  378. /* .max_gain = 0, */
  379. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  380. .sensitivity = 65536
  381. },
  382. .regs = {
  383. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  384. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  385. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  386. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  387. { ET8EK8_REG_8BIT, 0x121B, 0x64 },
  388. { ET8EK8_REG_8BIT, 0x121D, 0x64 },
  389. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  390. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  391. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  392. { ET8EK8_REG_8BIT, 0x1222, 0xFE },
  393. { ET8EK8_REG_TERM, 0, 0}
  394. }
  395. };
  396. /* Mode_648x492_5fps */
  397. static struct et8ek8_reglist mode_648x492_5fps = {
  398. /* (without the +1)
  399. * SPCK = 13.3333333333333 MHz
  400. * CCP2 = 53.3333333333333 MHz
  401. * VCO = 640 MHz
  402. * VCOUNT = 84 (2016)
  403. * HCOUNT = 221 (5304)
  404. * CKREF_DIV = 2
  405. * CKVAR_DIV = 200
  406. * VCO_DIV = 5
  407. * SPCK_DIV = 7
  408. * MRCK_DIV = 7
  409. * LVDSCK_DIV = 1
  410. */
  411. .type = ET8EK8_REGLIST_MODE,
  412. .mode = {
  413. .sensor_width = 2592,
  414. .sensor_height = 1968,
  415. .sensor_window_origin_x = 0,
  416. .sensor_window_origin_y = 0,
  417. .sensor_window_width = 2592,
  418. .sensor_window_height = 1968,
  419. .width = 5304,
  420. .height = 504,
  421. .window_origin_x = 0,
  422. .window_origin_y = 0,
  423. .window_width = 648,
  424. .window_height = 492,
  425. .pixel_clock = 13333333,
  426. .ext_clock = 9600000,
  427. .timeperframe = {
  428. .numerator = 100,
  429. .denominator = 499
  430. },
  431. .max_exp = 500,
  432. /* .max_gain = 0, */
  433. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  434. .sensitivity = 65536
  435. },
  436. .regs = {
  437. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  438. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  439. { ET8EK8_REG_8BIT, 0x123B, 0x71 },
  440. { ET8EK8_REG_8BIT, 0x123A, 0x57 },
  441. { ET8EK8_REG_8BIT, 0x121B, 0x61 },
  442. { ET8EK8_REG_8BIT, 0x121D, 0x61 },
  443. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  444. { ET8EK8_REG_8BIT, 0x1220, 0xDD },
  445. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  446. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  447. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  448. { ET8EK8_REG_TERM, 0, 0}
  449. }
  450. };
  451. /* Mode3_4VGA_1296x984_5fps */
  452. static struct et8ek8_reglist mode3_4vga_1296x984_5fps = {
  453. /* (without the +1)
  454. * SPCK = 49.4 MHz
  455. * CCP2 = 395.2 MHz
  456. * VCO = 790.4 MHz
  457. * VCOUNT = 250 (6000)
  458. * HCOUNT = 137 (3288)
  459. * CKREF_DIV = 2
  460. * CKVAR_DIV = 247
  461. * VCO_DIV = 1
  462. * SPCK_DIV = 7
  463. * MRCK_DIV = 7
  464. * LVDSCK_DIV = 0
  465. */
  466. .type = ET8EK8_REGLIST_MODE,
  467. .mode = {
  468. .sensor_width = 2592,
  469. .sensor_height = 1968,
  470. .sensor_window_origin_x = 0,
  471. .sensor_window_origin_y = 0,
  472. .sensor_window_width = 2592,
  473. .sensor_window_height = 1968,
  474. .width = 3288,
  475. .height = 3000,
  476. .window_origin_x = 0,
  477. .window_origin_y = 0,
  478. .window_width = 1296,
  479. .window_height = 984,
  480. .pixel_clock = 49400000,
  481. .ext_clock = 9600000,
  482. .timeperframe = {
  483. .numerator = 100,
  484. .denominator = 501
  485. },
  486. .max_exp = 2996,
  487. /* .max_gain = 0, */
  488. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  489. .sensitivity = 65536
  490. },
  491. .regs = {
  492. { ET8EK8_REG_8BIT, 0x1239, 0x7B },
  493. { ET8EK8_REG_8BIT, 0x1238, 0x82 },
  494. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  495. { ET8EK8_REG_8BIT, 0x123A, 0x17 },
  496. { ET8EK8_REG_8BIT, 0x121B, 0x63 },
  497. { ET8EK8_REG_8BIT, 0x121D, 0x63 },
  498. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  499. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  500. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  501. { ET8EK8_REG_8BIT, 0x1222, 0xFA },
  502. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  503. { ET8EK8_REG_TERM, 0, 0}
  504. }
  505. };
  506. /* Mode_4VGA_1296x984_25fps_DPCM10-8 */
  507. static struct et8ek8_reglist mode_4vga_1296x984_25fps_dpcm10_8 = {
  508. /* (without the +1)
  509. * SPCK = 84.2666666666667 MHz
  510. * CCP2 = 505.6 MHz
  511. * VCO = 505.6 MHz
  512. * VCOUNT = 88 (2112)
  513. * HCOUNT = 133 (3192)
  514. * CKREF_DIV = 2
  515. * CKVAR_DIV = 158
  516. * VCO_DIV = 0
  517. * SPCK_DIV = 5
  518. * MRCK_DIV = 7
  519. * LVDSCK_DIV = 0
  520. */
  521. .type = ET8EK8_REGLIST_MODE,
  522. .mode = {
  523. .sensor_width = 2592,
  524. .sensor_height = 1968,
  525. .sensor_window_origin_x = 0,
  526. .sensor_window_origin_y = 0,
  527. .sensor_window_width = 2592,
  528. .sensor_window_height = 1968,
  529. .width = 3192,
  530. .height = 1056,
  531. .window_origin_x = 0,
  532. .window_origin_y = 0,
  533. .window_width = 1296,
  534. .window_height = 984,
  535. .pixel_clock = 84266667,
  536. .ext_clock = 9600000,
  537. .timeperframe = {
  538. .numerator = 100,
  539. .denominator = 2500
  540. },
  541. .max_exp = 1052,
  542. /* .max_gain = 0, */
  543. .bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  544. .sensitivity = 65536
  545. },
  546. .regs = {
  547. { ET8EK8_REG_8BIT, 0x1239, 0x4F },
  548. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  549. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  550. { ET8EK8_REG_8BIT, 0x123A, 0x05 },
  551. { ET8EK8_REG_8BIT, 0x121B, 0x63 },
  552. { ET8EK8_REG_8BIT, 0x1220, 0x85 },
  553. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  554. { ET8EK8_REG_8BIT, 0x1222, 0x58 },
  555. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  556. { ET8EK8_REG_8BIT, 0x121D, 0x63 },
  557. { ET8EK8_REG_8BIT, 0x125D, 0x83 },
  558. { ET8EK8_REG_TERM, 0, 0}
  559. }
  560. };
  561. struct et8ek8_meta_reglist meta_reglist = {
  562. .version = "V14 03-June-2008",
  563. .reglist = {
  564. { .ptr = &mode1_poweron_mode2_16vga_2592x1968_12_07fps },
  565. { .ptr = &mode1_16vga_2592x1968_13_12fps_dpcm10_8 },
  566. { .ptr = &mode3_4vga_1296x984_29_99fps_dpcm10_8 },
  567. { .ptr = &mode4_svga_864x656_29_88fps },
  568. { .ptr = &mode5_vga_648x492_29_93fps },
  569. { .ptr = &mode2_16vga_2592x1968_3_99fps },
  570. { .ptr = &mode_648x492_5fps },
  571. { .ptr = &mode3_4vga_1296x984_5fps },
  572. { .ptr = &mode_4vga_1296x984_25fps_dpcm10_8 },
  573. { .ptr = NULL }
  574. }
  575. };