mtk_dsi.c 29 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <drm/drmP.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_crtc_helper.h>
  16. #include <drm/drm_mipi_dsi.h>
  17. #include <drm/drm_panel.h>
  18. #include <drm/drm_of.h>
  19. #include <linux/clk.h>
  20. #include <linux/component.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/irq.h>
  23. #include <linux/of.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/phy/phy.h>
  26. #include <linux/platform_device.h>
  27. #include <video/mipi_display.h>
  28. #include <video/videomode.h>
  29. #include "mtk_drm_ddp_comp.h"
  30. #define DSI_START 0x00
  31. #define DSI_INTEN 0x08
  32. #define DSI_INTSTA 0x0c
  33. #define LPRX_RD_RDY_INT_FLAG BIT(0)
  34. #define CMD_DONE_INT_FLAG BIT(1)
  35. #define TE_RDY_INT_FLAG BIT(2)
  36. #define VM_DONE_INT_FLAG BIT(3)
  37. #define EXT_TE_RDY_INT_FLAG BIT(4)
  38. #define DSI_BUSY BIT(31)
  39. #define DSI_CON_CTRL 0x10
  40. #define DSI_RESET BIT(0)
  41. #define DSI_EN BIT(1)
  42. #define DSI_MODE_CTRL 0x14
  43. #define MODE (3)
  44. #define CMD_MODE 0
  45. #define SYNC_PULSE_MODE 1
  46. #define SYNC_EVENT_MODE 2
  47. #define BURST_MODE 3
  48. #define FRM_MODE BIT(16)
  49. #define MIX_MODE BIT(17)
  50. #define DSI_TXRX_CTRL 0x18
  51. #define VC_NUM BIT(1)
  52. #define LANE_NUM (0xf << 2)
  53. #define DIS_EOT BIT(6)
  54. #define NULL_EN BIT(7)
  55. #define TE_FREERUN BIT(8)
  56. #define EXT_TE_EN BIT(9)
  57. #define EXT_TE_EDGE BIT(10)
  58. #define MAX_RTN_SIZE (0xf << 12)
  59. #define HSTX_CKLP_EN BIT(16)
  60. #define DSI_PSCTRL 0x1c
  61. #define DSI_PS_WC 0x3fff
  62. #define DSI_PS_SEL (3 << 16)
  63. #define PACKED_PS_16BIT_RGB565 (0 << 16)
  64. #define LOOSELY_PS_18BIT_RGB666 (1 << 16)
  65. #define PACKED_PS_18BIT_RGB666 (2 << 16)
  66. #define PACKED_PS_24BIT_RGB888 (3 << 16)
  67. #define DSI_VSA_NL 0x20
  68. #define DSI_VBP_NL 0x24
  69. #define DSI_VFP_NL 0x28
  70. #define DSI_VACT_NL 0x2C
  71. #define DSI_HSA_WC 0x50
  72. #define DSI_HBP_WC 0x54
  73. #define DSI_HFP_WC 0x58
  74. #define DSI_CMDQ_SIZE 0x60
  75. #define CMDQ_SIZE 0x3f
  76. #define DSI_HSTX_CKL_WC 0x64
  77. #define DSI_RX_DATA0 0x74
  78. #define DSI_RX_DATA1 0x78
  79. #define DSI_RX_DATA2 0x7c
  80. #define DSI_RX_DATA3 0x80
  81. #define DSI_RACK 0x84
  82. #define RACK BIT(0)
  83. #define DSI_PHY_LCCON 0x104
  84. #define LC_HS_TX_EN BIT(0)
  85. #define LC_ULPM_EN BIT(1)
  86. #define LC_WAKEUP_EN BIT(2)
  87. #define DSI_PHY_LD0CON 0x108
  88. #define LD0_HS_TX_EN BIT(0)
  89. #define LD0_ULPM_EN BIT(1)
  90. #define LD0_WAKEUP_EN BIT(2)
  91. #define DSI_PHY_TIMECON0 0x110
  92. #define LPX (0xff << 0)
  93. #define HS_PREP (0xff << 8)
  94. #define HS_ZERO (0xff << 16)
  95. #define HS_TRAIL (0xff << 24)
  96. #define DSI_PHY_TIMECON1 0x114
  97. #define TA_GO (0xff << 0)
  98. #define TA_SURE (0xff << 8)
  99. #define TA_GET (0xff << 16)
  100. #define DA_HS_EXIT (0xff << 24)
  101. #define DSI_PHY_TIMECON2 0x118
  102. #define CONT_DET (0xff << 0)
  103. #define CLK_ZERO (0xff << 16)
  104. #define CLK_TRAIL (0xff << 24)
  105. #define DSI_PHY_TIMECON3 0x11c
  106. #define CLK_HS_PREP (0xff << 0)
  107. #define CLK_HS_POST (0xff << 8)
  108. #define CLK_HS_EXIT (0xff << 16)
  109. #define DSI_VM_CMD_CON 0x130
  110. #define VM_CMD_EN BIT(0)
  111. #define TS_VFP_EN BIT(5)
  112. #define DSI_CMDQ0 0x180
  113. #define CONFIG (0xff << 0)
  114. #define SHORT_PACKET 0
  115. #define LONG_PACKET 2
  116. #define BTA BIT(2)
  117. #define DATA_ID (0xff << 8)
  118. #define DATA_0 (0xff << 16)
  119. #define DATA_1 (0xff << 24)
  120. #define T_LPX 5
  121. #define T_HS_PREP 6
  122. #define T_HS_TRAIL 8
  123. #define T_HS_EXIT 7
  124. #define T_HS_ZERO 10
  125. #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
  126. #define MTK_DSI_HOST_IS_READ(type) \
  127. ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
  128. (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
  129. (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
  130. (type == MIPI_DSI_DCS_READ))
  131. struct phy;
  132. struct mtk_dsi {
  133. struct mtk_ddp_comp ddp_comp;
  134. struct device *dev;
  135. struct mipi_dsi_host host;
  136. struct drm_encoder encoder;
  137. struct drm_connector conn;
  138. struct drm_panel *panel;
  139. struct drm_bridge *bridge;
  140. struct phy *phy;
  141. void __iomem *regs;
  142. struct clk *engine_clk;
  143. struct clk *digital_clk;
  144. struct clk *hs_clk;
  145. u32 data_rate;
  146. unsigned long mode_flags;
  147. enum mipi_dsi_pixel_format format;
  148. unsigned int lanes;
  149. struct videomode vm;
  150. int refcount;
  151. bool enabled;
  152. u32 irq_data;
  153. wait_queue_head_t irq_wait_queue;
  154. };
  155. static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
  156. {
  157. return container_of(e, struct mtk_dsi, encoder);
  158. }
  159. static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
  160. {
  161. return container_of(c, struct mtk_dsi, conn);
  162. }
  163. static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
  164. {
  165. return container_of(h, struct mtk_dsi, host);
  166. }
  167. static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
  168. {
  169. u32 temp = readl(dsi->regs + offset);
  170. writel((temp & ~mask) | (data & mask), dsi->regs + offset);
  171. }
  172. static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
  173. {
  174. u32 timcon0, timcon1, timcon2, timcon3;
  175. u32 ui, cycle_time;
  176. ui = 1000 / dsi->data_rate + 0x01;
  177. cycle_time = 8000 / dsi->data_rate + 0x01;
  178. timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
  179. timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
  180. T_HS_EXIT << 24;
  181. timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
  182. (NS_TO_CYCLE(0x150, cycle_time) << 16);
  183. timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
  184. NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
  185. writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
  186. writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
  187. writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
  188. writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
  189. }
  190. static void mtk_dsi_enable(struct mtk_dsi *dsi)
  191. {
  192. mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
  193. }
  194. static void mtk_dsi_disable(struct mtk_dsi *dsi)
  195. {
  196. mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
  197. }
  198. static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
  199. {
  200. mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
  201. mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
  202. }
  203. static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
  204. {
  205. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
  206. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
  207. }
  208. static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
  209. {
  210. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
  211. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
  212. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
  213. }
  214. static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
  215. {
  216. mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
  217. mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
  218. }
  219. static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
  220. {
  221. mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
  222. mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
  223. mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
  224. }
  225. static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
  226. {
  227. u32 tmp_reg1;
  228. tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
  229. return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
  230. }
  231. static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
  232. {
  233. if (enter && !mtk_dsi_clk_hs_state(dsi))
  234. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
  235. else if (!enter && mtk_dsi_clk_hs_state(dsi))
  236. mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
  237. }
  238. static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
  239. {
  240. u32 vid_mode = CMD_MODE;
  241. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
  242. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  243. vid_mode = BURST_MODE;
  244. else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  245. vid_mode = SYNC_PULSE_MODE;
  246. else
  247. vid_mode = SYNC_EVENT_MODE;
  248. }
  249. writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
  250. }
  251. static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
  252. {
  253. mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
  254. mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
  255. }
  256. static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
  257. {
  258. struct videomode *vm = &dsi->vm;
  259. u32 dsi_buf_bpp, ps_wc;
  260. u32 ps_bpp_mode;
  261. if (dsi->format == MIPI_DSI_FMT_RGB565)
  262. dsi_buf_bpp = 2;
  263. else
  264. dsi_buf_bpp = 3;
  265. ps_wc = vm->hactive * dsi_buf_bpp;
  266. ps_bpp_mode = ps_wc;
  267. switch (dsi->format) {
  268. case MIPI_DSI_FMT_RGB888:
  269. ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
  270. break;
  271. case MIPI_DSI_FMT_RGB666:
  272. ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
  273. break;
  274. case MIPI_DSI_FMT_RGB666_PACKED:
  275. ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
  276. break;
  277. case MIPI_DSI_FMT_RGB565:
  278. ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
  279. break;
  280. }
  281. writel(vm->vactive, dsi->regs + DSI_VACT_NL);
  282. writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
  283. writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
  284. }
  285. static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
  286. {
  287. u32 tmp_reg;
  288. switch (dsi->lanes) {
  289. case 1:
  290. tmp_reg = 1 << 2;
  291. break;
  292. case 2:
  293. tmp_reg = 3 << 2;
  294. break;
  295. case 3:
  296. tmp_reg = 7 << 2;
  297. break;
  298. case 4:
  299. tmp_reg = 0xf << 2;
  300. break;
  301. default:
  302. tmp_reg = 0xf << 2;
  303. break;
  304. }
  305. tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
  306. tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
  307. writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
  308. }
  309. static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
  310. {
  311. u32 dsi_tmp_buf_bpp;
  312. u32 tmp_reg;
  313. switch (dsi->format) {
  314. case MIPI_DSI_FMT_RGB888:
  315. tmp_reg = PACKED_PS_24BIT_RGB888;
  316. dsi_tmp_buf_bpp = 3;
  317. break;
  318. case MIPI_DSI_FMT_RGB666:
  319. tmp_reg = LOOSELY_PS_18BIT_RGB666;
  320. dsi_tmp_buf_bpp = 3;
  321. break;
  322. case MIPI_DSI_FMT_RGB666_PACKED:
  323. tmp_reg = PACKED_PS_18BIT_RGB666;
  324. dsi_tmp_buf_bpp = 3;
  325. break;
  326. case MIPI_DSI_FMT_RGB565:
  327. tmp_reg = PACKED_PS_16BIT_RGB565;
  328. dsi_tmp_buf_bpp = 2;
  329. break;
  330. default:
  331. tmp_reg = PACKED_PS_24BIT_RGB888;
  332. dsi_tmp_buf_bpp = 3;
  333. break;
  334. }
  335. tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
  336. writel(tmp_reg, dsi->regs + DSI_PSCTRL);
  337. }
  338. static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
  339. {
  340. u32 horizontal_sync_active_byte;
  341. u32 horizontal_backporch_byte;
  342. u32 horizontal_frontporch_byte;
  343. u32 dsi_tmp_buf_bpp;
  344. struct videomode *vm = &dsi->vm;
  345. if (dsi->format == MIPI_DSI_FMT_RGB565)
  346. dsi_tmp_buf_bpp = 2;
  347. else
  348. dsi_tmp_buf_bpp = 3;
  349. writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
  350. writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
  351. writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
  352. writel(vm->vactive, dsi->regs + DSI_VACT_NL);
  353. horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
  354. if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  355. horizontal_backporch_byte =
  356. (vm->hback_porch * dsi_tmp_buf_bpp - 10);
  357. else
  358. horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
  359. dsi_tmp_buf_bpp - 10);
  360. horizontal_frontporch_byte = (vm->hfront_porch * dsi_tmp_buf_bpp - 12);
  361. writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
  362. writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
  363. writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
  364. mtk_dsi_ps_control(dsi);
  365. }
  366. static void mtk_dsi_start(struct mtk_dsi *dsi)
  367. {
  368. writel(0, dsi->regs + DSI_START);
  369. writel(1, dsi->regs + DSI_START);
  370. }
  371. static void mtk_dsi_stop(struct mtk_dsi *dsi)
  372. {
  373. writel(0, dsi->regs + DSI_START);
  374. }
  375. static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
  376. {
  377. writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
  378. }
  379. static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
  380. {
  381. u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
  382. writel(inten, dsi->regs + DSI_INTEN);
  383. }
  384. static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
  385. {
  386. dsi->irq_data |= irq_bit;
  387. }
  388. static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
  389. {
  390. dsi->irq_data &= ~irq_bit;
  391. }
  392. static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
  393. unsigned int timeout)
  394. {
  395. s32 ret = 0;
  396. unsigned long jiffies = msecs_to_jiffies(timeout);
  397. ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
  398. dsi->irq_data & irq_flag,
  399. jiffies);
  400. if (ret == 0) {
  401. DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
  402. mtk_dsi_enable(dsi);
  403. mtk_dsi_reset_engine(dsi);
  404. }
  405. return ret;
  406. }
  407. static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
  408. {
  409. struct mtk_dsi *dsi = dev_id;
  410. u32 status, tmp;
  411. u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
  412. status = readl(dsi->regs + DSI_INTSTA) & flag;
  413. if (status) {
  414. do {
  415. mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
  416. tmp = readl(dsi->regs + DSI_INTSTA);
  417. } while (tmp & DSI_BUSY);
  418. mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
  419. mtk_dsi_irq_data_set(dsi, status);
  420. wake_up_interruptible(&dsi->irq_wait_queue);
  421. }
  422. return IRQ_HANDLED;
  423. }
  424. static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
  425. {
  426. mtk_dsi_irq_data_clear(dsi, irq_flag);
  427. mtk_dsi_set_cmd_mode(dsi);
  428. if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
  429. DRM_ERROR("failed to switch cmd mode\n");
  430. return -ETIME;
  431. } else {
  432. return 0;
  433. }
  434. }
  435. static int mtk_dsi_poweron(struct mtk_dsi *dsi)
  436. {
  437. struct device *dev = dsi->dev;
  438. int ret;
  439. u64 pixel_clock, total_bits;
  440. u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
  441. if (++dsi->refcount != 1)
  442. return 0;
  443. switch (dsi->format) {
  444. case MIPI_DSI_FMT_RGB565:
  445. bit_per_pixel = 16;
  446. break;
  447. case MIPI_DSI_FMT_RGB666_PACKED:
  448. bit_per_pixel = 18;
  449. break;
  450. case MIPI_DSI_FMT_RGB666:
  451. case MIPI_DSI_FMT_RGB888:
  452. default:
  453. bit_per_pixel = 24;
  454. break;
  455. }
  456. /**
  457. * vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
  458. * htotal_time = htotal * byte_per_pixel / num_lanes
  459. * overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
  460. * mipi_ratio = (htotal_time + overhead_time) / htotal_time
  461. * data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
  462. */
  463. pixel_clock = dsi->vm.pixelclock * 1000;
  464. htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
  465. dsi->vm.hsync_len;
  466. htotal_bits = htotal * bit_per_pixel;
  467. overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
  468. T_HS_EXIT;
  469. overhead_bits = overhead_cycles * dsi->lanes * 8;
  470. total_bits = htotal_bits + overhead_bits;
  471. dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
  472. htotal * dsi->lanes);
  473. ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
  474. if (ret < 0) {
  475. dev_err(dev, "Failed to set data rate: %d\n", ret);
  476. goto err_refcount;
  477. }
  478. phy_power_on(dsi->phy);
  479. ret = clk_prepare_enable(dsi->engine_clk);
  480. if (ret < 0) {
  481. dev_err(dev, "Failed to enable engine clock: %d\n", ret);
  482. goto err_phy_power_off;
  483. }
  484. ret = clk_prepare_enable(dsi->digital_clk);
  485. if (ret < 0) {
  486. dev_err(dev, "Failed to enable digital clock: %d\n", ret);
  487. goto err_disable_engine_clk;
  488. }
  489. mtk_dsi_enable(dsi);
  490. mtk_dsi_reset_engine(dsi);
  491. mtk_dsi_phy_timconfig(dsi);
  492. mtk_dsi_rxtx_control(dsi);
  493. mtk_dsi_ps_control_vact(dsi);
  494. mtk_dsi_set_vm_cmd(dsi);
  495. mtk_dsi_config_vdo_timing(dsi);
  496. mtk_dsi_set_interrupt_enable(dsi);
  497. mtk_dsi_clk_ulp_mode_leave(dsi);
  498. mtk_dsi_lane0_ulp_mode_leave(dsi);
  499. mtk_dsi_clk_hs_mode(dsi, 0);
  500. if (dsi->panel) {
  501. if (drm_panel_prepare(dsi->panel)) {
  502. DRM_ERROR("failed to prepare the panel\n");
  503. goto err_disable_digital_clk;
  504. }
  505. }
  506. return 0;
  507. err_disable_digital_clk:
  508. clk_disable_unprepare(dsi->digital_clk);
  509. err_disable_engine_clk:
  510. clk_disable_unprepare(dsi->engine_clk);
  511. err_phy_power_off:
  512. phy_power_off(dsi->phy);
  513. err_refcount:
  514. dsi->refcount--;
  515. return ret;
  516. }
  517. static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
  518. {
  519. if (WARN_ON(dsi->refcount == 0))
  520. return;
  521. if (--dsi->refcount != 0)
  522. return;
  523. if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
  524. if (dsi->panel) {
  525. if (drm_panel_unprepare(dsi->panel)) {
  526. DRM_ERROR("failed to unprepare the panel\n");
  527. return;
  528. }
  529. }
  530. }
  531. mtk_dsi_reset_engine(dsi);
  532. mtk_dsi_lane0_ulp_mode_enter(dsi);
  533. mtk_dsi_clk_ulp_mode_enter(dsi);
  534. mtk_dsi_disable(dsi);
  535. clk_disable_unprepare(dsi->engine_clk);
  536. clk_disable_unprepare(dsi->digital_clk);
  537. phy_power_off(dsi->phy);
  538. }
  539. static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
  540. {
  541. int ret;
  542. if (dsi->enabled)
  543. return;
  544. ret = mtk_dsi_poweron(dsi);
  545. if (ret < 0) {
  546. DRM_ERROR("failed to power on dsi\n");
  547. return;
  548. }
  549. mtk_dsi_set_mode(dsi);
  550. mtk_dsi_clk_hs_mode(dsi, 1);
  551. mtk_dsi_start(dsi);
  552. if (dsi->panel) {
  553. if (drm_panel_enable(dsi->panel)) {
  554. DRM_ERROR("failed to enable the panel\n");
  555. goto err_dsi_power_off;
  556. }
  557. }
  558. dsi->enabled = true;
  559. return;
  560. err_dsi_power_off:
  561. mtk_dsi_stop(dsi);
  562. mtk_dsi_poweroff(dsi);
  563. }
  564. static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
  565. {
  566. if (!dsi->enabled)
  567. return;
  568. if (dsi->panel) {
  569. if (drm_panel_disable(dsi->panel)) {
  570. DRM_ERROR("failed to disable the panel\n");
  571. return;
  572. }
  573. }
  574. mtk_dsi_stop(dsi);
  575. mtk_dsi_poweroff(dsi);
  576. dsi->enabled = false;
  577. }
  578. static void mtk_dsi_encoder_destroy(struct drm_encoder *encoder)
  579. {
  580. drm_encoder_cleanup(encoder);
  581. }
  582. static const struct drm_encoder_funcs mtk_dsi_encoder_funcs = {
  583. .destroy = mtk_dsi_encoder_destroy,
  584. };
  585. static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
  586. const struct drm_display_mode *mode,
  587. struct drm_display_mode *adjusted_mode)
  588. {
  589. return true;
  590. }
  591. static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
  592. struct drm_display_mode *mode,
  593. struct drm_display_mode *adjusted)
  594. {
  595. struct mtk_dsi *dsi = encoder_to_dsi(encoder);
  596. dsi->vm.pixelclock = adjusted->clock;
  597. dsi->vm.hactive = adjusted->hdisplay;
  598. dsi->vm.hback_porch = adjusted->htotal - adjusted->hsync_end;
  599. dsi->vm.hfront_porch = adjusted->hsync_start - adjusted->hdisplay;
  600. dsi->vm.hsync_len = adjusted->hsync_end - adjusted->hsync_start;
  601. dsi->vm.vactive = adjusted->vdisplay;
  602. dsi->vm.vback_porch = adjusted->vtotal - adjusted->vsync_end;
  603. dsi->vm.vfront_porch = adjusted->vsync_start - adjusted->vdisplay;
  604. dsi->vm.vsync_len = adjusted->vsync_end - adjusted->vsync_start;
  605. }
  606. static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
  607. {
  608. struct mtk_dsi *dsi = encoder_to_dsi(encoder);
  609. mtk_output_dsi_disable(dsi);
  610. }
  611. static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
  612. {
  613. struct mtk_dsi *dsi = encoder_to_dsi(encoder);
  614. mtk_output_dsi_enable(dsi);
  615. }
  616. static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
  617. {
  618. struct mtk_dsi *dsi = connector_to_dsi(connector);
  619. return drm_panel_get_modes(dsi->panel);
  620. }
  621. static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
  622. .mode_fixup = mtk_dsi_encoder_mode_fixup,
  623. .mode_set = mtk_dsi_encoder_mode_set,
  624. .disable = mtk_dsi_encoder_disable,
  625. .enable = mtk_dsi_encoder_enable,
  626. };
  627. static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
  628. .dpms = drm_atomic_helper_connector_dpms,
  629. .fill_modes = drm_helper_probe_single_connector_modes,
  630. .destroy = drm_connector_cleanup,
  631. .reset = drm_atomic_helper_connector_reset,
  632. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  633. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  634. };
  635. static const struct drm_connector_helper_funcs
  636. mtk_dsi_connector_helper_funcs = {
  637. .get_modes = mtk_dsi_connector_get_modes,
  638. };
  639. static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
  640. {
  641. int ret;
  642. ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
  643. DRM_MODE_CONNECTOR_DSI);
  644. if (ret) {
  645. DRM_ERROR("Failed to connector init to drm\n");
  646. return ret;
  647. }
  648. drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
  649. dsi->conn.dpms = DRM_MODE_DPMS_OFF;
  650. drm_mode_connector_attach_encoder(&dsi->conn, &dsi->encoder);
  651. if (dsi->panel) {
  652. ret = drm_panel_attach(dsi->panel, &dsi->conn);
  653. if (ret) {
  654. DRM_ERROR("Failed to attach panel to drm\n");
  655. goto err_connector_cleanup;
  656. }
  657. }
  658. return 0;
  659. err_connector_cleanup:
  660. drm_connector_cleanup(&dsi->conn);
  661. return ret;
  662. }
  663. static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
  664. {
  665. int ret;
  666. ret = drm_encoder_init(drm, &dsi->encoder, &mtk_dsi_encoder_funcs,
  667. DRM_MODE_ENCODER_DSI, NULL);
  668. if (ret) {
  669. DRM_ERROR("Failed to encoder init to drm\n");
  670. return ret;
  671. }
  672. drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
  673. /*
  674. * Currently display data paths are statically assigned to a crtc each.
  675. * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
  676. */
  677. dsi->encoder.possible_crtcs = 1;
  678. /* If there's a bridge, attach to it and let it create the connector */
  679. ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL);
  680. if (ret) {
  681. DRM_ERROR("Failed to attach bridge to drm\n");
  682. /* Otherwise create our own connector and attach to a panel */
  683. ret = mtk_dsi_create_connector(drm, dsi);
  684. if (ret)
  685. goto err_encoder_cleanup;
  686. }
  687. return 0;
  688. err_encoder_cleanup:
  689. drm_encoder_cleanup(&dsi->encoder);
  690. return ret;
  691. }
  692. static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
  693. {
  694. drm_encoder_cleanup(&dsi->encoder);
  695. /* Skip connector cleanup if creation was delegated to the bridge */
  696. if (dsi->conn.dev)
  697. drm_connector_cleanup(&dsi->conn);
  698. }
  699. static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
  700. {
  701. struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
  702. mtk_dsi_poweron(dsi);
  703. }
  704. static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
  705. {
  706. struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
  707. mtk_dsi_poweroff(dsi);
  708. }
  709. static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
  710. .start = mtk_dsi_ddp_start,
  711. .stop = mtk_dsi_ddp_stop,
  712. };
  713. static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
  714. struct mipi_dsi_device *device)
  715. {
  716. struct mtk_dsi *dsi = host_to_dsi(host);
  717. dsi->lanes = device->lanes;
  718. dsi->format = device->format;
  719. dsi->mode_flags = device->mode_flags;
  720. if (dsi->conn.dev)
  721. drm_helper_hpd_irq_event(dsi->conn.dev);
  722. return 0;
  723. }
  724. static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
  725. struct mipi_dsi_device *device)
  726. {
  727. struct mtk_dsi *dsi = host_to_dsi(host);
  728. if (dsi->conn.dev)
  729. drm_helper_hpd_irq_event(dsi->conn.dev);
  730. return 0;
  731. }
  732. static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
  733. {
  734. int ret;
  735. u32 val;
  736. ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
  737. 4, 2000000);
  738. if (ret) {
  739. DRM_WARN("polling dsi wait not busy timeout!\n");
  740. mtk_dsi_enable(dsi);
  741. mtk_dsi_reset_engine(dsi);
  742. }
  743. }
  744. static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
  745. {
  746. switch (type) {
  747. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
  748. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
  749. return 1;
  750. case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
  751. case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
  752. return 2;
  753. case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
  754. case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
  755. return read_data[1] + read_data[2] * 16;
  756. case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
  757. DRM_INFO("type is 0x02, try again\n");
  758. break;
  759. default:
  760. DRM_INFO("type(0x%x) cannot be non-recognite\n", type);
  761. break;
  762. }
  763. return 0;
  764. }
  765. static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
  766. {
  767. const char *tx_buf = msg->tx_buf;
  768. u8 config, cmdq_size, cmdq_off, type = msg->type;
  769. u32 reg_val, cmdq_mask, i;
  770. if (MTK_DSI_HOST_IS_READ(type))
  771. config = BTA;
  772. else
  773. config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
  774. if (msg->tx_len > 2) {
  775. cmdq_size = 1 + (msg->tx_len + 3) / 4;
  776. cmdq_off = 4;
  777. cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
  778. reg_val = (msg->tx_len << 16) | (type << 8) | config;
  779. } else {
  780. cmdq_size = 1;
  781. cmdq_off = 2;
  782. cmdq_mask = CONFIG | DATA_ID;
  783. reg_val = (type << 8) | config;
  784. }
  785. for (i = 0; i < msg->tx_len; i++)
  786. writeb(tx_buf[i], dsi->regs + DSI_CMDQ0 + cmdq_off + i);
  787. mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);
  788. mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
  789. }
  790. static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
  791. const struct mipi_dsi_msg *msg, u8 flag)
  792. {
  793. mtk_dsi_wait_for_idle(dsi);
  794. mtk_dsi_irq_data_clear(dsi, flag);
  795. mtk_dsi_cmdq(dsi, msg);
  796. mtk_dsi_start(dsi);
  797. if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
  798. return -ETIME;
  799. else
  800. return 0;
  801. }
  802. static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
  803. const struct mipi_dsi_msg *msg)
  804. {
  805. struct mtk_dsi *dsi = host_to_dsi(host);
  806. u32 recv_cnt, i;
  807. u8 read_data[16];
  808. void *src_addr;
  809. u8 irq_flag = CMD_DONE_INT_FLAG;
  810. if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
  811. DRM_ERROR("dsi engine is not command mode\n");
  812. return -EINVAL;
  813. }
  814. if (MTK_DSI_HOST_IS_READ(msg->type))
  815. irq_flag |= LPRX_RD_RDY_INT_FLAG;
  816. if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
  817. return -ETIME;
  818. if (!MTK_DSI_HOST_IS_READ(msg->type))
  819. return 0;
  820. if (!msg->rx_buf) {
  821. DRM_ERROR("dsi receive buffer size may be NULL\n");
  822. return -EINVAL;
  823. }
  824. for (i = 0; i < 16; i++)
  825. *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
  826. recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
  827. if (recv_cnt > 2)
  828. src_addr = &read_data[4];
  829. else
  830. src_addr = &read_data[1];
  831. if (recv_cnt > 10)
  832. recv_cnt = 10;
  833. if (recv_cnt > msg->rx_len)
  834. recv_cnt = msg->rx_len;
  835. if (recv_cnt)
  836. memcpy(msg->rx_buf, src_addr, recv_cnt);
  837. DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
  838. recv_cnt, *((u8 *)(msg->tx_buf)));
  839. return recv_cnt;
  840. }
  841. static const struct mipi_dsi_host_ops mtk_dsi_ops = {
  842. .attach = mtk_dsi_host_attach,
  843. .detach = mtk_dsi_host_detach,
  844. .transfer = mtk_dsi_host_transfer,
  845. };
  846. static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
  847. {
  848. int ret;
  849. struct drm_device *drm = data;
  850. struct mtk_dsi *dsi = dev_get_drvdata(dev);
  851. ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
  852. if (ret < 0) {
  853. dev_err(dev, "Failed to register component %s: %d\n",
  854. dev->of_node->full_name, ret);
  855. return ret;
  856. }
  857. ret = mipi_dsi_host_register(&dsi->host);
  858. if (ret < 0) {
  859. dev_err(dev, "failed to register DSI host: %d\n", ret);
  860. goto err_ddp_comp_unregister;
  861. }
  862. ret = mtk_dsi_create_conn_enc(drm, dsi);
  863. if (ret) {
  864. DRM_ERROR("Encoder create failed with %d\n", ret);
  865. goto err_unregister;
  866. }
  867. return 0;
  868. err_unregister:
  869. mipi_dsi_host_unregister(&dsi->host);
  870. err_ddp_comp_unregister:
  871. mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
  872. return ret;
  873. }
  874. static void mtk_dsi_unbind(struct device *dev, struct device *master,
  875. void *data)
  876. {
  877. struct drm_device *drm = data;
  878. struct mtk_dsi *dsi = dev_get_drvdata(dev);
  879. mtk_dsi_destroy_conn_enc(dsi);
  880. mipi_dsi_host_unregister(&dsi->host);
  881. mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
  882. }
  883. static const struct component_ops mtk_dsi_component_ops = {
  884. .bind = mtk_dsi_bind,
  885. .unbind = mtk_dsi_unbind,
  886. };
  887. static int mtk_dsi_probe(struct platform_device *pdev)
  888. {
  889. struct mtk_dsi *dsi;
  890. struct device *dev = &pdev->dev;
  891. struct resource *regs;
  892. int irq_num;
  893. int comp_id;
  894. int ret;
  895. dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
  896. if (!dsi)
  897. return -ENOMEM;
  898. dsi->host.ops = &mtk_dsi_ops;
  899. dsi->host.dev = dev;
  900. ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
  901. &dsi->panel, &dsi->bridge);
  902. if (ret)
  903. return ret;
  904. dsi->engine_clk = devm_clk_get(dev, "engine");
  905. if (IS_ERR(dsi->engine_clk)) {
  906. ret = PTR_ERR(dsi->engine_clk);
  907. dev_err(dev, "Failed to get engine clock: %d\n", ret);
  908. return ret;
  909. }
  910. dsi->digital_clk = devm_clk_get(dev, "digital");
  911. if (IS_ERR(dsi->digital_clk)) {
  912. ret = PTR_ERR(dsi->digital_clk);
  913. dev_err(dev, "Failed to get digital clock: %d\n", ret);
  914. return ret;
  915. }
  916. dsi->hs_clk = devm_clk_get(dev, "hs");
  917. if (IS_ERR(dsi->hs_clk)) {
  918. ret = PTR_ERR(dsi->hs_clk);
  919. dev_err(dev, "Failed to get hs clock: %d\n", ret);
  920. return ret;
  921. }
  922. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  923. dsi->regs = devm_ioremap_resource(dev, regs);
  924. if (IS_ERR(dsi->regs)) {
  925. ret = PTR_ERR(dsi->regs);
  926. dev_err(dev, "Failed to ioremap memory: %d\n", ret);
  927. return ret;
  928. }
  929. dsi->phy = devm_phy_get(dev, "dphy");
  930. if (IS_ERR(dsi->phy)) {
  931. ret = PTR_ERR(dsi->phy);
  932. dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
  933. return ret;
  934. }
  935. comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
  936. if (comp_id < 0) {
  937. dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
  938. return comp_id;
  939. }
  940. ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
  941. &mtk_dsi_funcs);
  942. if (ret) {
  943. dev_err(dev, "Failed to initialize component: %d\n", ret);
  944. return ret;
  945. }
  946. irq_num = platform_get_irq(pdev, 0);
  947. if (irq_num < 0) {
  948. dev_err(&pdev->dev, "failed to request dsi irq resource\n");
  949. return -EPROBE_DEFER;
  950. }
  951. irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
  952. ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
  953. IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
  954. if (ret) {
  955. dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
  956. return -EPROBE_DEFER;
  957. }
  958. init_waitqueue_head(&dsi->irq_wait_queue);
  959. platform_set_drvdata(pdev, dsi);
  960. return component_add(&pdev->dev, &mtk_dsi_component_ops);
  961. }
  962. static int mtk_dsi_remove(struct platform_device *pdev)
  963. {
  964. struct mtk_dsi *dsi = platform_get_drvdata(pdev);
  965. mtk_output_dsi_disable(dsi);
  966. component_del(&pdev->dev, &mtk_dsi_component_ops);
  967. return 0;
  968. }
  969. static const struct of_device_id mtk_dsi_of_match[] = {
  970. { .compatible = "mediatek,mt2701-dsi" },
  971. { .compatible = "mediatek,mt8173-dsi" },
  972. { },
  973. };
  974. struct platform_driver mtk_dsi_driver = {
  975. .probe = mtk_dsi_probe,
  976. .remove = mtk_dsi_remove,
  977. .driver = {
  978. .name = "mtk-dsi",
  979. .of_match_table = mtk_dsi_of_match,
  980. },
  981. };