smumgr.h 11 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef _SMUMGR_H_
  24. #define _SMUMGR_H_
  25. #include <linux/types.h>
  26. #include "pp_instance.h"
  27. #include "amd_powerplay.h"
  28. struct pp_smumgr;
  29. struct pp_instance;
  30. struct pp_hwmgr;
  31. #define smu_lower_32_bits(n) ((uint32_t)(n))
  32. #define smu_upper_32_bits(n) ((uint32_t)(((n)>>16)>>16))
  33. extern const struct pp_smumgr_func cz_smu_funcs;
  34. extern const struct pp_smumgr_func iceland_smu_funcs;
  35. extern const struct pp_smumgr_func tonga_smu_funcs;
  36. extern const struct pp_smumgr_func fiji_smu_funcs;
  37. extern const struct pp_smumgr_func polaris10_smu_funcs;
  38. extern const struct pp_smumgr_func vega10_smu_funcs;
  39. enum AVFS_BTC_STATUS {
  40. AVFS_BTC_BOOT = 0,
  41. AVFS_BTC_BOOT_STARTEDSMU,
  42. AVFS_LOAD_VIRUS,
  43. AVFS_BTC_VIRUS_LOADED,
  44. AVFS_BTC_VIRUS_FAIL,
  45. AVFS_BTC_COMPLETED_PREVIOUSLY,
  46. AVFS_BTC_ENABLEAVFS,
  47. AVFS_BTC_STARTED,
  48. AVFS_BTC_FAILED,
  49. AVFS_BTC_RESTOREVFT_FAILED,
  50. AVFS_BTC_SAVEVFT_FAILED,
  51. AVFS_BTC_DPMTABLESETUP_FAILED,
  52. AVFS_BTC_COMPLETED_UNSAVED,
  53. AVFS_BTC_COMPLETED_SAVED,
  54. AVFS_BTC_COMPLETED_RESTORED,
  55. AVFS_BTC_DISABLED,
  56. AVFS_BTC_NOTSUPPORTED,
  57. AVFS_BTC_SMUMSG_ERROR
  58. };
  59. enum SMU_TABLE {
  60. SMU_UVD_TABLE = 0,
  61. SMU_VCE_TABLE,
  62. SMU_SAMU_TABLE,
  63. SMU_BIF_TABLE,
  64. };
  65. enum SMU_TYPE {
  66. SMU_SoftRegisters = 0,
  67. SMU_Discrete_DpmTable,
  68. };
  69. enum SMU_MEMBER {
  70. HandshakeDisables = 0,
  71. VoltageChangeTimeout,
  72. AverageGraphicsActivity,
  73. PreVBlankGap,
  74. VBlankTimeout,
  75. UcodeLoadStatus,
  76. UvdBootLevel,
  77. VceBootLevel,
  78. SamuBootLevel,
  79. LowSclkInterruptThreshold,
  80. };
  81. enum SMU_MAC_DEFINITION {
  82. SMU_MAX_LEVELS_GRAPHICS = 0,
  83. SMU_MAX_LEVELS_MEMORY,
  84. SMU_MAX_LEVELS_LINK,
  85. SMU_MAX_ENTRIES_SMIO,
  86. SMU_MAX_LEVELS_VDDC,
  87. SMU_MAX_LEVELS_VDDGFX,
  88. SMU_MAX_LEVELS_VDDCI,
  89. SMU_MAX_LEVELS_MVDD,
  90. SMU_UVD_MCLK_HANDSHAKE_DISABLE,
  91. };
  92. struct pp_smumgr_func {
  93. int (*smu_init)(struct pp_smumgr *smumgr);
  94. int (*smu_fini)(struct pp_smumgr *smumgr);
  95. int (*start_smu)(struct pp_smumgr *smumgr);
  96. int (*check_fw_load_finish)(struct pp_smumgr *smumgr,
  97. uint32_t firmware);
  98. int (*request_smu_load_fw)(struct pp_smumgr *smumgr);
  99. int (*request_smu_load_specific_fw)(struct pp_smumgr *smumgr,
  100. uint32_t firmware);
  101. int (*get_argument)(struct pp_smumgr *smumgr);
  102. int (*send_msg_to_smc)(struct pp_smumgr *smumgr, uint16_t msg);
  103. int (*send_msg_to_smc_with_parameter)(struct pp_smumgr *smumgr,
  104. uint16_t msg, uint32_t parameter);
  105. int (*download_pptable_settings)(struct pp_smumgr *smumgr,
  106. void **table);
  107. int (*upload_pptable_settings)(struct pp_smumgr *smumgr);
  108. int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
  109. int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
  110. int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
  111. int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
  112. int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
  113. int (*init_smc_table)(struct pp_hwmgr *hwmgr);
  114. int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
  115. int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
  116. int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
  117. uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
  118. uint32_t (*get_mac_definition)(uint32_t value);
  119. bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
  120. int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
  121. struct amd_pp_profile *request);
  122. };
  123. struct pp_smumgr {
  124. uint32_t chip_family;
  125. uint32_t chip_id;
  126. void *device;
  127. void *backend;
  128. uint32_t usec_timeout;
  129. bool reload_fw;
  130. const struct pp_smumgr_func *smumgr_funcs;
  131. bool is_kicker;
  132. };
  133. extern int smum_early_init(struct pp_instance *handle);
  134. extern int smum_get_argument(struct pp_smumgr *smumgr);
  135. extern int smum_download_powerplay_table(struct pp_smumgr *smumgr, void **table);
  136. extern int smum_upload_powerplay_table(struct pp_smumgr *smumgr);
  137. extern int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg);
  138. extern int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
  139. uint16_t msg, uint32_t parameter);
  140. extern int smum_wait_on_register(struct pp_smumgr *smumgr,
  141. uint32_t index, uint32_t value, uint32_t mask);
  142. extern int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
  143. uint32_t index, uint32_t value, uint32_t mask);
  144. extern int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
  145. uint32_t indirect_port, uint32_t index,
  146. uint32_t value, uint32_t mask);
  147. extern void smum_wait_for_indirect_register_unequal(
  148. struct pp_smumgr *smumgr,
  149. uint32_t indirect_port, uint32_t index,
  150. uint32_t value, uint32_t mask);
  151. extern int smu_allocate_memory(void *device, uint32_t size,
  152. enum cgs_gpu_mem_type type,
  153. uint32_t byte_align, uint64_t *mc_addr,
  154. void **kptr, void *handle);
  155. extern int smu_free_memory(void *device, void *handle);
  156. extern int vega10_smum_init(struct pp_smumgr *smumgr);
  157. extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
  158. extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
  159. extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
  160. extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
  161. void *input, void *output, void *storage, int result);
  162. extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
  163. void *input, void *output, void *storage, int result);
  164. extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
  165. extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
  166. extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
  167. extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
  168. extern uint32_t smum_get_offsetof(struct pp_smumgr *smumgr,
  169. uint32_t type, uint32_t member);
  170. extern uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value);
  171. extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
  172. extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
  173. struct amd_pp_profile *request);
  174. #define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
  175. #define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
  176. #define SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
  177. port, index, value, mask) \
  178. smum_wait_on_indirect_register(smumgr, \
  179. mm##port##_INDEX, index, value, mask)
  180. #define SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
  181. SMUM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
  182. #define SMUM_WAIT_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
  183. SMUM_WAIT_INDIRECT_REGISTER(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
  184. SMUM_FIELD_MASK(reg, field) )
  185. #define SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
  186. index, value, mask) \
  187. smum_wait_for_register_unequal(smumgr, \
  188. index, value, mask)
  189. #define SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, value, mask) \
  190. SMUM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
  191. mm##reg, value, mask)
  192. #define SMUM_WAIT_FIELD_UNEQUAL(smumgr, reg, field, fieldval) \
  193. SMUM_WAIT_REGISTER_UNEQUAL(smumgr, reg, \
  194. (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
  195. SMUM_FIELD_MASK(reg, field))
  196. #define SMUM_GET_FIELD(value, reg, field) \
  197. (((value) & SMUM_FIELD_MASK(reg, field)) \
  198. >> SMUM_FIELD_SHIFT(reg, field))
  199. #define SMUM_READ_FIELD(device, reg, field) \
  200. SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)
  201. #define SMUM_SET_FIELD(value, reg, field, field_val) \
  202. (((value) & ~SMUM_FIELD_MASK(reg, field)) | \
  203. (SMUM_FIELD_MASK(reg, field) & ((field_val) << \
  204. SMUM_FIELD_SHIFT(reg, field))))
  205. #define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
  206. SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
  207. reg, field)
  208. #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, \
  209. port, index, value, mask) \
  210. smum_wait_on_indirect_register(smumgr, \
  211. mm##port##_INDEX_0, index, value, mask)
  212. #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, \
  213. port, index, value, mask) \
  214. smum_wait_for_indirect_register_unequal(smumgr, \
  215. mm##port##_INDEX_0, index, value, mask)
  216. #define SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, value, mask) \
  217. SMUM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
  218. #define SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
  219. SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
  220. /*Operations on named fields.*/
  221. #define SMUM_READ_VFPF_INDIRECT_FIELD(device, port, reg, field) \
  222. SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
  223. reg, field)
  224. #define SMUM_WRITE_FIELD(device, reg, field, fieldval) \
  225. cgs_write_register(device, mm##reg, \
  226. SMUM_SET_FIELD(cgs_read_register(device, mm##reg), reg, field, fieldval))
  227. #define SMUM_WRITE_VFPF_INDIRECT_FIELD(device, port, reg, field, fieldval) \
  228. cgs_write_ind_register(device, port, ix##reg, \
  229. SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
  230. reg, field, fieldval))
  231. #define SMUM_WRITE_INDIRECT_FIELD(device, port, reg, field, fieldval) \
  232. cgs_write_ind_register(device, port, ix##reg, \
  233. SMUM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
  234. reg, field, fieldval))
  235. #define SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, port, reg, field, fieldval) \
  236. SMUM_WAIT_VFPF_INDIRECT_REGISTER(smumgr, port, reg, \
  237. (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
  238. SMUM_FIELD_MASK(reg, field))
  239. #define SMUM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
  240. SMUM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, \
  241. (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
  242. SMUM_FIELD_MASK(reg, field))
  243. #define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, index, value, mask) \
  244. smum_wait_for_indirect_register_unequal(smumgr, \
  245. mm##port##_INDEX, index, value, mask)
  246. #define SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, value, mask) \
  247. SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(smumgr, port, ix##reg, value, mask)
  248. #define SMUM_WAIT_INDIRECT_FIELD_UNEQUAL(smumgr, port, reg, field, fieldval) \
  249. SMUM_WAIT_INDIRECT_REGISTER_UNEQUAL(smumgr, port, reg, (fieldval) << SMUM_FIELD_SHIFT(reg, field), \
  250. SMUM_FIELD_MASK(reg, field) )
  251. #endif