amd_powerplay.h 14 KB

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  1. /*
  2. * Copyright 2015 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef _AMD_POWERPLAY_H_
  24. #define _AMD_POWERPLAY_H_
  25. #include <linux/seq_file.h>
  26. #include <linux/types.h>
  27. #include <linux/errno.h>
  28. #include "amd_shared.h"
  29. #include "cgs_common.h"
  30. #include "dm_pp_interface.h"
  31. extern const struct amd_ip_funcs pp_ip_funcs;
  32. extern const struct amd_powerplay_funcs pp_dpm_funcs;
  33. #define PP_DPM_DISABLED 0xCCCC
  34. enum amd_pp_sensors {
  35. AMDGPU_PP_SENSOR_GFX_SCLK = 0,
  36. AMDGPU_PP_SENSOR_VDDNB,
  37. AMDGPU_PP_SENSOR_VDDGFX,
  38. AMDGPU_PP_SENSOR_UVD_VCLK,
  39. AMDGPU_PP_SENSOR_UVD_DCLK,
  40. AMDGPU_PP_SENSOR_VCE_ECCLK,
  41. AMDGPU_PP_SENSOR_GPU_LOAD,
  42. AMDGPU_PP_SENSOR_GFX_MCLK,
  43. AMDGPU_PP_SENSOR_GPU_TEMP,
  44. AMDGPU_PP_SENSOR_VCE_POWER,
  45. AMDGPU_PP_SENSOR_UVD_POWER,
  46. AMDGPU_PP_SENSOR_GPU_POWER,
  47. };
  48. enum amd_pp_event {
  49. AMD_PP_EVENT_INITIALIZE = 0,
  50. AMD_PP_EVENT_UNINITIALIZE,
  51. AMD_PP_EVENT_POWER_SOURCE_CHANGE,
  52. AMD_PP_EVENT_SUSPEND,
  53. AMD_PP_EVENT_RESUME,
  54. AMD_PP_EVENT_ENTER_REST_STATE,
  55. AMD_PP_EVENT_EXIT_REST_STATE,
  56. AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
  57. AMD_PP_EVENT_THERMAL_NOTIFICATION,
  58. AMD_PP_EVENT_VBIOS_NOTIFICATION,
  59. AMD_PP_EVENT_ENTER_THERMAL_STATE,
  60. AMD_PP_EVENT_EXIT_THERMAL_STATE,
  61. AMD_PP_EVENT_ENTER_FORCED_STATE,
  62. AMD_PP_EVENT_EXIT_FORCED_STATE,
  63. AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
  64. AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
  65. AMD_PP_EVENT_ENTER_SCREEN_SAVER,
  66. AMD_PP_EVENT_EXIT_SCREEN_SAVER,
  67. AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
  68. AMD_PP_EVENT_VPU_RECOVERY_END,
  69. AMD_PP_EVENT_ENABLE_POWER_PLAY,
  70. AMD_PP_EVENT_DISABLE_POWER_PLAY,
  71. AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
  72. AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
  73. AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
  74. AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
  75. AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
  76. AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
  77. AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
  78. AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
  79. AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
  80. AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
  81. AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
  82. AMD_PP_EVENT_ENABLE_CGPG,
  83. AMD_PP_EVENT_DISABLE_CGPG,
  84. AMD_PP_EVENT_ENTER_TEXT_MODE,
  85. AMD_PP_EVENT_EXIT_TEXT_MODE,
  86. AMD_PP_EVENT_VIDEO_START,
  87. AMD_PP_EVENT_VIDEO_STOP,
  88. AMD_PP_EVENT_ENABLE_USER_STATE,
  89. AMD_PP_EVENT_DISABLE_USER_STATE,
  90. AMD_PP_EVENT_READJUST_POWER_STATE,
  91. AMD_PP_EVENT_START_INACTIVITY,
  92. AMD_PP_EVENT_STOP_INACTIVITY,
  93. AMD_PP_EVENT_LINKED_ADAPTERS_READY,
  94. AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
  95. AMD_PP_EVENT_COMPLETE_INIT,
  96. AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
  97. AMD_PP_EVENT_BACKLIGHT_CHANGED,
  98. AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
  99. AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
  100. AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
  101. AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
  102. AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
  103. AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
  104. AMD_PP_EVENT_SCREEN_ON,
  105. AMD_PP_EVENT_SCREEN_OFF,
  106. AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
  107. AMD_PP_EVENT_ENTER_ULP_STATE,
  108. AMD_PP_EVENT_EXIT_ULP_STATE,
  109. AMD_PP_EVENT_REGISTER_IP_STATE,
  110. AMD_PP_EVENT_UNREGISTER_IP_STATE,
  111. AMD_PP_EVENT_ENTER_MGPU_MODE,
  112. AMD_PP_EVENT_EXIT_MGPU_MODE,
  113. AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
  114. AMD_PP_EVENT_PRE_SUSPEND,
  115. AMD_PP_EVENT_PRE_RESUME,
  116. AMD_PP_EVENT_ENTER_BACOS,
  117. AMD_PP_EVENT_EXIT_BACOS,
  118. AMD_PP_EVENT_RESUME_BACO,
  119. AMD_PP_EVENT_RESET_BACO,
  120. AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
  121. AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
  122. AMD_PP_EVENT_START_COMPUTE_APPLICATION,
  123. AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
  124. AMD_PP_EVENT_REDUCE_POWER_LIMIT,
  125. AMD_PP_EVENT_ENTER_FRAME_LOCK,
  126. AMD_PP_EVENT_EXIT_FRAME_LOOCK,
  127. AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
  128. AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
  129. AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
  130. AMD_PP_EVENT_HIBERNATE,
  131. AMD_PP_EVENT_CONNECTED_STANDBY,
  132. AMD_PP_EVENT_ENTER_SELF_REFRESH,
  133. AMD_PP_EVENT_EXIT_SELF_REFRESH,
  134. AMD_PP_EVENT_START_AVFS_BTC,
  135. AMD_PP_EVENT_MAX
  136. };
  137. struct amd_pp_init {
  138. struct cgs_device *device;
  139. uint32_t chip_family;
  140. uint32_t chip_id;
  141. bool pm_en;
  142. uint32_t feature_mask;
  143. };
  144. enum amd_pp_display_config_type{
  145. AMD_PP_DisplayConfigType_None = 0,
  146. AMD_PP_DisplayConfigType_DP54 ,
  147. AMD_PP_DisplayConfigType_DP432 ,
  148. AMD_PP_DisplayConfigType_DP324 ,
  149. AMD_PP_DisplayConfigType_DP27,
  150. AMD_PP_DisplayConfigType_DP243,
  151. AMD_PP_DisplayConfigType_DP216,
  152. AMD_PP_DisplayConfigType_DP162,
  153. AMD_PP_DisplayConfigType_HDMI6G ,
  154. AMD_PP_DisplayConfigType_HDMI297 ,
  155. AMD_PP_DisplayConfigType_HDMI162,
  156. AMD_PP_DisplayConfigType_LVDS,
  157. AMD_PP_DisplayConfigType_DVI,
  158. AMD_PP_DisplayConfigType_WIRELESS,
  159. AMD_PP_DisplayConfigType_VGA
  160. };
  161. struct single_display_configuration
  162. {
  163. uint32_t controller_index;
  164. uint32_t controller_id;
  165. uint32_t signal_type;
  166. uint32_t display_state;
  167. /* phy id for the primary internal transmitter */
  168. uint8_t primary_transmitter_phyi_d;
  169. /* bitmap with the active lanes */
  170. uint8_t primary_transmitter_active_lanemap;
  171. /* phy id for the secondary internal transmitter (for dual-link dvi) */
  172. uint8_t secondary_transmitter_phy_id;
  173. /* bitmap with the active lanes */
  174. uint8_t secondary_transmitter_active_lanemap;
  175. /* misc phy settings for SMU. */
  176. uint32_t config_flags;
  177. uint32_t display_type;
  178. uint32_t view_resolution_cx;
  179. uint32_t view_resolution_cy;
  180. enum amd_pp_display_config_type displayconfigtype;
  181. uint32_t vertical_refresh; /* for active display */
  182. };
  183. #define MAX_NUM_DISPLAY 32
  184. struct amd_pp_display_configuration {
  185. bool nb_pstate_switch_disable;/* controls NB PState switch */
  186. bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
  187. bool cpu_pstate_disable;
  188. uint32_t cpu_pstate_separation_time;
  189. uint32_t num_display; /* total number of display*/
  190. uint32_t num_path_including_non_display;
  191. uint32_t crossfire_display_index;
  192. uint32_t min_mem_set_clock;
  193. uint32_t min_core_set_clock;
  194. /* unit 10KHz x bit*/
  195. uint32_t min_bus_bandwidth;
  196. /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
  197. uint32_t min_core_set_clock_in_sr;
  198. struct single_display_configuration displays[MAX_NUM_DISPLAY];
  199. uint32_t vrefresh; /* for active display*/
  200. uint32_t min_vblank_time; /* for active display*/
  201. bool multi_monitor_in_sync;
  202. /* Controller Index of primary display - used in MCLK SMC switching hang
  203. * SW Workaround*/
  204. uint32_t crtc_index;
  205. /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
  206. uint32_t line_time_in_us;
  207. bool invalid_vblank_time;
  208. uint32_t display_clk;
  209. /*
  210. * for given display configuration if multimonitormnsync == false then
  211. * Memory clock DPMS with this latency or below is allowed, DPMS with
  212. * higher latency not allowed.
  213. */
  214. uint32_t dce_tolerable_mclk_in_active_latency;
  215. uint32_t min_dcef_set_clk;
  216. uint32_t min_dcef_deep_sleep_set_clk;
  217. };
  218. struct amd_pp_simple_clock_info {
  219. uint32_t engine_max_clock;
  220. uint32_t memory_max_clock;
  221. uint32_t level;
  222. };
  223. enum PP_DAL_POWERLEVEL {
  224. PP_DAL_POWERLEVEL_INVALID = 0,
  225. PP_DAL_POWERLEVEL_ULTRALOW,
  226. PP_DAL_POWERLEVEL_LOW,
  227. PP_DAL_POWERLEVEL_NOMINAL,
  228. PP_DAL_POWERLEVEL_PERFORMANCE,
  229. PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
  230. PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
  231. PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
  232. PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
  233. PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
  234. PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
  235. PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
  236. PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
  237. };
  238. struct amd_pp_clock_info {
  239. uint32_t min_engine_clock;
  240. uint32_t max_engine_clock;
  241. uint32_t min_memory_clock;
  242. uint32_t max_memory_clock;
  243. uint32_t min_bus_bandwidth;
  244. uint32_t max_bus_bandwidth;
  245. uint32_t max_engine_clock_in_sr;
  246. uint32_t min_engine_clock_in_sr;
  247. enum PP_DAL_POWERLEVEL max_clocks_state;
  248. };
  249. enum amd_pp_clock_type {
  250. amd_pp_disp_clock = 1,
  251. amd_pp_sys_clock,
  252. amd_pp_mem_clock,
  253. amd_pp_dcef_clock,
  254. amd_pp_soc_clock,
  255. amd_pp_pixel_clock,
  256. amd_pp_phy_clock
  257. };
  258. #define MAX_NUM_CLOCKS 16
  259. struct amd_pp_clocks {
  260. uint32_t count;
  261. uint32_t clock[MAX_NUM_CLOCKS];
  262. uint32_t latency[MAX_NUM_CLOCKS];
  263. };
  264. enum {
  265. PP_GROUP_UNKNOWN = 0,
  266. PP_GROUP_GFX = 1,
  267. PP_GROUP_SYS,
  268. PP_GROUP_MAX
  269. };
  270. enum pp_clock_type {
  271. PP_SCLK,
  272. PP_MCLK,
  273. PP_PCIE,
  274. };
  275. struct pp_states_info {
  276. uint32_t nums;
  277. uint32_t states[16];
  278. };
  279. struct pp_gpu_power {
  280. uint32_t vddc_power;
  281. uint32_t vddci_power;
  282. uint32_t max_gpu_power;
  283. uint32_t average_gpu_power;
  284. };
  285. struct pp_display_clock_request {
  286. enum amd_pp_clock_type clock_type;
  287. uint32_t clock_freq_in_khz;
  288. };
  289. #define PP_GROUP_MASK 0xF0000000
  290. #define PP_GROUP_SHIFT 28
  291. #define PP_BLOCK_MASK 0x0FFFFF00
  292. #define PP_BLOCK_SHIFT 8
  293. #define PP_BLOCK_GFX_CG 0x01
  294. #define PP_BLOCK_GFX_MG 0x02
  295. #define PP_BLOCK_GFX_3D 0x04
  296. #define PP_BLOCK_GFX_RLC 0x08
  297. #define PP_BLOCK_GFX_CP 0x10
  298. #define PP_BLOCK_SYS_BIF 0x01
  299. #define PP_BLOCK_SYS_MC 0x02
  300. #define PP_BLOCK_SYS_ROM 0x04
  301. #define PP_BLOCK_SYS_DRM 0x08
  302. #define PP_BLOCK_SYS_HDP 0x10
  303. #define PP_BLOCK_SYS_SDMA 0x20
  304. #define PP_STATE_MASK 0x0000000F
  305. #define PP_STATE_SHIFT 0
  306. #define PP_STATE_SUPPORT_MASK 0x000000F0
  307. #define PP_STATE_SUPPORT_SHIFT 0
  308. #define PP_STATE_CG 0x01
  309. #define PP_STATE_LS 0x02
  310. #define PP_STATE_DS 0x04
  311. #define PP_STATE_SD 0x08
  312. #define PP_STATE_SUPPORT_CG 0x10
  313. #define PP_STATE_SUPPORT_LS 0x20
  314. #define PP_STATE_SUPPORT_DS 0x40
  315. #define PP_STATE_SUPPORT_SD 0x80
  316. #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
  317. block << PP_BLOCK_SHIFT |\
  318. support << PP_STATE_SUPPORT_SHIFT |\
  319. state << PP_STATE_SHIFT)
  320. struct amd_powerplay_funcs {
  321. int (*get_temperature)(void *handle);
  322. int (*load_firmware)(void *handle);
  323. int (*wait_for_fw_loading_complete)(void *handle);
  324. int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
  325. enum amd_dpm_forced_level (*get_performance_level)(void *handle);
  326. enum amd_pm_state_type (*get_current_power_state)(void *handle);
  327. int (*get_sclk)(void *handle, bool low);
  328. int (*get_mclk)(void *handle, bool low);
  329. int (*powergate_vce)(void *handle, bool gate);
  330. int (*powergate_uvd)(void *handle, bool gate);
  331. int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
  332. void *input, void *output);
  333. int (*set_fan_control_mode)(void *handle, uint32_t mode);
  334. int (*get_fan_control_mode)(void *handle);
  335. int (*set_fan_speed_percent)(void *handle, uint32_t percent);
  336. int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
  337. int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
  338. int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
  339. int (*get_pp_table)(void *handle, char **table);
  340. int (*set_pp_table)(void *handle, const char *buf, size_t size);
  341. int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
  342. int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
  343. int (*get_sclk_od)(void *handle);
  344. int (*set_sclk_od)(void *handle, uint32_t value);
  345. int (*get_mclk_od)(void *handle);
  346. int (*set_mclk_od)(void *handle, uint32_t value);
  347. int (*read_sensor)(void *handle, int idx, void *value, int *size);
  348. struct amd_vce_state* (*get_vce_clock_state)(void *handle, unsigned idx);
  349. int (*reset_power_profile_state)(void *handle,
  350. struct amd_pp_profile *request);
  351. int (*get_power_profile_state)(void *handle,
  352. struct amd_pp_profile *query);
  353. int (*set_power_profile_state)(void *handle,
  354. struct amd_pp_profile *request);
  355. int (*switch_power_profile)(void *handle,
  356. enum amd_pp_profile_type type);
  357. };
  358. struct amd_powerplay {
  359. void *pp_handle;
  360. const struct amd_ip_funcs *ip_funcs;
  361. const struct amd_powerplay_funcs *pp_funcs;
  362. };
  363. int amd_powerplay_create(struct amd_pp_init *pp_init,
  364. void **handle);
  365. int amd_powerplay_destroy(void *handle);
  366. int amd_powerplay_reset(void *handle);
  367. int amd_powerplay_display_configuration_change(void *handle,
  368. const struct amd_pp_display_configuration *input);
  369. int amd_powerplay_get_display_power_level(void *handle,
  370. struct amd_pp_simple_clock_info *output);
  371. int amd_powerplay_get_current_clocks(void *handle,
  372. struct amd_pp_clock_info *output);
  373. int amd_powerplay_get_clock_by_type(void *handle,
  374. enum amd_pp_clock_type type,
  375. struct amd_pp_clocks *clocks);
  376. int amd_powerplay_get_clock_by_type_with_latency(void *handle,
  377. enum amd_pp_clock_type type,
  378. struct pp_clock_levels_with_latency *clocks);
  379. int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
  380. enum amd_pp_clock_type type,
  381. struct pp_clock_levels_with_voltage *clocks);
  382. int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
  383. struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
  384. int amd_powerplay_display_clock_voltage_request(void *handle,
  385. struct pp_display_clock_request *clock);
  386. int amd_powerplay_get_display_mode_validation_clocks(void *handle,
  387. struct amd_pp_simple_clock_info *output);
  388. int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id);
  389. #endif /* _AMD_POWERPLAY_H_ */