clk-tegra-audio.c 6.8 KB

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  1. /*
  2. * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/io.h>
  17. #include <linux/clk-provider.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include <linux/delay.h>
  21. #include <linux/export.h>
  22. #include <linux/clk/tegra.h>
  23. #include "clk.h"
  24. #include "clk-id.h"
  25. #define AUDIO_SYNC_CLK_I2S0 0x4a0
  26. #define AUDIO_SYNC_CLK_I2S1 0x4a4
  27. #define AUDIO_SYNC_CLK_I2S2 0x4a8
  28. #define AUDIO_SYNC_CLK_I2S3 0x4ac
  29. #define AUDIO_SYNC_CLK_I2S4 0x4b0
  30. #define AUDIO_SYNC_CLK_SPDIF 0x4b4
  31. #define AUDIO_SYNC_CLK_DMIC1 0x560
  32. #define AUDIO_SYNC_CLK_DMIC2 0x564
  33. #define AUDIO_SYNC_CLK_DMIC3 0x6b8
  34. #define AUDIO_SYNC_DOUBLER 0x49c
  35. #define PLLA_OUT 0xb4
  36. struct tegra_sync_source_initdata {
  37. char *name;
  38. unsigned long rate;
  39. unsigned long max_rate;
  40. int clk_id;
  41. };
  42. #define SYNC(_name) \
  43. {\
  44. .name = #_name,\
  45. .rate = 24000000,\
  46. .max_rate = 24000000,\
  47. .clk_id = tegra_clk_ ## _name,\
  48. }
  49. struct tegra_audio_clk_initdata {
  50. char *gate_name;
  51. char *mux_name;
  52. u32 offset;
  53. int gate_clk_id;
  54. int mux_clk_id;
  55. };
  56. #define AUDIO(_name, _offset) \
  57. {\
  58. .gate_name = #_name,\
  59. .mux_name = #_name"_mux",\
  60. .offset = _offset,\
  61. .gate_clk_id = tegra_clk_ ## _name,\
  62. .mux_clk_id = tegra_clk_ ## _name ## _mux,\
  63. }
  64. struct tegra_audio2x_clk_initdata {
  65. char *parent;
  66. char *gate_name;
  67. char *name_2x;
  68. char *div_name;
  69. int clk_id;
  70. int clk_num;
  71. u8 div_offset;
  72. };
  73. #define AUDIO2X(_name, _num, _offset) \
  74. {\
  75. .parent = #_name,\
  76. .gate_name = #_name"_2x",\
  77. .name_2x = #_name"_doubler",\
  78. .div_name = #_name"_div",\
  79. .clk_id = tegra_clk_ ## _name ## _2x,\
  80. .clk_num = _num,\
  81. .div_offset = _offset,\
  82. }
  83. static DEFINE_SPINLOCK(clk_doubler_lock);
  84. static const char * const mux_audio_sync_clk[] = { "spdif_in_sync",
  85. "i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync",
  86. "pll_a_out0", "vimclk_sync",
  87. };
  88. static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync",
  89. "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
  90. "vimclk_sync",
  91. };
  92. static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
  93. SYNC(spdif_in_sync),
  94. SYNC(i2s0_sync),
  95. SYNC(i2s1_sync),
  96. SYNC(i2s2_sync),
  97. SYNC(i2s3_sync),
  98. SYNC(i2s4_sync),
  99. SYNC(vimclk_sync),
  100. };
  101. static struct tegra_audio_clk_initdata audio_clks[] = {
  102. AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
  103. AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
  104. AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
  105. AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
  106. AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
  107. AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
  108. };
  109. static struct tegra_audio_clk_initdata dmic_clks[] = {
  110. AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1),
  111. AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2),
  112. AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3),
  113. };
  114. static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
  115. AUDIO2X(audio0, 113, 24),
  116. AUDIO2X(audio1, 114, 25),
  117. AUDIO2X(audio2, 115, 26),
  118. AUDIO2X(audio3, 116, 27),
  119. AUDIO2X(audio4, 117, 28),
  120. AUDIO2X(spdif, 118, 29),
  121. };
  122. static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
  123. struct tegra_clk *tegra_clks,
  124. struct tegra_audio_clk_initdata *sync,
  125. int num_sync_clks,
  126. const char * const *mux_names,
  127. int num_mux_inputs)
  128. {
  129. struct clk *clk;
  130. struct clk **dt_clk;
  131. struct tegra_audio_clk_initdata *data;
  132. int i;
  133. for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
  134. dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
  135. if (!dt_clk)
  136. continue;
  137. clk = clk_register_mux(NULL, data->mux_name, mux_names,
  138. num_mux_inputs,
  139. CLK_SET_RATE_NO_REPARENT,
  140. clk_base + data->offset, 0, 3, 0,
  141. NULL);
  142. *dt_clk = clk;
  143. dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
  144. if (!dt_clk)
  145. continue;
  146. clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
  147. 0, clk_base + data->offset, 4,
  148. CLK_GATE_SET_TO_DISABLE, NULL);
  149. *dt_clk = clk;
  150. }
  151. }
  152. void __init tegra_audio_clk_init(void __iomem *clk_base,
  153. void __iomem *pmc_base, struct tegra_clk *tegra_clks,
  154. struct tegra_audio_clk_info *audio_info,
  155. unsigned int num_plls)
  156. {
  157. struct clk *clk;
  158. struct clk **dt_clk;
  159. int i;
  160. if (!audio_info || num_plls < 1) {
  161. pr_err("No audio data passed to tegra_audio_clk_init\n");
  162. WARN_ON(1);
  163. return;
  164. }
  165. for (i = 0; i < num_plls; i++) {
  166. struct tegra_audio_clk_info *info = &audio_info[i];
  167. dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);
  168. if (dt_clk) {
  169. clk = tegra_clk_register_pll(info->name, info->parent,
  170. clk_base, pmc_base, 0, info->pll_params,
  171. NULL);
  172. *dt_clk = clk;
  173. }
  174. }
  175. /* PLLA_OUT0 */
  176. dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
  177. if (dt_clk) {
  178. clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
  179. clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
  180. 8, 8, 1, NULL);
  181. clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
  182. clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
  183. CLK_SET_RATE_PARENT, 0, NULL);
  184. *dt_clk = clk;
  185. }
  186. for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
  187. struct tegra_sync_source_initdata *data;
  188. data = &sync_source_clks[i];
  189. dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
  190. if (!dt_clk)
  191. continue;
  192. clk = tegra_clk_register_sync_source(data->name,
  193. data->rate, data->max_rate);
  194. *dt_clk = clk;
  195. }
  196. tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
  197. ARRAY_SIZE(audio_clks), mux_audio_sync_clk,
  198. ARRAY_SIZE(mux_audio_sync_clk));
  199. /* make sure the DMIC sync clocks have a valid parent */
  200. for (i = 0; i < ARRAY_SIZE(dmic_clks); i++)
  201. writel_relaxed(1, clk_base + dmic_clks[i].offset);
  202. tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks,
  203. ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk,
  204. ARRAY_SIZE(mux_dmic_sync_clk));
  205. for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
  206. struct tegra_audio2x_clk_initdata *data;
  207. data = &audio2x_clks[i];
  208. dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
  209. if (!dt_clk)
  210. continue;
  211. clk = clk_register_fixed_factor(NULL, data->name_2x,
  212. data->parent, CLK_SET_RATE_PARENT, 2, 1);
  213. clk = tegra_clk_register_divider(data->div_name,
  214. data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
  215. 0, 0, data->div_offset, 1, 0,
  216. &clk_doubler_lock);
  217. clk = tegra_clk_register_periph_gate(data->gate_name,
  218. data->div_name, TEGRA_PERIPH_NO_RESET,
  219. clk_base, CLK_SET_RATE_PARENT, data->clk_num,
  220. periph_clk_enb_refcnt);
  221. *dt_clk = clk;
  222. }
  223. }