chip.c 27 KB

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  1. /*
  2. * linux/kernel/irq/chip.c
  3. *
  4. * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  5. * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
  6. *
  7. * This file contains the core interrupt handling code, for irq-chip
  8. * based architectures.
  9. *
  10. * Detailed information is available in Documentation/DocBook/genericirq
  11. */
  12. #include <linux/irq.h>
  13. #include <linux/msi.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel_stat.h>
  17. #include <linux/irqdomain.h>
  18. #include <trace/events/irq.h>
  19. #include "internals.h"
  20. /**
  21. * irq_set_chip - set the irq chip for an irq
  22. * @irq: irq number
  23. * @chip: pointer to irq chip description structure
  24. */
  25. int irq_set_chip(unsigned int irq, struct irq_chip *chip)
  26. {
  27. unsigned long flags;
  28. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  29. if (!desc)
  30. return -EINVAL;
  31. if (!chip)
  32. chip = &no_irq_chip;
  33. desc->irq_data.chip = chip;
  34. irq_put_desc_unlock(desc, flags);
  35. /*
  36. * For !CONFIG_SPARSE_IRQ make the irq show up in
  37. * allocated_irqs.
  38. */
  39. irq_mark_irq(irq);
  40. return 0;
  41. }
  42. EXPORT_SYMBOL(irq_set_chip);
  43. /**
  44. * irq_set_type - set the irq trigger type for an irq
  45. * @irq: irq number
  46. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  47. */
  48. int irq_set_irq_type(unsigned int irq, unsigned int type)
  49. {
  50. unsigned long flags;
  51. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  52. int ret = 0;
  53. if (!desc)
  54. return -EINVAL;
  55. type &= IRQ_TYPE_SENSE_MASK;
  56. ret = __irq_set_trigger(desc, type);
  57. irq_put_desc_busunlock(desc, flags);
  58. return ret;
  59. }
  60. EXPORT_SYMBOL(irq_set_irq_type);
  61. /**
  62. * irq_set_handler_data - set irq handler data for an irq
  63. * @irq: Interrupt number
  64. * @data: Pointer to interrupt specific data
  65. *
  66. * Set the hardware irq controller data for an irq
  67. */
  68. int irq_set_handler_data(unsigned int irq, void *data)
  69. {
  70. unsigned long flags;
  71. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  72. if (!desc)
  73. return -EINVAL;
  74. desc->irq_common_data.handler_data = data;
  75. irq_put_desc_unlock(desc, flags);
  76. return 0;
  77. }
  78. EXPORT_SYMBOL(irq_set_handler_data);
  79. /**
  80. * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
  81. * @irq_base: Interrupt number base
  82. * @irq_offset: Interrupt number offset
  83. * @entry: Pointer to MSI descriptor data
  84. *
  85. * Set the MSI descriptor entry for an irq at offset
  86. */
  87. int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
  88. struct msi_desc *entry)
  89. {
  90. unsigned long flags;
  91. struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  92. if (!desc)
  93. return -EINVAL;
  94. desc->irq_common_data.msi_desc = entry;
  95. if (entry && !irq_offset)
  96. entry->irq = irq_base;
  97. irq_put_desc_unlock(desc, flags);
  98. return 0;
  99. }
  100. /**
  101. * irq_set_msi_desc - set MSI descriptor data for an irq
  102. * @irq: Interrupt number
  103. * @entry: Pointer to MSI descriptor data
  104. *
  105. * Set the MSI descriptor entry for an irq
  106. */
  107. int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
  108. {
  109. return irq_set_msi_desc_off(irq, 0, entry);
  110. }
  111. /**
  112. * irq_set_chip_data - set irq chip data for an irq
  113. * @irq: Interrupt number
  114. * @data: Pointer to chip specific data
  115. *
  116. * Set the hardware irq chip data for an irq
  117. */
  118. int irq_set_chip_data(unsigned int irq, void *data)
  119. {
  120. unsigned long flags;
  121. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  122. if (!desc)
  123. return -EINVAL;
  124. desc->irq_data.chip_data = data;
  125. irq_put_desc_unlock(desc, flags);
  126. return 0;
  127. }
  128. EXPORT_SYMBOL(irq_set_chip_data);
  129. struct irq_data *irq_get_irq_data(unsigned int irq)
  130. {
  131. struct irq_desc *desc = irq_to_desc(irq);
  132. return desc ? &desc->irq_data : NULL;
  133. }
  134. EXPORT_SYMBOL_GPL(irq_get_irq_data);
  135. static void irq_state_clr_disabled(struct irq_desc *desc)
  136. {
  137. irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
  138. }
  139. static void irq_state_set_disabled(struct irq_desc *desc)
  140. {
  141. irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
  142. }
  143. static void irq_state_clr_masked(struct irq_desc *desc)
  144. {
  145. irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
  146. }
  147. static void irq_state_set_masked(struct irq_desc *desc)
  148. {
  149. irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
  150. }
  151. int irq_startup(struct irq_desc *desc, bool resend)
  152. {
  153. int ret = 0;
  154. irq_state_clr_disabled(desc);
  155. desc->depth = 0;
  156. irq_domain_activate_irq(&desc->irq_data);
  157. if (desc->irq_data.chip->irq_startup) {
  158. ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
  159. irq_state_clr_masked(desc);
  160. } else {
  161. irq_enable(desc);
  162. }
  163. if (resend)
  164. check_irq_resend(desc);
  165. return ret;
  166. }
  167. void irq_shutdown(struct irq_desc *desc)
  168. {
  169. irq_state_set_disabled(desc);
  170. desc->depth = 1;
  171. if (desc->irq_data.chip->irq_shutdown)
  172. desc->irq_data.chip->irq_shutdown(&desc->irq_data);
  173. else if (desc->irq_data.chip->irq_disable)
  174. desc->irq_data.chip->irq_disable(&desc->irq_data);
  175. else
  176. desc->irq_data.chip->irq_mask(&desc->irq_data);
  177. irq_domain_deactivate_irq(&desc->irq_data);
  178. irq_state_set_masked(desc);
  179. }
  180. void irq_enable(struct irq_desc *desc)
  181. {
  182. irq_state_clr_disabled(desc);
  183. if (desc->irq_data.chip->irq_enable)
  184. desc->irq_data.chip->irq_enable(&desc->irq_data);
  185. else
  186. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  187. irq_state_clr_masked(desc);
  188. }
  189. /**
  190. * irq_disable - Mark interrupt disabled
  191. * @desc: irq descriptor which should be disabled
  192. *
  193. * If the chip does not implement the irq_disable callback, we
  194. * use a lazy disable approach. That means we mark the interrupt
  195. * disabled, but leave the hardware unmasked. That's an
  196. * optimization because we avoid the hardware access for the
  197. * common case where no interrupt happens after we marked it
  198. * disabled. If an interrupt happens, then the interrupt flow
  199. * handler masks the line at the hardware level and marks it
  200. * pending.
  201. */
  202. void irq_disable(struct irq_desc *desc)
  203. {
  204. irq_state_set_disabled(desc);
  205. if (desc->irq_data.chip->irq_disable) {
  206. desc->irq_data.chip->irq_disable(&desc->irq_data);
  207. irq_state_set_masked(desc);
  208. }
  209. }
  210. void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
  211. {
  212. if (desc->irq_data.chip->irq_enable)
  213. desc->irq_data.chip->irq_enable(&desc->irq_data);
  214. else
  215. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  216. cpumask_set_cpu(cpu, desc->percpu_enabled);
  217. }
  218. void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
  219. {
  220. if (desc->irq_data.chip->irq_disable)
  221. desc->irq_data.chip->irq_disable(&desc->irq_data);
  222. else
  223. desc->irq_data.chip->irq_mask(&desc->irq_data);
  224. cpumask_clear_cpu(cpu, desc->percpu_enabled);
  225. }
  226. static inline void mask_ack_irq(struct irq_desc *desc)
  227. {
  228. if (desc->irq_data.chip->irq_mask_ack)
  229. desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
  230. else {
  231. desc->irq_data.chip->irq_mask(&desc->irq_data);
  232. if (desc->irq_data.chip->irq_ack)
  233. desc->irq_data.chip->irq_ack(&desc->irq_data);
  234. }
  235. irq_state_set_masked(desc);
  236. }
  237. void mask_irq(struct irq_desc *desc)
  238. {
  239. if (desc->irq_data.chip->irq_mask) {
  240. desc->irq_data.chip->irq_mask(&desc->irq_data);
  241. irq_state_set_masked(desc);
  242. }
  243. }
  244. void unmask_irq(struct irq_desc *desc)
  245. {
  246. if (desc->irq_data.chip->irq_unmask) {
  247. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  248. irq_state_clr_masked(desc);
  249. }
  250. }
  251. void unmask_threaded_irq(struct irq_desc *desc)
  252. {
  253. struct irq_chip *chip = desc->irq_data.chip;
  254. if (chip->flags & IRQCHIP_EOI_THREADED)
  255. chip->irq_eoi(&desc->irq_data);
  256. if (chip->irq_unmask) {
  257. chip->irq_unmask(&desc->irq_data);
  258. irq_state_clr_masked(desc);
  259. }
  260. }
  261. /*
  262. * handle_nested_irq - Handle a nested irq from a irq thread
  263. * @irq: the interrupt number
  264. *
  265. * Handle interrupts which are nested into a threaded interrupt
  266. * handler. The handler function is called inside the calling
  267. * threads context.
  268. */
  269. void handle_nested_irq(unsigned int irq)
  270. {
  271. struct irq_desc *desc = irq_to_desc(irq);
  272. struct irqaction *action;
  273. irqreturn_t action_ret;
  274. might_sleep();
  275. raw_spin_lock_irq(&desc->lock);
  276. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  277. kstat_incr_irqs_this_cpu(desc);
  278. action = desc->action;
  279. if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
  280. desc->istate |= IRQS_PENDING;
  281. goto out_unlock;
  282. }
  283. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  284. raw_spin_unlock_irq(&desc->lock);
  285. action_ret = action->thread_fn(action->irq, action->dev_id);
  286. if (!noirqdebug)
  287. note_interrupt(desc, action_ret);
  288. raw_spin_lock_irq(&desc->lock);
  289. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  290. out_unlock:
  291. raw_spin_unlock_irq(&desc->lock);
  292. }
  293. EXPORT_SYMBOL_GPL(handle_nested_irq);
  294. static bool irq_check_poll(struct irq_desc *desc)
  295. {
  296. if (!(desc->istate & IRQS_POLL_INPROGRESS))
  297. return false;
  298. return irq_wait_for_poll(desc);
  299. }
  300. static bool irq_may_run(struct irq_desc *desc)
  301. {
  302. unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
  303. /*
  304. * If the interrupt is not in progress and is not an armed
  305. * wakeup interrupt, proceed.
  306. */
  307. if (!irqd_has_set(&desc->irq_data, mask))
  308. return true;
  309. /*
  310. * If the interrupt is an armed wakeup source, mark it pending
  311. * and suspended, disable it and notify the pm core about the
  312. * event.
  313. */
  314. if (irq_pm_check_wakeup(desc))
  315. return false;
  316. /*
  317. * Handle a potential concurrent poll on a different core.
  318. */
  319. return irq_check_poll(desc);
  320. }
  321. /**
  322. * handle_simple_irq - Simple and software-decoded IRQs.
  323. * @irq: the interrupt number
  324. * @desc: the interrupt description structure for this irq
  325. *
  326. * Simple interrupts are either sent from a demultiplexing interrupt
  327. * handler or come from hardware, where no interrupt hardware control
  328. * is necessary.
  329. *
  330. * Note: The caller is expected to handle the ack, clear, mask and
  331. * unmask issues if necessary.
  332. */
  333. void
  334. handle_simple_irq(unsigned int irq, struct irq_desc *desc)
  335. {
  336. raw_spin_lock(&desc->lock);
  337. if (!irq_may_run(desc))
  338. goto out_unlock;
  339. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  340. kstat_incr_irqs_this_cpu(desc);
  341. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  342. desc->istate |= IRQS_PENDING;
  343. goto out_unlock;
  344. }
  345. handle_irq_event(desc);
  346. out_unlock:
  347. raw_spin_unlock(&desc->lock);
  348. }
  349. EXPORT_SYMBOL_GPL(handle_simple_irq);
  350. /*
  351. * Called unconditionally from handle_level_irq() and only for oneshot
  352. * interrupts from handle_fasteoi_irq()
  353. */
  354. static void cond_unmask_irq(struct irq_desc *desc)
  355. {
  356. /*
  357. * We need to unmask in the following cases:
  358. * - Standard level irq (IRQF_ONESHOT is not set)
  359. * - Oneshot irq which did not wake the thread (caused by a
  360. * spurious interrupt or a primary handler handling it
  361. * completely).
  362. */
  363. if (!irqd_irq_disabled(&desc->irq_data) &&
  364. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
  365. unmask_irq(desc);
  366. }
  367. /**
  368. * handle_level_irq - Level type irq handler
  369. * @irq: the interrupt number
  370. * @desc: the interrupt description structure for this irq
  371. *
  372. * Level type interrupts are active as long as the hardware line has
  373. * the active level. This may require to mask the interrupt and unmask
  374. * it after the associated handler has acknowledged the device, so the
  375. * interrupt line is back to inactive.
  376. */
  377. void
  378. handle_level_irq(unsigned int irq, struct irq_desc *desc)
  379. {
  380. raw_spin_lock(&desc->lock);
  381. mask_ack_irq(desc);
  382. if (!irq_may_run(desc))
  383. goto out_unlock;
  384. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  385. kstat_incr_irqs_this_cpu(desc);
  386. /*
  387. * If its disabled or no action available
  388. * keep it masked and get out of here
  389. */
  390. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  391. desc->istate |= IRQS_PENDING;
  392. goto out_unlock;
  393. }
  394. handle_irq_event(desc);
  395. cond_unmask_irq(desc);
  396. out_unlock:
  397. raw_spin_unlock(&desc->lock);
  398. }
  399. EXPORT_SYMBOL_GPL(handle_level_irq);
  400. #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
  401. static inline void preflow_handler(struct irq_desc *desc)
  402. {
  403. if (desc->preflow_handler)
  404. desc->preflow_handler(&desc->irq_data);
  405. }
  406. #else
  407. static inline void preflow_handler(struct irq_desc *desc) { }
  408. #endif
  409. static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
  410. {
  411. if (!(desc->istate & IRQS_ONESHOT)) {
  412. chip->irq_eoi(&desc->irq_data);
  413. return;
  414. }
  415. /*
  416. * We need to unmask in the following cases:
  417. * - Oneshot irq which did not wake the thread (caused by a
  418. * spurious interrupt or a primary handler handling it
  419. * completely).
  420. */
  421. if (!irqd_irq_disabled(&desc->irq_data) &&
  422. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
  423. chip->irq_eoi(&desc->irq_data);
  424. unmask_irq(desc);
  425. } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
  426. chip->irq_eoi(&desc->irq_data);
  427. }
  428. }
  429. /**
  430. * handle_fasteoi_irq - irq handler for transparent controllers
  431. * @irq: the interrupt number
  432. * @desc: the interrupt description structure for this irq
  433. *
  434. * Only a single callback will be issued to the chip: an ->eoi()
  435. * call when the interrupt has been serviced. This enables support
  436. * for modern forms of interrupt handlers, which handle the flow
  437. * details in hardware, transparently.
  438. */
  439. void
  440. handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
  441. {
  442. struct irq_chip *chip = desc->irq_data.chip;
  443. raw_spin_lock(&desc->lock);
  444. if (!irq_may_run(desc))
  445. goto out;
  446. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  447. kstat_incr_irqs_this_cpu(desc);
  448. /*
  449. * If its disabled or no action available
  450. * then mask it and get out of here:
  451. */
  452. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  453. desc->istate |= IRQS_PENDING;
  454. mask_irq(desc);
  455. goto out;
  456. }
  457. if (desc->istate & IRQS_ONESHOT)
  458. mask_irq(desc);
  459. preflow_handler(desc);
  460. handle_irq_event(desc);
  461. cond_unmask_eoi_irq(desc, chip);
  462. raw_spin_unlock(&desc->lock);
  463. return;
  464. out:
  465. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  466. chip->irq_eoi(&desc->irq_data);
  467. raw_spin_unlock(&desc->lock);
  468. }
  469. EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
  470. /**
  471. * handle_edge_irq - edge type IRQ handler
  472. * @irq: the interrupt number
  473. * @desc: the interrupt description structure for this irq
  474. *
  475. * Interrupt occures on the falling and/or rising edge of a hardware
  476. * signal. The occurrence is latched into the irq controller hardware
  477. * and must be acked in order to be reenabled. After the ack another
  478. * interrupt can happen on the same source even before the first one
  479. * is handled by the associated event handler. If this happens it
  480. * might be necessary to disable (mask) the interrupt depending on the
  481. * controller hardware. This requires to reenable the interrupt inside
  482. * of the loop which handles the interrupts which have arrived while
  483. * the handler was running. If all pending interrupts are handled, the
  484. * loop is left.
  485. */
  486. void
  487. handle_edge_irq(unsigned int irq, struct irq_desc *desc)
  488. {
  489. raw_spin_lock(&desc->lock);
  490. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  491. if (!irq_may_run(desc)) {
  492. desc->istate |= IRQS_PENDING;
  493. mask_ack_irq(desc);
  494. goto out_unlock;
  495. }
  496. /*
  497. * If its disabled or no action available then mask it and get
  498. * out of here.
  499. */
  500. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  501. desc->istate |= IRQS_PENDING;
  502. mask_ack_irq(desc);
  503. goto out_unlock;
  504. }
  505. kstat_incr_irqs_this_cpu(desc);
  506. /* Start handling the irq */
  507. desc->irq_data.chip->irq_ack(&desc->irq_data);
  508. do {
  509. if (unlikely(!desc->action)) {
  510. mask_irq(desc);
  511. goto out_unlock;
  512. }
  513. /*
  514. * When another irq arrived while we were handling
  515. * one, we could have masked the irq.
  516. * Renable it, if it was not disabled in meantime.
  517. */
  518. if (unlikely(desc->istate & IRQS_PENDING)) {
  519. if (!irqd_irq_disabled(&desc->irq_data) &&
  520. irqd_irq_masked(&desc->irq_data))
  521. unmask_irq(desc);
  522. }
  523. handle_irq_event(desc);
  524. } while ((desc->istate & IRQS_PENDING) &&
  525. !irqd_irq_disabled(&desc->irq_data));
  526. out_unlock:
  527. raw_spin_unlock(&desc->lock);
  528. }
  529. EXPORT_SYMBOL(handle_edge_irq);
  530. #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
  531. /**
  532. * handle_edge_eoi_irq - edge eoi type IRQ handler
  533. * @irq: the interrupt number
  534. * @desc: the interrupt description structure for this irq
  535. *
  536. * Similar as the above handle_edge_irq, but using eoi and w/o the
  537. * mask/unmask logic.
  538. */
  539. void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
  540. {
  541. struct irq_chip *chip = irq_desc_get_chip(desc);
  542. raw_spin_lock(&desc->lock);
  543. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  544. if (!irq_may_run(desc)) {
  545. desc->istate |= IRQS_PENDING;
  546. goto out_eoi;
  547. }
  548. /*
  549. * If its disabled or no action available then mask it and get
  550. * out of here.
  551. */
  552. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  553. desc->istate |= IRQS_PENDING;
  554. goto out_eoi;
  555. }
  556. kstat_incr_irqs_this_cpu(desc);
  557. do {
  558. if (unlikely(!desc->action))
  559. goto out_eoi;
  560. handle_irq_event(desc);
  561. } while ((desc->istate & IRQS_PENDING) &&
  562. !irqd_irq_disabled(&desc->irq_data));
  563. out_eoi:
  564. chip->irq_eoi(&desc->irq_data);
  565. raw_spin_unlock(&desc->lock);
  566. }
  567. #endif
  568. /**
  569. * handle_percpu_irq - Per CPU local irq handler
  570. * @irq: the interrupt number
  571. * @desc: the interrupt description structure for this irq
  572. *
  573. * Per CPU interrupts on SMP machines without locking requirements
  574. */
  575. void
  576. handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
  577. {
  578. struct irq_chip *chip = irq_desc_get_chip(desc);
  579. kstat_incr_irqs_this_cpu(desc);
  580. if (chip->irq_ack)
  581. chip->irq_ack(&desc->irq_data);
  582. handle_irq_event_percpu(desc, desc->action);
  583. if (chip->irq_eoi)
  584. chip->irq_eoi(&desc->irq_data);
  585. }
  586. /**
  587. * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
  588. * @irq: the interrupt number
  589. * @desc: the interrupt description structure for this irq
  590. *
  591. * Per CPU interrupts on SMP machines without locking requirements. Same as
  592. * handle_percpu_irq() above but with the following extras:
  593. *
  594. * action->percpu_dev_id is a pointer to percpu variables which
  595. * contain the real device id for the cpu on which this handler is
  596. * called
  597. */
  598. void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
  599. {
  600. struct irq_chip *chip = irq_desc_get_chip(desc);
  601. struct irqaction *action = desc->action;
  602. void *dev_id = raw_cpu_ptr(action->percpu_dev_id);
  603. irqreturn_t res;
  604. kstat_incr_irqs_this_cpu(desc);
  605. if (chip->irq_ack)
  606. chip->irq_ack(&desc->irq_data);
  607. trace_irq_handler_entry(irq, action);
  608. res = action->handler(irq, dev_id);
  609. trace_irq_handler_exit(irq, action, res);
  610. if (chip->irq_eoi)
  611. chip->irq_eoi(&desc->irq_data);
  612. }
  613. void
  614. __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
  615. int is_chained, const char *name)
  616. {
  617. if (!handle) {
  618. handle = handle_bad_irq;
  619. } else {
  620. struct irq_data *irq_data = &desc->irq_data;
  621. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  622. /*
  623. * With hierarchical domains we might run into a
  624. * situation where the outermost chip is not yet set
  625. * up, but the inner chips are there. Instead of
  626. * bailing we install the handler, but obviously we
  627. * cannot enable/startup the interrupt at this point.
  628. */
  629. while (irq_data) {
  630. if (irq_data->chip != &no_irq_chip)
  631. break;
  632. /*
  633. * Bail out if the outer chip is not set up
  634. * and the interrrupt supposed to be started
  635. * right away.
  636. */
  637. if (WARN_ON(is_chained))
  638. return;
  639. /* Try the parent */
  640. irq_data = irq_data->parent_data;
  641. }
  642. #endif
  643. if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
  644. return;
  645. }
  646. /* Uninstall? */
  647. if (handle == handle_bad_irq) {
  648. if (desc->irq_data.chip != &no_irq_chip)
  649. mask_ack_irq(desc);
  650. irq_state_set_disabled(desc);
  651. desc->depth = 1;
  652. }
  653. desc->handle_irq = handle;
  654. desc->name = name;
  655. if (handle != handle_bad_irq && is_chained) {
  656. irq_settings_set_noprobe(desc);
  657. irq_settings_set_norequest(desc);
  658. irq_settings_set_nothread(desc);
  659. irq_startup(desc, true);
  660. }
  661. }
  662. void
  663. __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
  664. const char *name)
  665. {
  666. unsigned long flags;
  667. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  668. if (!desc)
  669. return;
  670. __irq_do_set_handler(desc, handle, is_chained, name);
  671. irq_put_desc_busunlock(desc, flags);
  672. }
  673. EXPORT_SYMBOL_GPL(__irq_set_handler);
  674. void
  675. irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
  676. void *data)
  677. {
  678. unsigned long flags;
  679. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  680. if (!desc)
  681. return;
  682. __irq_do_set_handler(desc, handle, 1, NULL);
  683. desc->irq_common_data.handler_data = data;
  684. irq_put_desc_busunlock(desc, flags);
  685. }
  686. EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
  687. void
  688. irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
  689. irq_flow_handler_t handle, const char *name)
  690. {
  691. irq_set_chip(irq, chip);
  692. __irq_set_handler(irq, handle, 0, name);
  693. }
  694. EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
  695. void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
  696. {
  697. unsigned long flags;
  698. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  699. if (!desc)
  700. return;
  701. irq_settings_clr_and_set(desc, clr, set);
  702. irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
  703. IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
  704. if (irq_settings_has_no_balance_set(desc))
  705. irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
  706. if (irq_settings_is_per_cpu(desc))
  707. irqd_set(&desc->irq_data, IRQD_PER_CPU);
  708. if (irq_settings_can_move_pcntxt(desc))
  709. irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
  710. if (irq_settings_is_level(desc))
  711. irqd_set(&desc->irq_data, IRQD_LEVEL);
  712. irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
  713. irq_put_desc_unlock(desc, flags);
  714. }
  715. EXPORT_SYMBOL_GPL(irq_modify_status);
  716. /**
  717. * irq_cpu_online - Invoke all irq_cpu_online functions.
  718. *
  719. * Iterate through all irqs and invoke the chip.irq_cpu_online()
  720. * for each.
  721. */
  722. void irq_cpu_online(void)
  723. {
  724. struct irq_desc *desc;
  725. struct irq_chip *chip;
  726. unsigned long flags;
  727. unsigned int irq;
  728. for_each_active_irq(irq) {
  729. desc = irq_to_desc(irq);
  730. if (!desc)
  731. continue;
  732. raw_spin_lock_irqsave(&desc->lock, flags);
  733. chip = irq_data_get_irq_chip(&desc->irq_data);
  734. if (chip && chip->irq_cpu_online &&
  735. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  736. !irqd_irq_disabled(&desc->irq_data)))
  737. chip->irq_cpu_online(&desc->irq_data);
  738. raw_spin_unlock_irqrestore(&desc->lock, flags);
  739. }
  740. }
  741. /**
  742. * irq_cpu_offline - Invoke all irq_cpu_offline functions.
  743. *
  744. * Iterate through all irqs and invoke the chip.irq_cpu_offline()
  745. * for each.
  746. */
  747. void irq_cpu_offline(void)
  748. {
  749. struct irq_desc *desc;
  750. struct irq_chip *chip;
  751. unsigned long flags;
  752. unsigned int irq;
  753. for_each_active_irq(irq) {
  754. desc = irq_to_desc(irq);
  755. if (!desc)
  756. continue;
  757. raw_spin_lock_irqsave(&desc->lock, flags);
  758. chip = irq_data_get_irq_chip(&desc->irq_data);
  759. if (chip && chip->irq_cpu_offline &&
  760. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  761. !irqd_irq_disabled(&desc->irq_data)))
  762. chip->irq_cpu_offline(&desc->irq_data);
  763. raw_spin_unlock_irqrestore(&desc->lock, flags);
  764. }
  765. }
  766. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  767. /**
  768. * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
  769. * NULL)
  770. * @data: Pointer to interrupt specific data
  771. */
  772. void irq_chip_enable_parent(struct irq_data *data)
  773. {
  774. data = data->parent_data;
  775. if (data->chip->irq_enable)
  776. data->chip->irq_enable(data);
  777. else
  778. data->chip->irq_unmask(data);
  779. }
  780. /**
  781. * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
  782. * NULL)
  783. * @data: Pointer to interrupt specific data
  784. */
  785. void irq_chip_disable_parent(struct irq_data *data)
  786. {
  787. data = data->parent_data;
  788. if (data->chip->irq_disable)
  789. data->chip->irq_disable(data);
  790. else
  791. data->chip->irq_mask(data);
  792. }
  793. /**
  794. * irq_chip_ack_parent - Acknowledge the parent interrupt
  795. * @data: Pointer to interrupt specific data
  796. */
  797. void irq_chip_ack_parent(struct irq_data *data)
  798. {
  799. data = data->parent_data;
  800. data->chip->irq_ack(data);
  801. }
  802. /**
  803. * irq_chip_mask_parent - Mask the parent interrupt
  804. * @data: Pointer to interrupt specific data
  805. */
  806. void irq_chip_mask_parent(struct irq_data *data)
  807. {
  808. data = data->parent_data;
  809. data->chip->irq_mask(data);
  810. }
  811. /**
  812. * irq_chip_unmask_parent - Unmask the parent interrupt
  813. * @data: Pointer to interrupt specific data
  814. */
  815. void irq_chip_unmask_parent(struct irq_data *data)
  816. {
  817. data = data->parent_data;
  818. data->chip->irq_unmask(data);
  819. }
  820. /**
  821. * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
  822. * @data: Pointer to interrupt specific data
  823. */
  824. void irq_chip_eoi_parent(struct irq_data *data)
  825. {
  826. data = data->parent_data;
  827. data->chip->irq_eoi(data);
  828. }
  829. /**
  830. * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
  831. * @data: Pointer to interrupt specific data
  832. * @dest: The affinity mask to set
  833. * @force: Flag to enforce setting (disable online checks)
  834. *
  835. * Conditinal, as the underlying parent chip might not implement it.
  836. */
  837. int irq_chip_set_affinity_parent(struct irq_data *data,
  838. const struct cpumask *dest, bool force)
  839. {
  840. data = data->parent_data;
  841. if (data->chip->irq_set_affinity)
  842. return data->chip->irq_set_affinity(data, dest, force);
  843. return -ENOSYS;
  844. }
  845. /**
  846. * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
  847. * @data: Pointer to interrupt specific data
  848. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  849. *
  850. * Conditional, as the underlying parent chip might not implement it.
  851. */
  852. int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
  853. {
  854. data = data->parent_data;
  855. if (data->chip->irq_set_type)
  856. return data->chip->irq_set_type(data, type);
  857. return -ENOSYS;
  858. }
  859. /**
  860. * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
  861. * @data: Pointer to interrupt specific data
  862. *
  863. * Iterate through the domain hierarchy of the interrupt and check
  864. * whether a hw retrigger function exists. If yes, invoke it.
  865. */
  866. int irq_chip_retrigger_hierarchy(struct irq_data *data)
  867. {
  868. for (data = data->parent_data; data; data = data->parent_data)
  869. if (data->chip && data->chip->irq_retrigger)
  870. return data->chip->irq_retrigger(data);
  871. return 0;
  872. }
  873. /**
  874. * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
  875. * @data: Pointer to interrupt specific data
  876. * @vcpu_info: The vcpu affinity information
  877. */
  878. int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
  879. {
  880. data = data->parent_data;
  881. if (data->chip->irq_set_vcpu_affinity)
  882. return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
  883. return -ENOSYS;
  884. }
  885. /**
  886. * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
  887. * @data: Pointer to interrupt specific data
  888. * @on: Whether to set or reset the wake-up capability of this irq
  889. *
  890. * Conditional, as the underlying parent chip might not implement it.
  891. */
  892. int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
  893. {
  894. data = data->parent_data;
  895. if (data->chip->irq_set_wake)
  896. return data->chip->irq_set_wake(data, on);
  897. return -ENOSYS;
  898. }
  899. #endif
  900. /**
  901. * irq_chip_compose_msi_msg - Componse msi message for a irq chip
  902. * @data: Pointer to interrupt specific data
  903. * @msg: Pointer to the MSI message
  904. *
  905. * For hierarchical domains we find the first chip in the hierarchy
  906. * which implements the irq_compose_msi_msg callback. For non
  907. * hierarchical we use the top level chip.
  908. */
  909. int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  910. {
  911. struct irq_data *pos = NULL;
  912. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  913. for (; data; data = data->parent_data)
  914. #endif
  915. if (data->chip && data->chip->irq_compose_msi_msg)
  916. pos = data;
  917. if (!pos)
  918. return -ENOSYS;
  919. pos->chip->irq_compose_msi_msg(pos, msg);
  920. return 0;
  921. }