core.c 51 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include "core.h"
  21. #include "mac.h"
  22. #include "htc.h"
  23. #include "hif.h"
  24. #include "wmi.h"
  25. #include "bmi.h"
  26. #include "debug.h"
  27. #include "htt.h"
  28. #include "testmode.h"
  29. #include "wmi-ops.h"
  30. unsigned int ath10k_debug_mask;
  31. static unsigned int ath10k_cryptmode_param;
  32. static bool uart_print;
  33. static bool skip_otp;
  34. static bool rawmode;
  35. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  36. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  37. module_param(uart_print, bool, 0644);
  38. module_param(skip_otp, bool, 0644);
  39. module_param(rawmode, bool, 0644);
  40. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  41. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  42. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  43. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  44. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  45. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  46. {
  47. .id = QCA988X_HW_2_0_VERSION,
  48. .dev_id = QCA988X_2_0_DEVICE_ID,
  49. .name = "qca988x hw2.0",
  50. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  51. .uart_pin = 7,
  52. .has_shifted_cc_wraparound = true,
  53. .otp_exe_param = 0,
  54. .channel_counters_freq_hz = 88000,
  55. .max_probe_resp_desc_thres = 0,
  56. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  57. .fw = {
  58. .dir = QCA988X_HW_2_0_FW_DIR,
  59. .fw = QCA988X_HW_2_0_FW_FILE,
  60. .otp = QCA988X_HW_2_0_OTP_FILE,
  61. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  62. .board_size = QCA988X_BOARD_DATA_SZ,
  63. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  64. },
  65. },
  66. {
  67. .id = QCA6174_HW_2_1_VERSION,
  68. .dev_id = QCA6164_2_1_DEVICE_ID,
  69. .name = "qca6164 hw2.1",
  70. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  71. .uart_pin = 6,
  72. .otp_exe_param = 0,
  73. .channel_counters_freq_hz = 88000,
  74. .max_probe_resp_desc_thres = 0,
  75. .fw = {
  76. .dir = QCA6174_HW_2_1_FW_DIR,
  77. .fw = QCA6174_HW_2_1_FW_FILE,
  78. .otp = QCA6174_HW_2_1_OTP_FILE,
  79. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  80. .board_size = QCA6174_BOARD_DATA_SZ,
  81. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  82. },
  83. },
  84. {
  85. .id = QCA6174_HW_2_1_VERSION,
  86. .dev_id = QCA6174_2_1_DEVICE_ID,
  87. .name = "qca6174 hw2.1",
  88. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  89. .uart_pin = 6,
  90. .otp_exe_param = 0,
  91. .channel_counters_freq_hz = 88000,
  92. .max_probe_resp_desc_thres = 0,
  93. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  94. .fw = {
  95. .dir = QCA6174_HW_2_1_FW_DIR,
  96. .fw = QCA6174_HW_2_1_FW_FILE,
  97. .otp = QCA6174_HW_2_1_OTP_FILE,
  98. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  99. .board_size = QCA6174_BOARD_DATA_SZ,
  100. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  101. },
  102. },
  103. {
  104. .id = QCA6174_HW_3_0_VERSION,
  105. .dev_id = QCA6174_2_1_DEVICE_ID,
  106. .name = "qca6174 hw3.0",
  107. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  108. .uart_pin = 6,
  109. .otp_exe_param = 0,
  110. .channel_counters_freq_hz = 88000,
  111. .max_probe_resp_desc_thres = 0,
  112. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  113. .fw = {
  114. .dir = QCA6174_HW_3_0_FW_DIR,
  115. .fw = QCA6174_HW_3_0_FW_FILE,
  116. .otp = QCA6174_HW_3_0_OTP_FILE,
  117. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  118. .board_size = QCA6174_BOARD_DATA_SZ,
  119. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  120. },
  121. },
  122. {
  123. .id = QCA6174_HW_3_2_VERSION,
  124. .dev_id = QCA6174_2_1_DEVICE_ID,
  125. .name = "qca6174 hw3.2",
  126. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  127. .uart_pin = 6,
  128. .otp_exe_param = 0,
  129. .channel_counters_freq_hz = 88000,
  130. .max_probe_resp_desc_thres = 0,
  131. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
  132. .fw = {
  133. /* uses same binaries as hw3.0 */
  134. .dir = QCA6174_HW_3_0_FW_DIR,
  135. .fw = QCA6174_HW_3_0_FW_FILE,
  136. .otp = QCA6174_HW_3_0_OTP_FILE,
  137. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  138. .board_size = QCA6174_BOARD_DATA_SZ,
  139. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  140. },
  141. },
  142. {
  143. .id = QCA99X0_HW_2_0_DEV_VERSION,
  144. .dev_id = QCA99X0_2_0_DEVICE_ID,
  145. .name = "qca99x0 hw2.0",
  146. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  147. .uart_pin = 7,
  148. .otp_exe_param = 0x00000700,
  149. .continuous_frag_desc = true,
  150. .channel_counters_freq_hz = 150000,
  151. .max_probe_resp_desc_thres = 24,
  152. .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
  153. .fw = {
  154. .dir = QCA99X0_HW_2_0_FW_DIR,
  155. .fw = QCA99X0_HW_2_0_FW_FILE,
  156. .otp = QCA99X0_HW_2_0_OTP_FILE,
  157. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  158. .board_size = QCA99X0_BOARD_DATA_SZ,
  159. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  160. },
  161. },
  162. {
  163. .id = QCA9377_HW_1_0_DEV_VERSION,
  164. .dev_id = QCA9377_1_0_DEVICE_ID,
  165. .name = "qca9377 hw1.0",
  166. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  167. .uart_pin = 6,
  168. .otp_exe_param = 0,
  169. .channel_counters_freq_hz = 88000,
  170. .max_probe_resp_desc_thres = 0,
  171. .fw = {
  172. .dir = QCA9377_HW_1_0_FW_DIR,
  173. .fw = QCA9377_HW_1_0_FW_FILE,
  174. .otp = QCA9377_HW_1_0_OTP_FILE,
  175. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  176. .board_size = QCA9377_BOARD_DATA_SZ,
  177. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  178. },
  179. },
  180. {
  181. .id = QCA9377_HW_1_1_DEV_VERSION,
  182. .dev_id = QCA9377_1_0_DEVICE_ID,
  183. .name = "qca9377 hw1.1",
  184. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  185. .uart_pin = 6,
  186. .otp_exe_param = 0,
  187. .channel_counters_freq_hz = 88000,
  188. .max_probe_resp_desc_thres = 0,
  189. .fw = {
  190. .dir = QCA9377_HW_1_0_FW_DIR,
  191. .fw = QCA9377_HW_1_0_FW_FILE,
  192. .otp = QCA9377_HW_1_0_OTP_FILE,
  193. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  194. .board_size = QCA9377_BOARD_DATA_SZ,
  195. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  196. },
  197. },
  198. };
  199. static const char *const ath10k_core_fw_feature_str[] = {
  200. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  201. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  202. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  203. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  204. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  205. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  206. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  207. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  208. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  209. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  210. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  211. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  212. [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
  213. };
  214. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  215. size_t buf_len,
  216. enum ath10k_fw_features feat)
  217. {
  218. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  219. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  220. ATH10K_FW_FEATURE_COUNT);
  221. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  222. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  223. return scnprintf(buf, buf_len, "bit%d", feat);
  224. }
  225. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  226. }
  227. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  228. char *buf,
  229. size_t buf_len)
  230. {
  231. unsigned int len = 0;
  232. int i;
  233. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  234. if (test_bit(i, ar->fw_features)) {
  235. if (len > 0)
  236. len += scnprintf(buf + len, buf_len - len, ",");
  237. len += ath10k_core_get_fw_feature_str(buf + len,
  238. buf_len - len,
  239. i);
  240. }
  241. }
  242. }
  243. static void ath10k_send_suspend_complete(struct ath10k *ar)
  244. {
  245. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  246. complete(&ar->target_suspend);
  247. }
  248. static int ath10k_init_configure_target(struct ath10k *ar)
  249. {
  250. u32 param_host;
  251. int ret;
  252. /* tell target which HTC version it is used*/
  253. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  254. HTC_PROTOCOL_VERSION);
  255. if (ret) {
  256. ath10k_err(ar, "settings HTC version failed\n");
  257. return ret;
  258. }
  259. /* set the firmware mode to STA/IBSS/AP */
  260. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  261. if (ret) {
  262. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  263. return ret;
  264. }
  265. /* TODO following parameters need to be re-visited. */
  266. /* num_device */
  267. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  268. /* Firmware mode */
  269. /* FIXME: Why FW_MODE_AP ??.*/
  270. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  271. /* mac_addr_method */
  272. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  273. /* firmware_bridge */
  274. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  275. /* fwsubmode */
  276. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  277. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  278. if (ret) {
  279. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  280. return ret;
  281. }
  282. /* We do all byte-swapping on the host */
  283. ret = ath10k_bmi_write32(ar, hi_be, 0);
  284. if (ret) {
  285. ath10k_err(ar, "setting host CPU BE mode failed\n");
  286. return ret;
  287. }
  288. /* FW descriptor/Data swap flags */
  289. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  290. if (ret) {
  291. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  292. return ret;
  293. }
  294. /* Some devices have a special sanity check that verifies the PCI
  295. * Device ID is written to this host interest var. It is known to be
  296. * required to boot QCA6164.
  297. */
  298. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  299. ar->dev_id);
  300. if (ret) {
  301. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  302. return ret;
  303. }
  304. return 0;
  305. }
  306. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  307. const char *dir,
  308. const char *file)
  309. {
  310. char filename[100];
  311. const struct firmware *fw;
  312. int ret;
  313. if (file == NULL)
  314. return ERR_PTR(-ENOENT);
  315. if (dir == NULL)
  316. dir = ".";
  317. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  318. ret = request_firmware(&fw, filename, ar->dev);
  319. if (ret)
  320. return ERR_PTR(ret);
  321. return fw;
  322. }
  323. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  324. size_t data_len)
  325. {
  326. u32 board_data_size = ar->hw_params.fw.board_size;
  327. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  328. u32 board_ext_data_addr;
  329. int ret;
  330. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  331. if (ret) {
  332. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  333. ret);
  334. return ret;
  335. }
  336. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  337. "boot push board extended data addr 0x%x\n",
  338. board_ext_data_addr);
  339. if (board_ext_data_addr == 0)
  340. return 0;
  341. if (data_len != (board_data_size + board_ext_data_size)) {
  342. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  343. data_len, board_data_size, board_ext_data_size);
  344. return -EINVAL;
  345. }
  346. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  347. data + board_data_size,
  348. board_ext_data_size);
  349. if (ret) {
  350. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  351. return ret;
  352. }
  353. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  354. (board_ext_data_size << 16) | 1);
  355. if (ret) {
  356. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  357. ret);
  358. return ret;
  359. }
  360. return 0;
  361. }
  362. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  363. size_t data_len)
  364. {
  365. u32 board_data_size = ar->hw_params.fw.board_size;
  366. u32 address;
  367. int ret;
  368. ret = ath10k_push_board_ext_data(ar, data, data_len);
  369. if (ret) {
  370. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  371. goto exit;
  372. }
  373. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  374. if (ret) {
  375. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  376. goto exit;
  377. }
  378. ret = ath10k_bmi_write_memory(ar, address, data,
  379. min_t(u32, board_data_size,
  380. data_len));
  381. if (ret) {
  382. ath10k_err(ar, "could not write board data (%d)\n", ret);
  383. goto exit;
  384. }
  385. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  386. if (ret) {
  387. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  388. goto exit;
  389. }
  390. exit:
  391. return ret;
  392. }
  393. static int ath10k_download_cal_file(struct ath10k *ar)
  394. {
  395. int ret;
  396. if (!ar->cal_file)
  397. return -ENOENT;
  398. if (IS_ERR(ar->cal_file))
  399. return PTR_ERR(ar->cal_file);
  400. ret = ath10k_download_board_data(ar, ar->cal_file->data,
  401. ar->cal_file->size);
  402. if (ret) {
  403. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  404. return ret;
  405. }
  406. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  407. return 0;
  408. }
  409. static int ath10k_download_cal_dt(struct ath10k *ar)
  410. {
  411. struct device_node *node;
  412. int data_len;
  413. void *data;
  414. int ret;
  415. node = ar->dev->of_node;
  416. if (!node)
  417. /* Device Tree is optional, don't print any warnings if
  418. * there's no node for ath10k.
  419. */
  420. return -ENOENT;
  421. if (!of_get_property(node, "qcom,ath10k-calibration-data",
  422. &data_len)) {
  423. /* The calibration data node is optional */
  424. return -ENOENT;
  425. }
  426. if (data_len != QCA988X_CAL_DATA_LEN) {
  427. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  428. data_len);
  429. ret = -EMSGSIZE;
  430. goto out;
  431. }
  432. data = kmalloc(data_len, GFP_KERNEL);
  433. if (!data) {
  434. ret = -ENOMEM;
  435. goto out;
  436. }
  437. ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data",
  438. data, data_len);
  439. if (ret) {
  440. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  441. ret);
  442. goto out_free;
  443. }
  444. ret = ath10k_download_board_data(ar, data, data_len);
  445. if (ret) {
  446. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  447. ret);
  448. goto out_free;
  449. }
  450. ret = 0;
  451. out_free:
  452. kfree(data);
  453. out:
  454. return ret;
  455. }
  456. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  457. {
  458. u32 result, address;
  459. u8 board_id, chip_id;
  460. int ret;
  461. address = ar->hw_params.patch_load_addr;
  462. if (!ar->otp_data || !ar->otp_len) {
  463. ath10k_warn(ar,
  464. "failed to retrieve board id because of invalid otp\n");
  465. return -ENODATA;
  466. }
  467. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  468. "boot upload otp to 0x%x len %zd for board id\n",
  469. address, ar->otp_len);
  470. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  471. if (ret) {
  472. ath10k_err(ar, "could not write otp for board id check: %d\n",
  473. ret);
  474. return ret;
  475. }
  476. ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
  477. &result);
  478. if (ret) {
  479. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  480. ret);
  481. return ret;
  482. }
  483. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  484. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  485. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  486. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  487. result, board_id, chip_id);
  488. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0)
  489. return -EOPNOTSUPP;
  490. ar->id.bmi_ids_valid = true;
  491. ar->id.bmi_board_id = board_id;
  492. ar->id.bmi_chip_id = chip_id;
  493. return 0;
  494. }
  495. static int ath10k_download_and_run_otp(struct ath10k *ar)
  496. {
  497. u32 result, address = ar->hw_params.patch_load_addr;
  498. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  499. int ret;
  500. ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len);
  501. if (ret) {
  502. ath10k_err(ar, "failed to download board data: %d\n", ret);
  503. return ret;
  504. }
  505. /* OTP is optional */
  506. if (!ar->otp_data || !ar->otp_len) {
  507. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
  508. ar->otp_data, ar->otp_len);
  509. return 0;
  510. }
  511. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  512. address, ar->otp_len);
  513. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  514. if (ret) {
  515. ath10k_err(ar, "could not write otp (%d)\n", ret);
  516. return ret;
  517. }
  518. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  519. if (ret) {
  520. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  521. return ret;
  522. }
  523. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  524. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  525. ar->fw_features)) &&
  526. result != 0) {
  527. ath10k_err(ar, "otp calibration failed: %d", result);
  528. return -EINVAL;
  529. }
  530. return 0;
  531. }
  532. static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode)
  533. {
  534. u32 address, data_len;
  535. const char *mode_name;
  536. const void *data;
  537. int ret;
  538. address = ar->hw_params.patch_load_addr;
  539. switch (mode) {
  540. case ATH10K_FIRMWARE_MODE_NORMAL:
  541. data = ar->firmware_data;
  542. data_len = ar->firmware_len;
  543. mode_name = "normal";
  544. ret = ath10k_swap_code_seg_configure(ar,
  545. ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW);
  546. if (ret) {
  547. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  548. ret);
  549. return ret;
  550. }
  551. break;
  552. case ATH10K_FIRMWARE_MODE_UTF:
  553. data = ar->testmode.utf_firmware_data;
  554. data_len = ar->testmode.utf_firmware_len;
  555. mode_name = "utf";
  556. break;
  557. default:
  558. ath10k_err(ar, "unknown firmware mode: %d\n", mode);
  559. return -EINVAL;
  560. }
  561. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  562. "boot uploading firmware image %p len %d mode %s\n",
  563. data, data_len, mode_name);
  564. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  565. if (ret) {
  566. ath10k_err(ar, "failed to download %s firmware: %d\n",
  567. mode_name, ret);
  568. return ret;
  569. }
  570. return ret;
  571. }
  572. static void ath10k_core_free_board_files(struct ath10k *ar)
  573. {
  574. if (!IS_ERR(ar->board))
  575. release_firmware(ar->board);
  576. ar->board = NULL;
  577. ar->board_data = NULL;
  578. ar->board_len = 0;
  579. }
  580. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  581. {
  582. if (!IS_ERR(ar->otp))
  583. release_firmware(ar->otp);
  584. if (!IS_ERR(ar->firmware))
  585. release_firmware(ar->firmware);
  586. if (!IS_ERR(ar->cal_file))
  587. release_firmware(ar->cal_file);
  588. ath10k_swap_code_seg_release(ar);
  589. ar->otp = NULL;
  590. ar->otp_data = NULL;
  591. ar->otp_len = 0;
  592. ar->firmware = NULL;
  593. ar->firmware_data = NULL;
  594. ar->firmware_len = 0;
  595. ar->cal_file = NULL;
  596. }
  597. static int ath10k_fetch_cal_file(struct ath10k *ar)
  598. {
  599. char filename[100];
  600. /* cal-<bus>-<id>.bin */
  601. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  602. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  603. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  604. if (IS_ERR(ar->cal_file))
  605. /* calibration file is optional, don't print any warnings */
  606. return PTR_ERR(ar->cal_file);
  607. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  608. ATH10K_FW_DIR, filename);
  609. return 0;
  610. }
  611. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  612. {
  613. if (!ar->hw_params.fw.board) {
  614. ath10k_err(ar, "failed to find board file fw entry\n");
  615. return -EINVAL;
  616. }
  617. ar->board = ath10k_fetch_fw_file(ar,
  618. ar->hw_params.fw.dir,
  619. ar->hw_params.fw.board);
  620. if (IS_ERR(ar->board))
  621. return PTR_ERR(ar->board);
  622. ar->board_data = ar->board->data;
  623. ar->board_len = ar->board->size;
  624. return 0;
  625. }
  626. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  627. const void *buf, size_t buf_len,
  628. const char *boardname)
  629. {
  630. const struct ath10k_fw_ie *hdr;
  631. bool name_match_found;
  632. int ret, board_ie_id;
  633. size_t board_ie_len;
  634. const void *board_ie_data;
  635. name_match_found = false;
  636. /* go through ATH10K_BD_IE_BOARD_ elements */
  637. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  638. hdr = buf;
  639. board_ie_id = le32_to_cpu(hdr->id);
  640. board_ie_len = le32_to_cpu(hdr->len);
  641. board_ie_data = hdr->data;
  642. buf_len -= sizeof(*hdr);
  643. buf += sizeof(*hdr);
  644. if (buf_len < ALIGN(board_ie_len, 4)) {
  645. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  646. buf_len, ALIGN(board_ie_len, 4));
  647. ret = -EINVAL;
  648. goto out;
  649. }
  650. switch (board_ie_id) {
  651. case ATH10K_BD_IE_BOARD_NAME:
  652. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  653. board_ie_data, board_ie_len);
  654. if (board_ie_len != strlen(boardname))
  655. break;
  656. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  657. if (ret)
  658. break;
  659. name_match_found = true;
  660. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  661. "boot found match for name '%s'",
  662. boardname);
  663. break;
  664. case ATH10K_BD_IE_BOARD_DATA:
  665. if (!name_match_found)
  666. /* no match found */
  667. break;
  668. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  669. "boot found board data for '%s'",
  670. boardname);
  671. ar->board_data = board_ie_data;
  672. ar->board_len = board_ie_len;
  673. ret = 0;
  674. goto out;
  675. default:
  676. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  677. board_ie_id);
  678. break;
  679. }
  680. /* jump over the padding */
  681. board_ie_len = ALIGN(board_ie_len, 4);
  682. buf_len -= board_ie_len;
  683. buf += board_ie_len;
  684. }
  685. /* no match found */
  686. ret = -ENOENT;
  687. out:
  688. return ret;
  689. }
  690. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  691. const char *boardname,
  692. const char *filename)
  693. {
  694. size_t len, magic_len, ie_len;
  695. struct ath10k_fw_ie *hdr;
  696. const u8 *data;
  697. int ret, ie_id;
  698. ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename);
  699. if (IS_ERR(ar->board))
  700. return PTR_ERR(ar->board);
  701. data = ar->board->data;
  702. len = ar->board->size;
  703. /* magic has extra null byte padded */
  704. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  705. if (len < magic_len) {
  706. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  707. ar->hw_params.fw.dir, filename, len);
  708. ret = -EINVAL;
  709. goto err;
  710. }
  711. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  712. ath10k_err(ar, "found invalid board magic\n");
  713. ret = -EINVAL;
  714. goto err;
  715. }
  716. /* magic is padded to 4 bytes */
  717. magic_len = ALIGN(magic_len, 4);
  718. if (len < magic_len) {
  719. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  720. ar->hw_params.fw.dir, filename, len);
  721. ret = -EINVAL;
  722. goto err;
  723. }
  724. data += magic_len;
  725. len -= magic_len;
  726. while (len > sizeof(struct ath10k_fw_ie)) {
  727. hdr = (struct ath10k_fw_ie *)data;
  728. ie_id = le32_to_cpu(hdr->id);
  729. ie_len = le32_to_cpu(hdr->len);
  730. len -= sizeof(*hdr);
  731. data = hdr->data;
  732. if (len < ALIGN(ie_len, 4)) {
  733. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  734. ie_id, ie_len, len);
  735. ret = -EINVAL;
  736. goto err;
  737. }
  738. switch (ie_id) {
  739. case ATH10K_BD_IE_BOARD:
  740. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  741. boardname);
  742. if (ret == -ENOENT)
  743. /* no match found, continue */
  744. break;
  745. else if (ret)
  746. /* there was an error, bail out */
  747. goto err;
  748. /* board data found */
  749. goto out;
  750. }
  751. /* jump over the padding */
  752. ie_len = ALIGN(ie_len, 4);
  753. len -= ie_len;
  754. data += ie_len;
  755. }
  756. out:
  757. if (!ar->board_data || !ar->board_len) {
  758. ath10k_err(ar,
  759. "failed to fetch board data for %s from %s/%s\n",
  760. boardname, ar->hw_params.fw.dir, filename);
  761. ret = -ENODATA;
  762. goto err;
  763. }
  764. return 0;
  765. err:
  766. ath10k_core_free_board_files(ar);
  767. return ret;
  768. }
  769. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  770. size_t name_len)
  771. {
  772. if (ar->id.bmi_ids_valid) {
  773. scnprintf(name, name_len,
  774. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  775. ath10k_bus_str(ar->hif.bus),
  776. ar->id.bmi_chip_id,
  777. ar->id.bmi_board_id);
  778. goto out;
  779. }
  780. scnprintf(name, name_len,
  781. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
  782. ath10k_bus_str(ar->hif.bus),
  783. ar->id.vendor, ar->id.device,
  784. ar->id.subsystem_vendor, ar->id.subsystem_device);
  785. out:
  786. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  787. return 0;
  788. }
  789. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  790. {
  791. char boardname[100];
  792. int ret;
  793. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  794. if (ret) {
  795. ath10k_err(ar, "failed to create board name: %d", ret);
  796. return ret;
  797. }
  798. ar->bd_api = 2;
  799. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  800. ATH10K_BOARD_API2_FILE);
  801. if (!ret)
  802. goto success;
  803. ar->bd_api = 1;
  804. ret = ath10k_core_fetch_board_data_api_1(ar);
  805. if (ret) {
  806. ath10k_err(ar, "failed to fetch board data\n");
  807. return ret;
  808. }
  809. success:
  810. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  811. return 0;
  812. }
  813. static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
  814. {
  815. int ret = 0;
  816. if (ar->hw_params.fw.fw == NULL) {
  817. ath10k_err(ar, "firmware file not defined\n");
  818. return -EINVAL;
  819. }
  820. ar->firmware = ath10k_fetch_fw_file(ar,
  821. ar->hw_params.fw.dir,
  822. ar->hw_params.fw.fw);
  823. if (IS_ERR(ar->firmware)) {
  824. ret = PTR_ERR(ar->firmware);
  825. ath10k_err(ar, "could not fetch firmware (%d)\n", ret);
  826. goto err;
  827. }
  828. ar->firmware_data = ar->firmware->data;
  829. ar->firmware_len = ar->firmware->size;
  830. /* OTP may be undefined. If so, don't fetch it at all */
  831. if (ar->hw_params.fw.otp == NULL)
  832. return 0;
  833. ar->otp = ath10k_fetch_fw_file(ar,
  834. ar->hw_params.fw.dir,
  835. ar->hw_params.fw.otp);
  836. if (IS_ERR(ar->otp)) {
  837. ret = PTR_ERR(ar->otp);
  838. ath10k_err(ar, "could not fetch otp (%d)\n", ret);
  839. goto err;
  840. }
  841. ar->otp_data = ar->otp->data;
  842. ar->otp_len = ar->otp->size;
  843. return 0;
  844. err:
  845. ath10k_core_free_firmware_files(ar);
  846. return ret;
  847. }
  848. static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
  849. {
  850. size_t magic_len, len, ie_len;
  851. int ie_id, i, index, bit, ret;
  852. struct ath10k_fw_ie *hdr;
  853. const u8 *data;
  854. __le32 *timestamp, *version;
  855. /* first fetch the firmware file (firmware-*.bin) */
  856. ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name);
  857. if (IS_ERR(ar->firmware)) {
  858. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  859. ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware));
  860. return PTR_ERR(ar->firmware);
  861. }
  862. data = ar->firmware->data;
  863. len = ar->firmware->size;
  864. /* magic also includes the null byte, check that as well */
  865. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  866. if (len < magic_len) {
  867. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  868. ar->hw_params.fw.dir, name, len);
  869. ret = -EINVAL;
  870. goto err;
  871. }
  872. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  873. ath10k_err(ar, "invalid firmware magic\n");
  874. ret = -EINVAL;
  875. goto err;
  876. }
  877. /* jump over the padding */
  878. magic_len = ALIGN(magic_len, 4);
  879. len -= magic_len;
  880. data += magic_len;
  881. /* loop elements */
  882. while (len > sizeof(struct ath10k_fw_ie)) {
  883. hdr = (struct ath10k_fw_ie *)data;
  884. ie_id = le32_to_cpu(hdr->id);
  885. ie_len = le32_to_cpu(hdr->len);
  886. len -= sizeof(*hdr);
  887. data += sizeof(*hdr);
  888. if (len < ie_len) {
  889. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  890. ie_id, len, ie_len);
  891. ret = -EINVAL;
  892. goto err;
  893. }
  894. switch (ie_id) {
  895. case ATH10K_FW_IE_FW_VERSION:
  896. if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1)
  897. break;
  898. memcpy(ar->hw->wiphy->fw_version, data, ie_len);
  899. ar->hw->wiphy->fw_version[ie_len] = '\0';
  900. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  901. "found fw version %s\n",
  902. ar->hw->wiphy->fw_version);
  903. break;
  904. case ATH10K_FW_IE_TIMESTAMP:
  905. if (ie_len != sizeof(u32))
  906. break;
  907. timestamp = (__le32 *)data;
  908. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  909. le32_to_cpup(timestamp));
  910. break;
  911. case ATH10K_FW_IE_FEATURES:
  912. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  913. "found firmware features ie (%zd B)\n",
  914. ie_len);
  915. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  916. index = i / 8;
  917. bit = i % 8;
  918. if (index == ie_len)
  919. break;
  920. if (data[index] & (1 << bit)) {
  921. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  922. "Enabling feature bit: %i\n",
  923. i);
  924. __set_bit(i, ar->fw_features);
  925. }
  926. }
  927. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  928. ar->fw_features,
  929. sizeof(ar->fw_features));
  930. break;
  931. case ATH10K_FW_IE_FW_IMAGE:
  932. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  933. "found fw image ie (%zd B)\n",
  934. ie_len);
  935. ar->firmware_data = data;
  936. ar->firmware_len = ie_len;
  937. break;
  938. case ATH10K_FW_IE_OTP_IMAGE:
  939. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  940. "found otp image ie (%zd B)\n",
  941. ie_len);
  942. ar->otp_data = data;
  943. ar->otp_len = ie_len;
  944. break;
  945. case ATH10K_FW_IE_WMI_OP_VERSION:
  946. if (ie_len != sizeof(u32))
  947. break;
  948. version = (__le32 *)data;
  949. ar->wmi.op_version = le32_to_cpup(version);
  950. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  951. ar->wmi.op_version);
  952. break;
  953. case ATH10K_FW_IE_HTT_OP_VERSION:
  954. if (ie_len != sizeof(u32))
  955. break;
  956. version = (__le32 *)data;
  957. ar->htt.op_version = le32_to_cpup(version);
  958. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  959. ar->htt.op_version);
  960. break;
  961. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  962. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  963. "found fw code swap image ie (%zd B)\n",
  964. ie_len);
  965. ar->swap.firmware_codeswap_data = data;
  966. ar->swap.firmware_codeswap_len = ie_len;
  967. break;
  968. default:
  969. ath10k_warn(ar, "Unknown FW IE: %u\n",
  970. le32_to_cpu(hdr->id));
  971. break;
  972. }
  973. /* jump over the padding */
  974. ie_len = ALIGN(ie_len, 4);
  975. len -= ie_len;
  976. data += ie_len;
  977. }
  978. if (!ar->firmware_data || !ar->firmware_len) {
  979. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  980. ar->hw_params.fw.dir, name);
  981. ret = -ENOMEDIUM;
  982. goto err;
  983. }
  984. return 0;
  985. err:
  986. ath10k_core_free_firmware_files(ar);
  987. return ret;
  988. }
  989. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  990. {
  991. int ret;
  992. /* calibration file is optional, don't check for any errors */
  993. ath10k_fetch_cal_file(ar);
  994. ar->fw_api = 5;
  995. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  996. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE);
  997. if (ret == 0)
  998. goto success;
  999. ar->fw_api = 4;
  1000. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1001. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE);
  1002. if (ret == 0)
  1003. goto success;
  1004. ar->fw_api = 3;
  1005. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1006. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE);
  1007. if (ret == 0)
  1008. goto success;
  1009. ar->fw_api = 2;
  1010. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1011. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE);
  1012. if (ret == 0)
  1013. goto success;
  1014. ar->fw_api = 1;
  1015. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1016. ret = ath10k_core_fetch_firmware_api_1(ar);
  1017. if (ret)
  1018. return ret;
  1019. success:
  1020. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1021. return 0;
  1022. }
  1023. static int ath10k_download_cal_data(struct ath10k *ar)
  1024. {
  1025. int ret;
  1026. ret = ath10k_download_cal_file(ar);
  1027. if (ret == 0) {
  1028. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1029. goto done;
  1030. }
  1031. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1032. "boot did not find a calibration file, try DT next: %d\n",
  1033. ret);
  1034. ret = ath10k_download_cal_dt(ar);
  1035. if (ret == 0) {
  1036. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1037. goto done;
  1038. }
  1039. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1040. "boot did not find DT entry, try OTP next: %d\n",
  1041. ret);
  1042. ret = ath10k_download_and_run_otp(ar);
  1043. if (ret) {
  1044. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1045. return ret;
  1046. }
  1047. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1048. done:
  1049. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1050. ath10k_cal_mode_str(ar->cal_mode));
  1051. return 0;
  1052. }
  1053. static int ath10k_init_uart(struct ath10k *ar)
  1054. {
  1055. int ret;
  1056. /*
  1057. * Explicitly setting UART prints to zero as target turns it on
  1058. * based on scratch registers.
  1059. */
  1060. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1061. if (ret) {
  1062. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1063. return ret;
  1064. }
  1065. if (!uart_print)
  1066. return 0;
  1067. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1068. if (ret) {
  1069. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1070. return ret;
  1071. }
  1072. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1073. if (ret) {
  1074. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1075. return ret;
  1076. }
  1077. /* Set the UART baud rate to 19200. */
  1078. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1079. if (ret) {
  1080. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1081. return ret;
  1082. }
  1083. ath10k_info(ar, "UART prints enabled\n");
  1084. return 0;
  1085. }
  1086. static int ath10k_init_hw_params(struct ath10k *ar)
  1087. {
  1088. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1089. int i;
  1090. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1091. hw_params = &ath10k_hw_params_list[i];
  1092. if (hw_params->id == ar->target_version &&
  1093. hw_params->dev_id == ar->dev_id)
  1094. break;
  1095. }
  1096. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1097. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1098. ar->target_version);
  1099. return -EINVAL;
  1100. }
  1101. ar->hw_params = *hw_params;
  1102. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1103. ar->hw_params.name, ar->target_version);
  1104. return 0;
  1105. }
  1106. static void ath10k_core_restart(struct work_struct *work)
  1107. {
  1108. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1109. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1110. /* Place a barrier to make sure the compiler doesn't reorder
  1111. * CRASH_FLUSH and calling other functions.
  1112. */
  1113. barrier();
  1114. ieee80211_stop_queues(ar->hw);
  1115. ath10k_drain_tx(ar);
  1116. complete_all(&ar->scan.started);
  1117. complete_all(&ar->scan.completed);
  1118. complete_all(&ar->scan.on_channel);
  1119. complete_all(&ar->offchan_tx_completed);
  1120. complete_all(&ar->install_key_done);
  1121. complete_all(&ar->vdev_setup_done);
  1122. complete_all(&ar->thermal.wmi_sync);
  1123. wake_up(&ar->htt.empty_tx_wq);
  1124. wake_up(&ar->wmi.tx_credits_wq);
  1125. wake_up(&ar->peer_mapping_wq);
  1126. mutex_lock(&ar->conf_mutex);
  1127. switch (ar->state) {
  1128. case ATH10K_STATE_ON:
  1129. ar->state = ATH10K_STATE_RESTARTING;
  1130. ath10k_hif_stop(ar);
  1131. ath10k_scan_finish(ar);
  1132. ieee80211_restart_hw(ar->hw);
  1133. break;
  1134. case ATH10K_STATE_OFF:
  1135. /* this can happen if driver is being unloaded
  1136. * or if the crash happens during FW probing */
  1137. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1138. break;
  1139. case ATH10K_STATE_RESTARTING:
  1140. /* hw restart might be requested from multiple places */
  1141. break;
  1142. case ATH10K_STATE_RESTARTED:
  1143. ar->state = ATH10K_STATE_WEDGED;
  1144. /* fall through */
  1145. case ATH10K_STATE_WEDGED:
  1146. ath10k_warn(ar, "device is wedged, will not restart\n");
  1147. break;
  1148. case ATH10K_STATE_UTF:
  1149. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1150. break;
  1151. }
  1152. mutex_unlock(&ar->conf_mutex);
  1153. }
  1154. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1155. {
  1156. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) &&
  1157. !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  1158. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1159. return -EINVAL;
  1160. }
  1161. if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1162. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1163. ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version);
  1164. return -EINVAL;
  1165. }
  1166. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1167. switch (ath10k_cryptmode_param) {
  1168. case ATH10K_CRYPT_MODE_HW:
  1169. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1170. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1171. break;
  1172. case ATH10K_CRYPT_MODE_SW:
  1173. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1174. ar->fw_features)) {
  1175. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1176. return -EINVAL;
  1177. }
  1178. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1179. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1180. break;
  1181. default:
  1182. ath10k_info(ar, "invalid cryptmode: %d\n",
  1183. ath10k_cryptmode_param);
  1184. return -EINVAL;
  1185. }
  1186. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1187. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1188. if (rawmode) {
  1189. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1190. ar->fw_features)) {
  1191. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1192. return -EINVAL;
  1193. }
  1194. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1195. }
  1196. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1197. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1198. /* Workaround:
  1199. *
  1200. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1201. * and causes enormous performance issues (malformed frames,
  1202. * etc).
  1203. *
  1204. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1205. * albeit a bit slower compared to regular operation.
  1206. */
  1207. ar->htt.max_num_amsdu = 1;
  1208. }
  1209. /* Backwards compatibility for firmwares without
  1210. * ATH10K_FW_IE_WMI_OP_VERSION.
  1211. */
  1212. if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1213. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  1214. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1215. ar->fw_features))
  1216. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1217. else
  1218. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1219. } else {
  1220. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1221. }
  1222. }
  1223. switch (ar->wmi.op_version) {
  1224. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1225. ar->max_num_peers = TARGET_NUM_PEERS;
  1226. ar->max_num_stations = TARGET_NUM_STATIONS;
  1227. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1228. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1229. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1230. WMI_STAT_PEER;
  1231. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1232. break;
  1233. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1234. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1235. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1236. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1237. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1238. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1239. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1240. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1241. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1242. break;
  1243. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1244. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1245. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1246. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1247. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1248. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1249. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1250. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1251. WMI_STAT_PEER;
  1252. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1253. break;
  1254. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1255. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1256. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1257. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1258. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1259. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1260. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  1261. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1262. ar->max_spatial_stream = WMI_10_4_MAX_SPATIAL_STREAM;
  1263. break;
  1264. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1265. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1266. WARN_ON(1);
  1267. return -EINVAL;
  1268. }
  1269. /* Backwards compatibility for firmwares without
  1270. * ATH10K_FW_IE_HTT_OP_VERSION.
  1271. */
  1272. if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1273. switch (ar->wmi.op_version) {
  1274. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1275. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1276. break;
  1277. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1278. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1279. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1280. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1281. break;
  1282. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1283. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1284. break;
  1285. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1286. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1287. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1288. WARN_ON(1);
  1289. return -EINVAL;
  1290. }
  1291. }
  1292. return 0;
  1293. }
  1294. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode)
  1295. {
  1296. int status;
  1297. lockdep_assert_held(&ar->conf_mutex);
  1298. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1299. ath10k_bmi_start(ar);
  1300. if (ath10k_init_configure_target(ar)) {
  1301. status = -EINVAL;
  1302. goto err;
  1303. }
  1304. status = ath10k_download_cal_data(ar);
  1305. if (status)
  1306. goto err;
  1307. /* Some of of qca988x solutions are having global reset issue
  1308. * during target initialization. Bypassing PLL setting before
  1309. * downloading firmware and letting the SoC run on REF_CLK is
  1310. * fixing the problem. Corresponding firmware change is also needed
  1311. * to set the clock source once the target is initialized.
  1312. */
  1313. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1314. ar->fw_features)) {
  1315. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1316. if (status) {
  1317. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1318. status);
  1319. goto err;
  1320. }
  1321. }
  1322. status = ath10k_download_fw(ar, mode);
  1323. if (status)
  1324. goto err;
  1325. status = ath10k_init_uart(ar);
  1326. if (status)
  1327. goto err;
  1328. ar->htc.htc_ops.target_send_suspend_complete =
  1329. ath10k_send_suspend_complete;
  1330. status = ath10k_htc_init(ar);
  1331. if (status) {
  1332. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1333. goto err;
  1334. }
  1335. status = ath10k_bmi_done(ar);
  1336. if (status)
  1337. goto err;
  1338. status = ath10k_wmi_attach(ar);
  1339. if (status) {
  1340. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1341. goto err;
  1342. }
  1343. status = ath10k_htt_init(ar);
  1344. if (status) {
  1345. ath10k_err(ar, "failed to init htt: %d\n", status);
  1346. goto err_wmi_detach;
  1347. }
  1348. status = ath10k_htt_tx_alloc(&ar->htt);
  1349. if (status) {
  1350. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1351. goto err_wmi_detach;
  1352. }
  1353. status = ath10k_htt_rx_alloc(&ar->htt);
  1354. if (status) {
  1355. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1356. goto err_htt_tx_detach;
  1357. }
  1358. status = ath10k_hif_start(ar);
  1359. if (status) {
  1360. ath10k_err(ar, "could not start HIF: %d\n", status);
  1361. goto err_htt_rx_detach;
  1362. }
  1363. status = ath10k_htc_wait_target(&ar->htc);
  1364. if (status) {
  1365. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1366. goto err_hif_stop;
  1367. }
  1368. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1369. status = ath10k_htt_connect(&ar->htt);
  1370. if (status) {
  1371. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1372. goto err_hif_stop;
  1373. }
  1374. }
  1375. status = ath10k_wmi_connect(ar);
  1376. if (status) {
  1377. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1378. goto err_hif_stop;
  1379. }
  1380. status = ath10k_htc_start(&ar->htc);
  1381. if (status) {
  1382. ath10k_err(ar, "failed to start htc: %d\n", status);
  1383. goto err_hif_stop;
  1384. }
  1385. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1386. status = ath10k_wmi_wait_for_service_ready(ar);
  1387. if (status) {
  1388. ath10k_warn(ar, "wmi service ready event not received");
  1389. goto err_hif_stop;
  1390. }
  1391. }
  1392. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1393. ar->hw->wiphy->fw_version);
  1394. status = ath10k_wmi_cmd_init(ar);
  1395. if (status) {
  1396. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1397. status);
  1398. goto err_hif_stop;
  1399. }
  1400. status = ath10k_wmi_wait_for_unified_ready(ar);
  1401. if (status) {
  1402. ath10k_err(ar, "wmi unified ready event not received\n");
  1403. goto err_hif_stop;
  1404. }
  1405. /* If firmware indicates Full Rx Reorder support it must be used in a
  1406. * slightly different manner. Let HTT code know.
  1407. */
  1408. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1409. ar->wmi.svc_map));
  1410. status = ath10k_htt_rx_ring_refill(ar);
  1411. if (status) {
  1412. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1413. goto err_hif_stop;
  1414. }
  1415. /* we don't care about HTT in UTF mode */
  1416. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1417. status = ath10k_htt_setup(&ar->htt);
  1418. if (status) {
  1419. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1420. goto err_hif_stop;
  1421. }
  1422. }
  1423. status = ath10k_debug_start(ar);
  1424. if (status)
  1425. goto err_hif_stop;
  1426. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1427. INIT_LIST_HEAD(&ar->arvifs);
  1428. return 0;
  1429. err_hif_stop:
  1430. ath10k_hif_stop(ar);
  1431. err_htt_rx_detach:
  1432. ath10k_htt_rx_free(&ar->htt);
  1433. err_htt_tx_detach:
  1434. ath10k_htt_tx_free(&ar->htt);
  1435. err_wmi_detach:
  1436. ath10k_wmi_detach(ar);
  1437. err:
  1438. return status;
  1439. }
  1440. EXPORT_SYMBOL(ath10k_core_start);
  1441. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1442. {
  1443. int ret;
  1444. unsigned long time_left;
  1445. reinit_completion(&ar->target_suspend);
  1446. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1447. if (ret) {
  1448. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1449. return ret;
  1450. }
  1451. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1452. if (!time_left) {
  1453. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1454. return -ETIMEDOUT;
  1455. }
  1456. return 0;
  1457. }
  1458. void ath10k_core_stop(struct ath10k *ar)
  1459. {
  1460. lockdep_assert_held(&ar->conf_mutex);
  1461. ath10k_debug_stop(ar);
  1462. /* try to suspend target */
  1463. if (ar->state != ATH10K_STATE_RESTARTING &&
  1464. ar->state != ATH10K_STATE_UTF)
  1465. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1466. ath10k_hif_stop(ar);
  1467. ath10k_htt_tx_free(&ar->htt);
  1468. ath10k_htt_rx_free(&ar->htt);
  1469. ath10k_wmi_detach(ar);
  1470. }
  1471. EXPORT_SYMBOL(ath10k_core_stop);
  1472. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1473. * order to know what hw capabilities should be advertised to mac80211 it is
  1474. * necessary to load the firmware (and tear it down immediately since start
  1475. * hook will try to init it again) before registering */
  1476. static int ath10k_core_probe_fw(struct ath10k *ar)
  1477. {
  1478. struct bmi_target_info target_info;
  1479. int ret = 0;
  1480. ret = ath10k_hif_power_up(ar);
  1481. if (ret) {
  1482. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1483. return ret;
  1484. }
  1485. memset(&target_info, 0, sizeof(target_info));
  1486. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1487. if (ret) {
  1488. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1489. goto err_power_down;
  1490. }
  1491. ar->target_version = target_info.version;
  1492. ar->hw->wiphy->hw_version = target_info.version;
  1493. ret = ath10k_init_hw_params(ar);
  1494. if (ret) {
  1495. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1496. goto err_power_down;
  1497. }
  1498. ret = ath10k_core_fetch_firmware_files(ar);
  1499. if (ret) {
  1500. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1501. goto err_power_down;
  1502. }
  1503. ath10k_debug_print_hwfw_info(ar);
  1504. ret = ath10k_core_get_board_id_from_otp(ar);
  1505. if (ret && ret != -EOPNOTSUPP) {
  1506. ath10k_err(ar, "failed to get board id from otp: %d\n",
  1507. ret);
  1508. return ret;
  1509. }
  1510. ret = ath10k_core_fetch_board_file(ar);
  1511. if (ret) {
  1512. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1513. goto err_free_firmware_files;
  1514. }
  1515. ath10k_debug_print_board_info(ar);
  1516. ret = ath10k_core_init_firmware_features(ar);
  1517. if (ret) {
  1518. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1519. ret);
  1520. goto err_free_firmware_files;
  1521. }
  1522. ret = ath10k_swap_code_seg_init(ar);
  1523. if (ret) {
  1524. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1525. ret);
  1526. goto err_free_firmware_files;
  1527. }
  1528. mutex_lock(&ar->conf_mutex);
  1529. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL);
  1530. if (ret) {
  1531. ath10k_err(ar, "could not init core (%d)\n", ret);
  1532. goto err_unlock;
  1533. }
  1534. ath10k_debug_print_boot_info(ar);
  1535. ath10k_core_stop(ar);
  1536. mutex_unlock(&ar->conf_mutex);
  1537. ath10k_hif_power_down(ar);
  1538. return 0;
  1539. err_unlock:
  1540. mutex_unlock(&ar->conf_mutex);
  1541. err_free_firmware_files:
  1542. ath10k_core_free_firmware_files(ar);
  1543. err_power_down:
  1544. ath10k_hif_power_down(ar);
  1545. return ret;
  1546. }
  1547. static void ath10k_core_register_work(struct work_struct *work)
  1548. {
  1549. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1550. int status;
  1551. status = ath10k_core_probe_fw(ar);
  1552. if (status) {
  1553. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1554. goto err;
  1555. }
  1556. status = ath10k_mac_register(ar);
  1557. if (status) {
  1558. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1559. goto err_release_fw;
  1560. }
  1561. status = ath10k_debug_register(ar);
  1562. if (status) {
  1563. ath10k_err(ar, "unable to initialize debugfs\n");
  1564. goto err_unregister_mac;
  1565. }
  1566. status = ath10k_spectral_create(ar);
  1567. if (status) {
  1568. ath10k_err(ar, "failed to initialize spectral\n");
  1569. goto err_debug_destroy;
  1570. }
  1571. status = ath10k_thermal_register(ar);
  1572. if (status) {
  1573. ath10k_err(ar, "could not register thermal device: %d\n",
  1574. status);
  1575. goto err_spectral_destroy;
  1576. }
  1577. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1578. return;
  1579. err_spectral_destroy:
  1580. ath10k_spectral_destroy(ar);
  1581. err_debug_destroy:
  1582. ath10k_debug_destroy(ar);
  1583. err_unregister_mac:
  1584. ath10k_mac_unregister(ar);
  1585. err_release_fw:
  1586. ath10k_core_free_firmware_files(ar);
  1587. err:
  1588. /* TODO: It's probably a good idea to release device from the driver
  1589. * but calling device_release_driver() here will cause a deadlock.
  1590. */
  1591. return;
  1592. }
  1593. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1594. {
  1595. ar->chip_id = chip_id;
  1596. queue_work(ar->workqueue, &ar->register_work);
  1597. return 0;
  1598. }
  1599. EXPORT_SYMBOL(ath10k_core_register);
  1600. void ath10k_core_unregister(struct ath10k *ar)
  1601. {
  1602. cancel_work_sync(&ar->register_work);
  1603. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1604. return;
  1605. ath10k_thermal_unregister(ar);
  1606. /* Stop spectral before unregistering from mac80211 to remove the
  1607. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1608. * would be already be free'd recursively, leading to a double free.
  1609. */
  1610. ath10k_spectral_destroy(ar);
  1611. /* We must unregister from mac80211 before we stop HTC and HIF.
  1612. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1613. * unhappy about callback failures. */
  1614. ath10k_mac_unregister(ar);
  1615. ath10k_testmode_destroy(ar);
  1616. ath10k_core_free_firmware_files(ar);
  1617. ath10k_core_free_board_files(ar);
  1618. ath10k_debug_unregister(ar);
  1619. }
  1620. EXPORT_SYMBOL(ath10k_core_unregister);
  1621. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1622. enum ath10k_bus bus,
  1623. enum ath10k_hw_rev hw_rev,
  1624. const struct ath10k_hif_ops *hif_ops)
  1625. {
  1626. struct ath10k *ar;
  1627. int ret;
  1628. ar = ath10k_mac_create(priv_size);
  1629. if (!ar)
  1630. return NULL;
  1631. ar->ath_common.priv = ar;
  1632. ar->ath_common.hw = ar->hw;
  1633. ar->dev = dev;
  1634. ar->hw_rev = hw_rev;
  1635. ar->hif.ops = hif_ops;
  1636. ar->hif.bus = bus;
  1637. switch (hw_rev) {
  1638. case ATH10K_HW_QCA988X:
  1639. ar->regs = &qca988x_regs;
  1640. ar->hw_values = &qca988x_values;
  1641. break;
  1642. case ATH10K_HW_QCA6174:
  1643. case ATH10K_HW_QCA9377:
  1644. ar->regs = &qca6174_regs;
  1645. ar->hw_values = &qca6174_values;
  1646. break;
  1647. case ATH10K_HW_QCA99X0:
  1648. ar->regs = &qca99x0_regs;
  1649. ar->hw_values = &qca99x0_values;
  1650. break;
  1651. default:
  1652. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1653. hw_rev);
  1654. ret = -ENOTSUPP;
  1655. goto err_free_mac;
  1656. }
  1657. init_completion(&ar->scan.started);
  1658. init_completion(&ar->scan.completed);
  1659. init_completion(&ar->scan.on_channel);
  1660. init_completion(&ar->target_suspend);
  1661. init_completion(&ar->wow.wakeup_completed);
  1662. init_completion(&ar->install_key_done);
  1663. init_completion(&ar->vdev_setup_done);
  1664. init_completion(&ar->thermal.wmi_sync);
  1665. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1666. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1667. if (!ar->workqueue)
  1668. goto err_free_mac;
  1669. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1670. if (!ar->workqueue_aux)
  1671. goto err_free_wq;
  1672. mutex_init(&ar->conf_mutex);
  1673. spin_lock_init(&ar->data_lock);
  1674. INIT_LIST_HEAD(&ar->peers);
  1675. init_waitqueue_head(&ar->peer_mapping_wq);
  1676. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1677. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1678. init_completion(&ar->offchan_tx_completed);
  1679. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1680. skb_queue_head_init(&ar->offchan_tx_queue);
  1681. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1682. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1683. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1684. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1685. ret = ath10k_debug_create(ar);
  1686. if (ret)
  1687. goto err_free_aux_wq;
  1688. return ar;
  1689. err_free_aux_wq:
  1690. destroy_workqueue(ar->workqueue_aux);
  1691. err_free_wq:
  1692. destroy_workqueue(ar->workqueue);
  1693. err_free_mac:
  1694. ath10k_mac_destroy(ar);
  1695. return NULL;
  1696. }
  1697. EXPORT_SYMBOL(ath10k_core_create);
  1698. void ath10k_core_destroy(struct ath10k *ar)
  1699. {
  1700. flush_workqueue(ar->workqueue);
  1701. destroy_workqueue(ar->workqueue);
  1702. flush_workqueue(ar->workqueue_aux);
  1703. destroy_workqueue(ar->workqueue_aux);
  1704. ath10k_debug_destroy(ar);
  1705. ath10k_wmi_free_host_mem(ar);
  1706. ath10k_mac_destroy(ar);
  1707. }
  1708. EXPORT_SYMBOL(ath10k_core_destroy);
  1709. MODULE_AUTHOR("Qualcomm Atheros");
  1710. MODULE_DESCRIPTION("Core module for QCA988X PCIe devices.");
  1711. MODULE_LICENSE("Dual BSD/GPL");