i40e_adminq_cmd.h 70 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 - 2014 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program. If not, see <http://www.gnu.org/licenses/>.
  17. *
  18. * The full GNU General Public License is included in this distribution in
  19. * the file called "COPYING".
  20. *
  21. * Contact Information:
  22. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. ******************************************************************************/
  26. #ifndef _I40E_ADMINQ_CMD_H_
  27. #define _I40E_ADMINQ_CMD_H_
  28. /* This header file defines the i40e Admin Queue commands and is shared between
  29. * i40e Firmware and Software.
  30. *
  31. * This file needs to comply with the Linux Kernel coding style.
  32. */
  33. #define I40E_FW_API_VERSION_MAJOR 0x0001
  34. #define I40E_FW_API_VERSION_MINOR 0x0004
  35. struct i40e_aq_desc {
  36. __le16 flags;
  37. __le16 opcode;
  38. __le16 datalen;
  39. __le16 retval;
  40. __le32 cookie_high;
  41. __le32 cookie_low;
  42. union {
  43. struct {
  44. __le32 param0;
  45. __le32 param1;
  46. __le32 param2;
  47. __le32 param3;
  48. } internal;
  49. struct {
  50. __le32 param0;
  51. __le32 param1;
  52. __le32 addr_high;
  53. __le32 addr_low;
  54. } external;
  55. u8 raw[16];
  56. } params;
  57. };
  58. /* Flags sub-structure
  59. * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
  60. * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  61. */
  62. /* command flags and offsets*/
  63. #define I40E_AQ_FLAG_DD_SHIFT 0
  64. #define I40E_AQ_FLAG_CMP_SHIFT 1
  65. #define I40E_AQ_FLAG_ERR_SHIFT 2
  66. #define I40E_AQ_FLAG_VFE_SHIFT 3
  67. #define I40E_AQ_FLAG_LB_SHIFT 9
  68. #define I40E_AQ_FLAG_RD_SHIFT 10
  69. #define I40E_AQ_FLAG_VFC_SHIFT 11
  70. #define I40E_AQ_FLAG_BUF_SHIFT 12
  71. #define I40E_AQ_FLAG_SI_SHIFT 13
  72. #define I40E_AQ_FLAG_EI_SHIFT 14
  73. #define I40E_AQ_FLAG_FE_SHIFT 15
  74. #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
  75. #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
  76. #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
  77. #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
  78. #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
  79. #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
  80. #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
  81. #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  82. #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
  83. #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
  84. #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
  85. /* error codes */
  86. enum i40e_admin_queue_err {
  87. I40E_AQ_RC_OK = 0, /* success */
  88. I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
  89. I40E_AQ_RC_ENOENT = 2, /* No such element */
  90. I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
  91. I40E_AQ_RC_EINTR = 4, /* operation interrupted */
  92. I40E_AQ_RC_EIO = 5, /* I/O error */
  93. I40E_AQ_RC_ENXIO = 6, /* No such resource */
  94. I40E_AQ_RC_E2BIG = 7, /* Arg too long */
  95. I40E_AQ_RC_EAGAIN = 8, /* Try again */
  96. I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
  97. I40E_AQ_RC_EACCES = 10, /* Permission denied */
  98. I40E_AQ_RC_EFAULT = 11, /* Bad address */
  99. I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
  100. I40E_AQ_RC_EEXIST = 13, /* object already exists */
  101. I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
  102. I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
  103. I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
  104. I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
  105. I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
  106. I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
  107. I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
  108. I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
  109. I40E_AQ_RC_EFBIG = 22, /* File too large */
  110. };
  111. /* Admin Queue command opcodes */
  112. enum i40e_admin_queue_opc {
  113. /* aq commands */
  114. i40e_aqc_opc_get_version = 0x0001,
  115. i40e_aqc_opc_driver_version = 0x0002,
  116. i40e_aqc_opc_queue_shutdown = 0x0003,
  117. i40e_aqc_opc_set_pf_context = 0x0004,
  118. /* resource ownership */
  119. i40e_aqc_opc_request_resource = 0x0008,
  120. i40e_aqc_opc_release_resource = 0x0009,
  121. i40e_aqc_opc_list_func_capabilities = 0x000A,
  122. i40e_aqc_opc_list_dev_capabilities = 0x000B,
  123. /* LAA */
  124. i40e_aqc_opc_mac_address_read = 0x0107,
  125. i40e_aqc_opc_mac_address_write = 0x0108,
  126. /* PXE */
  127. i40e_aqc_opc_clear_pxe_mode = 0x0110,
  128. /* internal switch commands */
  129. i40e_aqc_opc_get_switch_config = 0x0200,
  130. i40e_aqc_opc_add_statistics = 0x0201,
  131. i40e_aqc_opc_remove_statistics = 0x0202,
  132. i40e_aqc_opc_set_port_parameters = 0x0203,
  133. i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
  134. i40e_aqc_opc_add_vsi = 0x0210,
  135. i40e_aqc_opc_update_vsi_parameters = 0x0211,
  136. i40e_aqc_opc_get_vsi_parameters = 0x0212,
  137. i40e_aqc_opc_add_pv = 0x0220,
  138. i40e_aqc_opc_update_pv_parameters = 0x0221,
  139. i40e_aqc_opc_get_pv_parameters = 0x0222,
  140. i40e_aqc_opc_add_veb = 0x0230,
  141. i40e_aqc_opc_update_veb_parameters = 0x0231,
  142. i40e_aqc_opc_get_veb_parameters = 0x0232,
  143. i40e_aqc_opc_delete_element = 0x0243,
  144. i40e_aqc_opc_add_macvlan = 0x0250,
  145. i40e_aqc_opc_remove_macvlan = 0x0251,
  146. i40e_aqc_opc_add_vlan = 0x0252,
  147. i40e_aqc_opc_remove_vlan = 0x0253,
  148. i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
  149. i40e_aqc_opc_add_tag = 0x0255,
  150. i40e_aqc_opc_remove_tag = 0x0256,
  151. i40e_aqc_opc_add_multicast_etag = 0x0257,
  152. i40e_aqc_opc_remove_multicast_etag = 0x0258,
  153. i40e_aqc_opc_update_tag = 0x0259,
  154. i40e_aqc_opc_add_control_packet_filter = 0x025A,
  155. i40e_aqc_opc_remove_control_packet_filter = 0x025B,
  156. i40e_aqc_opc_add_cloud_filters = 0x025C,
  157. i40e_aqc_opc_remove_cloud_filters = 0x025D,
  158. i40e_aqc_opc_add_mirror_rule = 0x0260,
  159. i40e_aqc_opc_delete_mirror_rule = 0x0261,
  160. /* DCB commands */
  161. i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
  162. i40e_aqc_opc_dcb_updated = 0x0302,
  163. /* TX scheduler */
  164. i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
  165. i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
  166. i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
  167. i40e_aqc_opc_query_vsi_bw_config = 0x0408,
  168. i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
  169. i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
  170. i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
  171. i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
  172. i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
  173. i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
  174. i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
  175. i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
  176. i40e_aqc_opc_query_port_ets_config = 0x0419,
  177. i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
  178. i40e_aqc_opc_suspend_port_tx = 0x041B,
  179. i40e_aqc_opc_resume_port_tx = 0x041C,
  180. i40e_aqc_opc_configure_partition_bw = 0x041D,
  181. /* hmc */
  182. i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
  183. i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
  184. /* phy commands*/
  185. i40e_aqc_opc_get_phy_abilities = 0x0600,
  186. i40e_aqc_opc_set_phy_config = 0x0601,
  187. i40e_aqc_opc_set_mac_config = 0x0603,
  188. i40e_aqc_opc_set_link_restart_an = 0x0605,
  189. i40e_aqc_opc_get_link_status = 0x0607,
  190. i40e_aqc_opc_set_phy_int_mask = 0x0613,
  191. i40e_aqc_opc_get_local_advt_reg = 0x0614,
  192. i40e_aqc_opc_set_local_advt_reg = 0x0615,
  193. i40e_aqc_opc_get_partner_advt = 0x0616,
  194. i40e_aqc_opc_set_lb_modes = 0x0618,
  195. i40e_aqc_opc_get_phy_wol_caps = 0x0621,
  196. i40e_aqc_opc_set_phy_debug = 0x0622,
  197. i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
  198. /* NVM commands */
  199. i40e_aqc_opc_nvm_read = 0x0701,
  200. i40e_aqc_opc_nvm_erase = 0x0702,
  201. i40e_aqc_opc_nvm_update = 0x0703,
  202. i40e_aqc_opc_nvm_config_read = 0x0704,
  203. i40e_aqc_opc_nvm_config_write = 0x0705,
  204. i40e_aqc_opc_oem_post_update = 0x0720,
  205. /* virtualization commands */
  206. i40e_aqc_opc_send_msg_to_pf = 0x0801,
  207. i40e_aqc_opc_send_msg_to_vf = 0x0802,
  208. i40e_aqc_opc_send_msg_to_peer = 0x0803,
  209. /* alternate structure */
  210. i40e_aqc_opc_alternate_write = 0x0900,
  211. i40e_aqc_opc_alternate_write_indirect = 0x0901,
  212. i40e_aqc_opc_alternate_read = 0x0902,
  213. i40e_aqc_opc_alternate_read_indirect = 0x0903,
  214. i40e_aqc_opc_alternate_write_done = 0x0904,
  215. i40e_aqc_opc_alternate_set_mode = 0x0905,
  216. i40e_aqc_opc_alternate_clear_port = 0x0906,
  217. /* LLDP commands */
  218. i40e_aqc_opc_lldp_get_mib = 0x0A00,
  219. i40e_aqc_opc_lldp_update_mib = 0x0A01,
  220. i40e_aqc_opc_lldp_add_tlv = 0x0A02,
  221. i40e_aqc_opc_lldp_update_tlv = 0x0A03,
  222. i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
  223. i40e_aqc_opc_lldp_stop = 0x0A05,
  224. i40e_aqc_opc_lldp_start = 0x0A06,
  225. i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
  226. i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
  227. i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
  228. /* Tunnel commands */
  229. i40e_aqc_opc_add_udp_tunnel = 0x0B00,
  230. i40e_aqc_opc_del_udp_tunnel = 0x0B01,
  231. i40e_aqc_opc_set_rss_key = 0x0B02,
  232. i40e_aqc_opc_set_rss_lut = 0x0B03,
  233. i40e_aqc_opc_get_rss_key = 0x0B04,
  234. i40e_aqc_opc_get_rss_lut = 0x0B05,
  235. /* Async Events */
  236. i40e_aqc_opc_event_lan_overflow = 0x1001,
  237. /* OEM commands */
  238. i40e_aqc_opc_oem_parameter_change = 0xFE00,
  239. i40e_aqc_opc_oem_device_status_change = 0xFE01,
  240. i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
  241. i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
  242. /* debug commands */
  243. i40e_aqc_opc_debug_read_reg = 0xFF03,
  244. i40e_aqc_opc_debug_write_reg = 0xFF04,
  245. i40e_aqc_opc_debug_modify_reg = 0xFF07,
  246. i40e_aqc_opc_debug_dump_internals = 0xFF08,
  247. };
  248. /* command structures and indirect data structures */
  249. /* Structure naming conventions:
  250. * - no suffix for direct command descriptor structures
  251. * - _data for indirect sent data
  252. * - _resp for indirect return data (data which is both will use _data)
  253. * - _completion for direct return data
  254. * - _element_ for repeated elements (may also be _data or _resp)
  255. *
  256. * Command structures are expected to overlay the params.raw member of the basic
  257. * descriptor, and as such cannot exceed 16 bytes in length.
  258. */
  259. /* This macro is used to generate a compilation error if a structure
  260. * is not exactly the correct length. It gives a divide by zero error if the
  261. * structure is not of the correct size, otherwise it creates an enum that is
  262. * never used.
  263. */
  264. #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
  265. { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
  266. /* This macro is used extensively to ensure that command structures are 16
  267. * bytes in length as they have to map to the raw array of that size.
  268. */
  269. #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
  270. /* internal (0x00XX) commands */
  271. /* Get version (direct 0x0001) */
  272. struct i40e_aqc_get_version {
  273. __le32 rom_ver;
  274. __le32 fw_build;
  275. __le16 fw_major;
  276. __le16 fw_minor;
  277. __le16 api_major;
  278. __le16 api_minor;
  279. };
  280. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
  281. /* Send driver version (indirect 0x0002) */
  282. struct i40e_aqc_driver_version {
  283. u8 driver_major_ver;
  284. u8 driver_minor_ver;
  285. u8 driver_build_ver;
  286. u8 driver_subbuild_ver;
  287. u8 reserved[4];
  288. __le32 address_high;
  289. __le32 address_low;
  290. };
  291. I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
  292. /* Queue Shutdown (direct 0x0003) */
  293. struct i40e_aqc_queue_shutdown {
  294. __le32 driver_unloading;
  295. #define I40E_AQ_DRIVER_UNLOADING 0x1
  296. u8 reserved[12];
  297. };
  298. I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
  299. /* Set PF context (0x0004, direct) */
  300. struct i40e_aqc_set_pf_context {
  301. u8 pf_id;
  302. u8 reserved[15];
  303. };
  304. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
  305. /* Request resource ownership (direct 0x0008)
  306. * Release resource ownership (direct 0x0009)
  307. */
  308. #define I40E_AQ_RESOURCE_NVM 1
  309. #define I40E_AQ_RESOURCE_SDP 2
  310. #define I40E_AQ_RESOURCE_ACCESS_READ 1
  311. #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
  312. #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
  313. #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
  314. struct i40e_aqc_request_resource {
  315. __le16 resource_id;
  316. __le16 access_type;
  317. __le32 timeout;
  318. __le32 resource_number;
  319. u8 reserved[4];
  320. };
  321. I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
  322. /* Get function capabilities (indirect 0x000A)
  323. * Get device capabilities (indirect 0x000B)
  324. */
  325. struct i40e_aqc_list_capabilites {
  326. u8 command_flags;
  327. #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
  328. u8 pf_index;
  329. u8 reserved[2];
  330. __le32 count;
  331. __le32 addr_high;
  332. __le32 addr_low;
  333. };
  334. I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
  335. struct i40e_aqc_list_capabilities_element_resp {
  336. __le16 id;
  337. u8 major_rev;
  338. u8 minor_rev;
  339. __le32 number;
  340. __le32 logical_id;
  341. __le32 phys_id;
  342. u8 reserved[16];
  343. };
  344. /* list of caps */
  345. #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
  346. #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
  347. #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
  348. #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
  349. #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
  350. #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
  351. #define I40E_AQ_CAP_ID_SRIOV 0x0012
  352. #define I40E_AQ_CAP_ID_VF 0x0013
  353. #define I40E_AQ_CAP_ID_VMDQ 0x0014
  354. #define I40E_AQ_CAP_ID_8021QBG 0x0015
  355. #define I40E_AQ_CAP_ID_8021QBR 0x0016
  356. #define I40E_AQ_CAP_ID_VSI 0x0017
  357. #define I40E_AQ_CAP_ID_DCB 0x0018
  358. #define I40E_AQ_CAP_ID_FCOE 0x0021
  359. #define I40E_AQ_CAP_ID_ISCSI 0x0022
  360. #define I40E_AQ_CAP_ID_RSS 0x0040
  361. #define I40E_AQ_CAP_ID_RXQ 0x0041
  362. #define I40E_AQ_CAP_ID_TXQ 0x0042
  363. #define I40E_AQ_CAP_ID_MSIX 0x0043
  364. #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
  365. #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
  366. #define I40E_AQ_CAP_ID_1588 0x0046
  367. #define I40E_AQ_CAP_ID_IWARP 0x0051
  368. #define I40E_AQ_CAP_ID_LED 0x0061
  369. #define I40E_AQ_CAP_ID_SDP 0x0062
  370. #define I40E_AQ_CAP_ID_MDIO 0x0063
  371. #define I40E_AQ_CAP_ID_FLEX10 0x00F1
  372. #define I40E_AQ_CAP_ID_CEM 0x00F2
  373. /* Set CPPM Configuration (direct 0x0103) */
  374. struct i40e_aqc_cppm_configuration {
  375. __le16 command_flags;
  376. #define I40E_AQ_CPPM_EN_LTRC 0x0800
  377. #define I40E_AQ_CPPM_EN_DMCTH 0x1000
  378. #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
  379. #define I40E_AQ_CPPM_EN_HPTC 0x4000
  380. #define I40E_AQ_CPPM_EN_DMARC 0x8000
  381. __le16 ttlx;
  382. __le32 dmacr;
  383. __le16 dmcth;
  384. u8 hptc;
  385. u8 reserved;
  386. __le32 pfltrc;
  387. };
  388. I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
  389. /* Set ARP Proxy command / response (indirect 0x0104) */
  390. struct i40e_aqc_arp_proxy_data {
  391. __le16 command_flags;
  392. #define I40E_AQ_ARP_INIT_IPV4 0x0008
  393. #define I40E_AQ_ARP_UNSUP_CTL 0x0010
  394. #define I40E_AQ_ARP_ENA 0x0020
  395. #define I40E_AQ_ARP_ADD_IPV4 0x0040
  396. #define I40E_AQ_ARP_DEL_IPV4 0x0080
  397. __le16 table_id;
  398. __le32 pfpm_proxyfc;
  399. __le32 ip_addr;
  400. u8 mac_addr[6];
  401. u8 reserved[2];
  402. };
  403. I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
  404. /* Set NS Proxy Table Entry Command (indirect 0x0105) */
  405. struct i40e_aqc_ns_proxy_data {
  406. __le16 table_idx_mac_addr_0;
  407. __le16 table_idx_mac_addr_1;
  408. __le16 table_idx_ipv6_0;
  409. __le16 table_idx_ipv6_1;
  410. __le16 control;
  411. #define I40E_AQ_NS_PROXY_ADD_0 0x0100
  412. #define I40E_AQ_NS_PROXY_DEL_0 0x0200
  413. #define I40E_AQ_NS_PROXY_ADD_1 0x0400
  414. #define I40E_AQ_NS_PROXY_DEL_1 0x0800
  415. #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
  416. #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
  417. #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
  418. #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
  419. #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
  420. #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
  421. #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
  422. u8 mac_addr_0[6];
  423. u8 mac_addr_1[6];
  424. u8 local_mac_addr[6];
  425. u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
  426. u8 ipv6_addr_1[16];
  427. };
  428. I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
  429. /* Manage LAA Command (0x0106) - obsolete */
  430. struct i40e_aqc_mng_laa {
  431. __le16 command_flags;
  432. #define I40E_AQ_LAA_FLAG_WR 0x8000
  433. u8 reserved[2];
  434. __le32 sal;
  435. __le16 sah;
  436. u8 reserved2[6];
  437. };
  438. I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
  439. /* Manage MAC Address Read Command (indirect 0x0107) */
  440. struct i40e_aqc_mac_address_read {
  441. __le16 command_flags;
  442. #define I40E_AQC_LAN_ADDR_VALID 0x10
  443. #define I40E_AQC_SAN_ADDR_VALID 0x20
  444. #define I40E_AQC_PORT_ADDR_VALID 0x40
  445. #define I40E_AQC_WOL_ADDR_VALID 0x80
  446. #define I40E_AQC_MC_MAG_EN_VALID 0x100
  447. #define I40E_AQC_ADDR_VALID_MASK 0x1F0
  448. u8 reserved[6];
  449. __le32 addr_high;
  450. __le32 addr_low;
  451. };
  452. I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
  453. struct i40e_aqc_mac_address_read_data {
  454. u8 pf_lan_mac[6];
  455. u8 pf_san_mac[6];
  456. u8 port_mac[6];
  457. u8 pf_wol_mac[6];
  458. };
  459. I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
  460. /* Manage MAC Address Write Command (0x0108) */
  461. struct i40e_aqc_mac_address_write {
  462. __le16 command_flags;
  463. #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
  464. #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
  465. #define I40E_AQC_WRITE_TYPE_PORT 0x8000
  466. #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
  467. #define I40E_AQC_WRITE_TYPE_MASK 0xC000
  468. __le16 mac_sah;
  469. __le32 mac_sal;
  470. u8 reserved[8];
  471. };
  472. I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
  473. /* PXE commands (0x011x) */
  474. /* Clear PXE Command and response (direct 0x0110) */
  475. struct i40e_aqc_clear_pxe {
  476. u8 rx_cnt;
  477. u8 reserved[15];
  478. };
  479. I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
  480. /* Switch configuration commands (0x02xx) */
  481. /* Used by many indirect commands that only pass an seid and a buffer in the
  482. * command
  483. */
  484. struct i40e_aqc_switch_seid {
  485. __le16 seid;
  486. u8 reserved[6];
  487. __le32 addr_high;
  488. __le32 addr_low;
  489. };
  490. I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
  491. /* Get Switch Configuration command (indirect 0x0200)
  492. * uses i40e_aqc_switch_seid for the descriptor
  493. */
  494. struct i40e_aqc_get_switch_config_header_resp {
  495. __le16 num_reported;
  496. __le16 num_total;
  497. u8 reserved[12];
  498. };
  499. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
  500. struct i40e_aqc_switch_config_element_resp {
  501. u8 element_type;
  502. #define I40E_AQ_SW_ELEM_TYPE_MAC 1
  503. #define I40E_AQ_SW_ELEM_TYPE_PF 2
  504. #define I40E_AQ_SW_ELEM_TYPE_VF 3
  505. #define I40E_AQ_SW_ELEM_TYPE_EMP 4
  506. #define I40E_AQ_SW_ELEM_TYPE_BMC 5
  507. #define I40E_AQ_SW_ELEM_TYPE_PV 16
  508. #define I40E_AQ_SW_ELEM_TYPE_VEB 17
  509. #define I40E_AQ_SW_ELEM_TYPE_PA 18
  510. #define I40E_AQ_SW_ELEM_TYPE_VSI 19
  511. u8 revision;
  512. #define I40E_AQ_SW_ELEM_REV_1 1
  513. __le16 seid;
  514. __le16 uplink_seid;
  515. __le16 downlink_seid;
  516. u8 reserved[3];
  517. u8 connection_type;
  518. #define I40E_AQ_CONN_TYPE_REGULAR 0x1
  519. #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
  520. #define I40E_AQ_CONN_TYPE_CASCADED 0x3
  521. __le16 scheduler_id;
  522. __le16 element_info;
  523. };
  524. I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
  525. /* Get Switch Configuration (indirect 0x0200)
  526. * an array of elements are returned in the response buffer
  527. * the first in the array is the header, remainder are elements
  528. */
  529. struct i40e_aqc_get_switch_config_resp {
  530. struct i40e_aqc_get_switch_config_header_resp header;
  531. struct i40e_aqc_switch_config_element_resp element[1];
  532. };
  533. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
  534. /* Add Statistics (direct 0x0201)
  535. * Remove Statistics (direct 0x0202)
  536. */
  537. struct i40e_aqc_add_remove_statistics {
  538. __le16 seid;
  539. __le16 vlan;
  540. __le16 stat_index;
  541. u8 reserved[10];
  542. };
  543. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
  544. /* Set Port Parameters command (direct 0x0203) */
  545. struct i40e_aqc_set_port_parameters {
  546. __le16 command_flags;
  547. #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
  548. #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
  549. #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
  550. __le16 bad_frame_vsi;
  551. __le16 default_seid; /* reserved for command */
  552. u8 reserved[10];
  553. };
  554. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
  555. /* Get Switch Resource Allocation (indirect 0x0204) */
  556. struct i40e_aqc_get_switch_resource_alloc {
  557. u8 num_entries; /* reserved for command */
  558. u8 reserved[7];
  559. __le32 addr_high;
  560. __le32 addr_low;
  561. };
  562. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
  563. /* expect an array of these structs in the response buffer */
  564. struct i40e_aqc_switch_resource_alloc_element_resp {
  565. u8 resource_type;
  566. #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
  567. #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
  568. #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
  569. #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
  570. #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
  571. #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
  572. #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
  573. #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
  574. #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
  575. #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
  576. #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
  577. #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
  578. #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
  579. #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
  580. #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
  581. #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
  582. #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
  583. #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
  584. #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
  585. u8 reserved1;
  586. __le16 guaranteed;
  587. __le16 total;
  588. __le16 used;
  589. __le16 total_unalloced;
  590. u8 reserved2[6];
  591. };
  592. I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
  593. /* Add VSI (indirect 0x0210)
  594. * this indirect command uses struct i40e_aqc_vsi_properties_data
  595. * as the indirect buffer (128 bytes)
  596. *
  597. * Update VSI (indirect 0x211)
  598. * uses the same data structure as Add VSI
  599. *
  600. * Get VSI (indirect 0x0212)
  601. * uses the same completion and data structure as Add VSI
  602. */
  603. struct i40e_aqc_add_get_update_vsi {
  604. __le16 uplink_seid;
  605. u8 connection_type;
  606. #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
  607. #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
  608. #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
  609. u8 reserved1;
  610. u8 vf_id;
  611. u8 reserved2;
  612. __le16 vsi_flags;
  613. #define I40E_AQ_VSI_TYPE_SHIFT 0x0
  614. #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
  615. #define I40E_AQ_VSI_TYPE_VF 0x0
  616. #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
  617. #define I40E_AQ_VSI_TYPE_PF 0x2
  618. #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
  619. #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
  620. __le32 addr_high;
  621. __le32 addr_low;
  622. };
  623. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
  624. struct i40e_aqc_add_get_update_vsi_completion {
  625. __le16 seid;
  626. __le16 vsi_number;
  627. __le16 vsi_used;
  628. __le16 vsi_free;
  629. __le32 addr_high;
  630. __le32 addr_low;
  631. };
  632. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
  633. struct i40e_aqc_vsi_properties_data {
  634. /* first 96 byte are written by SW */
  635. __le16 valid_sections;
  636. #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
  637. #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
  638. #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
  639. #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
  640. #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
  641. #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
  642. #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
  643. #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
  644. #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
  645. #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
  646. /* switch section */
  647. __le16 switch_id; /* 12bit id combined with flags below */
  648. #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
  649. #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
  650. #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
  651. #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
  652. #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
  653. u8 sw_reserved[2];
  654. /* security section */
  655. u8 sec_flags;
  656. #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
  657. #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
  658. #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
  659. u8 sec_reserved;
  660. /* VLAN section */
  661. __le16 pvid; /* VLANS include priority bits */
  662. __le16 fcoe_pvid;
  663. u8 port_vlan_flags;
  664. #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
  665. #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
  666. I40E_AQ_VSI_PVLAN_MODE_SHIFT)
  667. #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
  668. #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
  669. #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
  670. #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
  671. #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
  672. #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
  673. I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
  674. #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
  675. #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
  676. #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
  677. #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
  678. u8 pvlan_reserved[3];
  679. /* ingress egress up sections */
  680. __le32 ingress_table; /* bitmap, 3 bits per up */
  681. #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
  682. #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
  683. I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
  684. #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
  685. #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
  686. I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
  687. #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
  688. #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
  689. I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
  690. #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
  691. #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
  692. I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
  693. #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
  694. #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
  695. I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
  696. #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
  697. #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
  698. I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
  699. #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
  700. #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
  701. I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
  702. #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
  703. #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
  704. I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
  705. __le32 egress_table; /* same defines as for ingress table */
  706. /* cascaded PV section */
  707. __le16 cas_pv_tag;
  708. u8 cas_pv_flags;
  709. #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
  710. #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
  711. I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
  712. #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
  713. #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
  714. #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
  715. #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
  716. #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
  717. #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
  718. u8 cas_pv_reserved;
  719. /* queue mapping section */
  720. __le16 mapping_flags;
  721. #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
  722. #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
  723. __le16 queue_mapping[16];
  724. #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
  725. #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
  726. __le16 tc_mapping[8];
  727. #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
  728. #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
  729. I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
  730. #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
  731. #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
  732. I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
  733. /* queueing option section */
  734. u8 queueing_opt_flags;
  735. #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
  736. #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
  737. #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
  738. #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
  739. #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
  740. #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
  741. u8 queueing_opt_reserved[3];
  742. /* scheduler section */
  743. u8 up_enable_bits;
  744. u8 sched_reserved;
  745. /* outer up section */
  746. __le32 outer_up_table; /* same structure and defines as ingress tbl */
  747. u8 cmd_reserved[8];
  748. /* last 32 bytes are written by FW */
  749. __le16 qs_handle[8];
  750. #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
  751. __le16 stat_counter_idx;
  752. __le16 sched_id;
  753. u8 resp_reserved[12];
  754. };
  755. I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
  756. /* Add Port Virtualizer (direct 0x0220)
  757. * also used for update PV (direct 0x0221) but only flags are used
  758. * (IS_CTRL_PORT only works on add PV)
  759. */
  760. struct i40e_aqc_add_update_pv {
  761. __le16 command_flags;
  762. #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
  763. #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
  764. #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
  765. #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
  766. __le16 uplink_seid;
  767. __le16 connected_seid;
  768. u8 reserved[10];
  769. };
  770. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
  771. struct i40e_aqc_add_update_pv_completion {
  772. /* reserved for update; for add also encodes error if rc == ENOSPC */
  773. __le16 pv_seid;
  774. #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
  775. #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
  776. #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
  777. #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
  778. u8 reserved[14];
  779. };
  780. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
  781. /* Get PV Params (direct 0x0222)
  782. * uses i40e_aqc_switch_seid for the descriptor
  783. */
  784. struct i40e_aqc_get_pv_params_completion {
  785. __le16 seid;
  786. __le16 default_stag;
  787. __le16 pv_flags; /* same flags as add_pv */
  788. #define I40E_AQC_GET_PV_PV_TYPE 0x1
  789. #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
  790. #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
  791. u8 reserved[8];
  792. __le16 default_port_seid;
  793. };
  794. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
  795. /* Add VEB (direct 0x0230) */
  796. struct i40e_aqc_add_veb {
  797. __le16 uplink_seid;
  798. __le16 downlink_seid;
  799. __le16 veb_flags;
  800. #define I40E_AQC_ADD_VEB_FLOATING 0x1
  801. #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
  802. #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
  803. I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
  804. #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
  805. #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
  806. #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
  807. u8 enable_tcs;
  808. u8 reserved[9];
  809. };
  810. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
  811. struct i40e_aqc_add_veb_completion {
  812. u8 reserved[6];
  813. __le16 switch_seid;
  814. /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
  815. __le16 veb_seid;
  816. #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
  817. #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
  818. #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
  819. #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
  820. __le16 statistic_index;
  821. __le16 vebs_used;
  822. __le16 vebs_free;
  823. };
  824. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
  825. /* Get VEB Parameters (direct 0x0232)
  826. * uses i40e_aqc_switch_seid for the descriptor
  827. */
  828. struct i40e_aqc_get_veb_parameters_completion {
  829. __le16 seid;
  830. __le16 switch_id;
  831. __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
  832. __le16 statistic_index;
  833. __le16 vebs_used;
  834. __le16 vebs_free;
  835. u8 reserved[4];
  836. };
  837. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
  838. /* Delete Element (direct 0x0243)
  839. * uses the generic i40e_aqc_switch_seid
  840. */
  841. /* Add MAC-VLAN (indirect 0x0250) */
  842. /* used for the command for most vlan commands */
  843. struct i40e_aqc_macvlan {
  844. __le16 num_addresses;
  845. __le16 seid[3];
  846. #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
  847. #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
  848. I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
  849. #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
  850. __le32 addr_high;
  851. __le32 addr_low;
  852. };
  853. I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
  854. /* indirect data for command and response */
  855. struct i40e_aqc_add_macvlan_element_data {
  856. u8 mac_addr[6];
  857. __le16 vlan_tag;
  858. __le16 flags;
  859. #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
  860. #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
  861. #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
  862. #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
  863. __le16 queue_number;
  864. #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
  865. #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
  866. I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
  867. /* response section */
  868. u8 match_method;
  869. #define I40E_AQC_MM_PERFECT_MATCH 0x01
  870. #define I40E_AQC_MM_HASH_MATCH 0x02
  871. #define I40E_AQC_MM_ERR_NO_RES 0xFF
  872. u8 reserved1[3];
  873. };
  874. struct i40e_aqc_add_remove_macvlan_completion {
  875. __le16 perfect_mac_used;
  876. __le16 perfect_mac_free;
  877. __le16 unicast_hash_free;
  878. __le16 multicast_hash_free;
  879. __le32 addr_high;
  880. __le32 addr_low;
  881. };
  882. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
  883. /* Remove MAC-VLAN (indirect 0x0251)
  884. * uses i40e_aqc_macvlan for the descriptor
  885. * data points to an array of num_addresses of elements
  886. */
  887. struct i40e_aqc_remove_macvlan_element_data {
  888. u8 mac_addr[6];
  889. __le16 vlan_tag;
  890. u8 flags;
  891. #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
  892. #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
  893. #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
  894. #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
  895. u8 reserved[3];
  896. /* reply section */
  897. u8 error_code;
  898. #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
  899. #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
  900. u8 reply_reserved[3];
  901. };
  902. /* Add VLAN (indirect 0x0252)
  903. * Remove VLAN (indirect 0x0253)
  904. * use the generic i40e_aqc_macvlan for the command
  905. */
  906. struct i40e_aqc_add_remove_vlan_element_data {
  907. __le16 vlan_tag;
  908. u8 vlan_flags;
  909. /* flags for add VLAN */
  910. #define I40E_AQC_ADD_VLAN_LOCAL 0x1
  911. #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
  912. #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
  913. #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
  914. #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
  915. #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
  916. #define I40E_AQC_VLAN_PTYPE_SHIFT 3
  917. #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
  918. #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
  919. #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
  920. #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
  921. #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
  922. /* flags for remove VLAN */
  923. #define I40E_AQC_REMOVE_VLAN_ALL 0x1
  924. u8 reserved;
  925. u8 result;
  926. /* flags for add VLAN */
  927. #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
  928. #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
  929. #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
  930. /* flags for remove VLAN */
  931. #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
  932. #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
  933. u8 reserved1[3];
  934. };
  935. struct i40e_aqc_add_remove_vlan_completion {
  936. u8 reserved[4];
  937. __le16 vlans_used;
  938. __le16 vlans_free;
  939. __le32 addr_high;
  940. __le32 addr_low;
  941. };
  942. /* Set VSI Promiscuous Modes (direct 0x0254) */
  943. struct i40e_aqc_set_vsi_promiscuous_modes {
  944. __le16 promiscuous_flags;
  945. __le16 valid_flags;
  946. /* flags used for both fields above */
  947. #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
  948. #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
  949. #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
  950. #define I40E_AQC_SET_VSI_DEFAULT 0x08
  951. #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
  952. __le16 seid;
  953. #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
  954. __le16 vlan_tag;
  955. #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
  956. #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
  957. u8 reserved[8];
  958. };
  959. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
  960. /* Add S/E-tag command (direct 0x0255)
  961. * Uses generic i40e_aqc_add_remove_tag_completion for completion
  962. */
  963. struct i40e_aqc_add_tag {
  964. __le16 flags;
  965. #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
  966. __le16 seid;
  967. #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
  968. #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
  969. I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
  970. __le16 tag;
  971. __le16 queue_number;
  972. u8 reserved[8];
  973. };
  974. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
  975. struct i40e_aqc_add_remove_tag_completion {
  976. u8 reserved[12];
  977. __le16 tags_used;
  978. __le16 tags_free;
  979. };
  980. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
  981. /* Remove S/E-tag command (direct 0x0256)
  982. * Uses generic i40e_aqc_add_remove_tag_completion for completion
  983. */
  984. struct i40e_aqc_remove_tag {
  985. __le16 seid;
  986. #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
  987. #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
  988. I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
  989. __le16 tag;
  990. u8 reserved[12];
  991. };
  992. I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
  993. /* Add multicast E-Tag (direct 0x0257)
  994. * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
  995. * and no external data
  996. */
  997. struct i40e_aqc_add_remove_mcast_etag {
  998. __le16 pv_seid;
  999. __le16 etag;
  1000. u8 num_unicast_etags;
  1001. u8 reserved[3];
  1002. __le32 addr_high; /* address of array of 2-byte s-tags */
  1003. __le32 addr_low;
  1004. };
  1005. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
  1006. struct i40e_aqc_add_remove_mcast_etag_completion {
  1007. u8 reserved[4];
  1008. __le16 mcast_etags_used;
  1009. __le16 mcast_etags_free;
  1010. __le32 addr_high;
  1011. __le32 addr_low;
  1012. };
  1013. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
  1014. /* Update S/E-Tag (direct 0x0259) */
  1015. struct i40e_aqc_update_tag {
  1016. __le16 seid;
  1017. #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
  1018. #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
  1019. I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
  1020. __le16 old_tag;
  1021. __le16 new_tag;
  1022. u8 reserved[10];
  1023. };
  1024. I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
  1025. struct i40e_aqc_update_tag_completion {
  1026. u8 reserved[12];
  1027. __le16 tags_used;
  1028. __le16 tags_free;
  1029. };
  1030. I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
  1031. /* Add Control Packet filter (direct 0x025A)
  1032. * Remove Control Packet filter (direct 0x025B)
  1033. * uses the i40e_aqc_add_oveb_cloud,
  1034. * and the generic direct completion structure
  1035. */
  1036. struct i40e_aqc_add_remove_control_packet_filter {
  1037. u8 mac[6];
  1038. __le16 etype;
  1039. __le16 flags;
  1040. #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
  1041. #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
  1042. #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
  1043. #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
  1044. #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
  1045. __le16 seid;
  1046. #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
  1047. #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
  1048. I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
  1049. __le16 queue;
  1050. u8 reserved[2];
  1051. };
  1052. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
  1053. struct i40e_aqc_add_remove_control_packet_filter_completion {
  1054. __le16 mac_etype_used;
  1055. __le16 etype_used;
  1056. __le16 mac_etype_free;
  1057. __le16 etype_free;
  1058. u8 reserved[8];
  1059. };
  1060. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
  1061. /* Add Cloud filters (indirect 0x025C)
  1062. * Remove Cloud filters (indirect 0x025D)
  1063. * uses the i40e_aqc_add_remove_cloud_filters,
  1064. * and the generic indirect completion structure
  1065. */
  1066. struct i40e_aqc_add_remove_cloud_filters {
  1067. u8 num_filters;
  1068. u8 reserved;
  1069. __le16 seid;
  1070. #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
  1071. #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
  1072. I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
  1073. u8 reserved2[4];
  1074. __le32 addr_high;
  1075. __le32 addr_low;
  1076. };
  1077. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
  1078. struct i40e_aqc_add_remove_cloud_filters_element_data {
  1079. u8 outer_mac[6];
  1080. u8 inner_mac[6];
  1081. __le16 inner_vlan;
  1082. union {
  1083. struct {
  1084. u8 reserved[12];
  1085. u8 data[4];
  1086. } v4;
  1087. struct {
  1088. u8 data[16];
  1089. } v6;
  1090. } ipaddr;
  1091. __le16 flags;
  1092. #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
  1093. #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
  1094. I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
  1095. /* 0x0000 reserved */
  1096. #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
  1097. /* 0x0002 reserved */
  1098. #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
  1099. #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
  1100. /* 0x0005 reserved */
  1101. #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
  1102. /* 0x0007 reserved */
  1103. /* 0x0008 reserved */
  1104. #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
  1105. #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
  1106. #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
  1107. #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
  1108. #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
  1109. #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
  1110. #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
  1111. #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
  1112. #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
  1113. #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
  1114. #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
  1115. #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0
  1116. #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
  1117. #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2
  1118. #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
  1119. __le32 tenant_id;
  1120. u8 reserved[4];
  1121. __le16 queue_number;
  1122. #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
  1123. #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
  1124. I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
  1125. u8 reserved2[14];
  1126. /* response section */
  1127. u8 allocation_result;
  1128. #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
  1129. #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
  1130. u8 response_reserved[7];
  1131. };
  1132. struct i40e_aqc_remove_cloud_filters_completion {
  1133. __le16 perfect_ovlan_used;
  1134. __le16 perfect_ovlan_free;
  1135. __le16 vlan_used;
  1136. __le16 vlan_free;
  1137. __le32 addr_high;
  1138. __le32 addr_low;
  1139. };
  1140. I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
  1141. /* Add Mirror Rule (indirect or direct 0x0260)
  1142. * Delete Mirror Rule (indirect or direct 0x0261)
  1143. * note: some rule types (4,5) do not use an external buffer.
  1144. * take care to set the flags correctly.
  1145. */
  1146. struct i40e_aqc_add_delete_mirror_rule {
  1147. __le16 seid;
  1148. __le16 rule_type;
  1149. #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
  1150. #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
  1151. I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
  1152. #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
  1153. #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
  1154. #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
  1155. #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
  1156. #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
  1157. __le16 num_entries;
  1158. __le16 destination; /* VSI for add, rule id for delete */
  1159. __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
  1160. __le32 addr_low;
  1161. };
  1162. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
  1163. struct i40e_aqc_add_delete_mirror_rule_completion {
  1164. u8 reserved[2];
  1165. __le16 rule_id; /* only used on add */
  1166. __le16 mirror_rules_used;
  1167. __le16 mirror_rules_free;
  1168. __le32 addr_high;
  1169. __le32 addr_low;
  1170. };
  1171. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
  1172. /* DCB 0x03xx*/
  1173. /* PFC Ignore (direct 0x0301)
  1174. * the command and response use the same descriptor structure
  1175. */
  1176. struct i40e_aqc_pfc_ignore {
  1177. u8 tc_bitmap;
  1178. u8 command_flags; /* unused on response */
  1179. #define I40E_AQC_PFC_IGNORE_SET 0x80
  1180. #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
  1181. u8 reserved[14];
  1182. };
  1183. I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
  1184. /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
  1185. * with no parameters
  1186. */
  1187. /* TX scheduler 0x04xx */
  1188. /* Almost all the indirect commands use
  1189. * this generic struct to pass the SEID in param0
  1190. */
  1191. struct i40e_aqc_tx_sched_ind {
  1192. __le16 vsi_seid;
  1193. u8 reserved[6];
  1194. __le32 addr_high;
  1195. __le32 addr_low;
  1196. };
  1197. I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
  1198. /* Several commands respond with a set of queue set handles */
  1199. struct i40e_aqc_qs_handles_resp {
  1200. __le16 qs_handles[8];
  1201. };
  1202. /* Configure VSI BW limits (direct 0x0400) */
  1203. struct i40e_aqc_configure_vsi_bw_limit {
  1204. __le16 vsi_seid;
  1205. u8 reserved[2];
  1206. __le16 credit;
  1207. u8 reserved1[2];
  1208. u8 max_credit; /* 0-3, limit = 2^max */
  1209. u8 reserved2[7];
  1210. };
  1211. I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
  1212. /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
  1213. * responds with i40e_aqc_qs_handles_resp
  1214. */
  1215. struct i40e_aqc_configure_vsi_ets_sla_bw_data {
  1216. u8 tc_valid_bits;
  1217. u8 reserved[15];
  1218. __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
  1219. /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
  1220. __le16 tc_bw_max[2];
  1221. u8 reserved1[28];
  1222. };
  1223. I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
  1224. /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
  1225. * responds with i40e_aqc_qs_handles_resp
  1226. */
  1227. struct i40e_aqc_configure_vsi_tc_bw_data {
  1228. u8 tc_valid_bits;
  1229. u8 reserved[3];
  1230. u8 tc_bw_credits[8];
  1231. u8 reserved1[4];
  1232. __le16 qs_handles[8];
  1233. };
  1234. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
  1235. /* Query vsi bw configuration (indirect 0x0408) */
  1236. struct i40e_aqc_query_vsi_bw_config_resp {
  1237. u8 tc_valid_bits;
  1238. u8 tc_suspended_bits;
  1239. u8 reserved[14];
  1240. __le16 qs_handles[8];
  1241. u8 reserved1[4];
  1242. __le16 port_bw_limit;
  1243. u8 reserved2[2];
  1244. u8 max_bw; /* 0-3, limit = 2^max */
  1245. u8 reserved3[23];
  1246. };
  1247. I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
  1248. /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
  1249. struct i40e_aqc_query_vsi_ets_sla_config_resp {
  1250. u8 tc_valid_bits;
  1251. u8 reserved[3];
  1252. u8 share_credits[8];
  1253. __le16 credits[8];
  1254. /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
  1255. __le16 tc_bw_max[2];
  1256. };
  1257. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
  1258. /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
  1259. struct i40e_aqc_configure_switching_comp_bw_limit {
  1260. __le16 seid;
  1261. u8 reserved[2];
  1262. __le16 credit;
  1263. u8 reserved1[2];
  1264. u8 max_bw; /* 0-3, limit = 2^max */
  1265. u8 reserved2[7];
  1266. };
  1267. I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
  1268. /* Enable Physical Port ETS (indirect 0x0413)
  1269. * Modify Physical Port ETS (indirect 0x0414)
  1270. * Disable Physical Port ETS (indirect 0x0415)
  1271. */
  1272. struct i40e_aqc_configure_switching_comp_ets_data {
  1273. u8 reserved[4];
  1274. u8 tc_valid_bits;
  1275. u8 seepage;
  1276. #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
  1277. u8 tc_strict_priority_flags;
  1278. u8 reserved1[17];
  1279. u8 tc_bw_share_credits[8];
  1280. u8 reserved2[96];
  1281. };
  1282. I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
  1283. /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
  1284. struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
  1285. u8 tc_valid_bits;
  1286. u8 reserved[15];
  1287. __le16 tc_bw_credit[8];
  1288. /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
  1289. __le16 tc_bw_max[2];
  1290. u8 reserved1[28];
  1291. };
  1292. I40E_CHECK_STRUCT_LEN(0x40,
  1293. i40e_aqc_configure_switching_comp_ets_bw_limit_data);
  1294. /* Configure Switching Component Bandwidth Allocation per Tc
  1295. * (indirect 0x0417)
  1296. */
  1297. struct i40e_aqc_configure_switching_comp_bw_config_data {
  1298. u8 tc_valid_bits;
  1299. u8 reserved[2];
  1300. u8 absolute_credits; /* bool */
  1301. u8 tc_bw_share_credits[8];
  1302. u8 reserved1[20];
  1303. };
  1304. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
  1305. /* Query Switching Component Configuration (indirect 0x0418) */
  1306. struct i40e_aqc_query_switching_comp_ets_config_resp {
  1307. u8 tc_valid_bits;
  1308. u8 reserved[35];
  1309. __le16 port_bw_limit;
  1310. u8 reserved1[2];
  1311. u8 tc_bw_max; /* 0-3, limit = 2^max */
  1312. u8 reserved2[23];
  1313. };
  1314. I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
  1315. /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
  1316. struct i40e_aqc_query_port_ets_config_resp {
  1317. u8 reserved[4];
  1318. u8 tc_valid_bits;
  1319. u8 reserved1;
  1320. u8 tc_strict_priority_bits;
  1321. u8 reserved2;
  1322. u8 tc_bw_share_credits[8];
  1323. __le16 tc_bw_limits[8];
  1324. /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
  1325. __le16 tc_bw_max[2];
  1326. u8 reserved3[32];
  1327. };
  1328. I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
  1329. /* Query Switching Component Bandwidth Allocation per Traffic Type
  1330. * (indirect 0x041A)
  1331. */
  1332. struct i40e_aqc_query_switching_comp_bw_config_resp {
  1333. u8 tc_valid_bits;
  1334. u8 reserved[2];
  1335. u8 absolute_credits_enable; /* bool */
  1336. u8 tc_bw_share_credits[8];
  1337. __le16 tc_bw_limits[8];
  1338. /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
  1339. __le16 tc_bw_max[2];
  1340. };
  1341. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
  1342. /* Suspend/resume port TX traffic
  1343. * (direct 0x041B and 0x041C) uses the generic SEID struct
  1344. */
  1345. /* Configure partition BW
  1346. * (indirect 0x041D)
  1347. */
  1348. struct i40e_aqc_configure_partition_bw_data {
  1349. __le16 pf_valid_bits;
  1350. u8 min_bw[16]; /* guaranteed bandwidth */
  1351. u8 max_bw[16]; /* bandwidth limit */
  1352. };
  1353. I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
  1354. /* Get and set the active HMC resource profile and status.
  1355. * (direct 0x0500) and (direct 0x0501)
  1356. */
  1357. struct i40e_aq_get_set_hmc_resource_profile {
  1358. u8 pm_profile;
  1359. u8 pe_vf_enabled;
  1360. u8 reserved[14];
  1361. };
  1362. I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
  1363. enum i40e_aq_hmc_profile {
  1364. /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
  1365. I40E_HMC_PROFILE_DEFAULT = 1,
  1366. I40E_HMC_PROFILE_FAVOR_VF = 2,
  1367. I40E_HMC_PROFILE_EQUAL = 3,
  1368. };
  1369. #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
  1370. #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
  1371. /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
  1372. /* set in param0 for get phy abilities to report qualified modules */
  1373. #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
  1374. #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
  1375. enum i40e_aq_phy_type {
  1376. I40E_PHY_TYPE_SGMII = 0x0,
  1377. I40E_PHY_TYPE_1000BASE_KX = 0x1,
  1378. I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
  1379. I40E_PHY_TYPE_10GBASE_KR = 0x3,
  1380. I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
  1381. I40E_PHY_TYPE_XAUI = 0x5,
  1382. I40E_PHY_TYPE_XFI = 0x6,
  1383. I40E_PHY_TYPE_SFI = 0x7,
  1384. I40E_PHY_TYPE_XLAUI = 0x8,
  1385. I40E_PHY_TYPE_XLPPI = 0x9,
  1386. I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
  1387. I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
  1388. I40E_PHY_TYPE_10GBASE_AOC = 0xC,
  1389. I40E_PHY_TYPE_40GBASE_AOC = 0xD,
  1390. I40E_PHY_TYPE_100BASE_TX = 0x11,
  1391. I40E_PHY_TYPE_1000BASE_T = 0x12,
  1392. I40E_PHY_TYPE_10GBASE_T = 0x13,
  1393. I40E_PHY_TYPE_10GBASE_SR = 0x14,
  1394. I40E_PHY_TYPE_10GBASE_LR = 0x15,
  1395. I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
  1396. I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
  1397. I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
  1398. I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
  1399. I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
  1400. I40E_PHY_TYPE_1000BASE_SX = 0x1B,
  1401. I40E_PHY_TYPE_1000BASE_LX = 0x1C,
  1402. I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
  1403. I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
  1404. I40E_PHY_TYPE_MAX
  1405. };
  1406. #define I40E_LINK_SPEED_100MB_SHIFT 0x1
  1407. #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
  1408. #define I40E_LINK_SPEED_10GB_SHIFT 0x3
  1409. #define I40E_LINK_SPEED_40GB_SHIFT 0x4
  1410. #define I40E_LINK_SPEED_20GB_SHIFT 0x5
  1411. enum i40e_aq_link_speed {
  1412. I40E_LINK_SPEED_UNKNOWN = 0,
  1413. I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
  1414. I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
  1415. I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
  1416. I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
  1417. I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
  1418. };
  1419. struct i40e_aqc_module_desc {
  1420. u8 oui[3];
  1421. u8 reserved1;
  1422. u8 part_number[16];
  1423. u8 revision[4];
  1424. u8 reserved2[8];
  1425. };
  1426. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
  1427. struct i40e_aq_get_phy_abilities_resp {
  1428. __le32 phy_type; /* bitmap using the above enum for offsets */
  1429. u8 link_speed; /* bitmap using the above enum bit patterns */
  1430. u8 abilities;
  1431. #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
  1432. #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
  1433. #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
  1434. #define I40E_AQ_PHY_LINK_ENABLED 0x08
  1435. #define I40E_AQ_PHY_AN_ENABLED 0x10
  1436. #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
  1437. __le16 eee_capability;
  1438. #define I40E_AQ_EEE_100BASE_TX 0x0002
  1439. #define I40E_AQ_EEE_1000BASE_T 0x0004
  1440. #define I40E_AQ_EEE_10GBASE_T 0x0008
  1441. #define I40E_AQ_EEE_1000BASE_KX 0x0010
  1442. #define I40E_AQ_EEE_10GBASE_KX4 0x0020
  1443. #define I40E_AQ_EEE_10GBASE_KR 0x0040
  1444. __le32 eeer_val;
  1445. u8 d3_lpan;
  1446. #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
  1447. u8 reserved[3];
  1448. u8 phy_id[4];
  1449. u8 module_type[3];
  1450. u8 qualified_module_count;
  1451. #define I40E_AQ_PHY_MAX_QMS 16
  1452. struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
  1453. };
  1454. I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
  1455. /* Set PHY Config (direct 0x0601) */
  1456. struct i40e_aq_set_phy_config { /* same bits as above in all */
  1457. __le32 phy_type;
  1458. u8 link_speed;
  1459. u8 abilities;
  1460. /* bits 0-2 use the values from get_phy_abilities_resp */
  1461. #define I40E_AQ_PHY_ENABLE_LINK 0x08
  1462. #define I40E_AQ_PHY_ENABLE_AN 0x10
  1463. #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
  1464. __le16 eee_capability;
  1465. __le32 eeer;
  1466. u8 low_power_ctrl;
  1467. u8 reserved[3];
  1468. };
  1469. I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
  1470. /* Set MAC Config command data structure (direct 0x0603) */
  1471. struct i40e_aq_set_mac_config {
  1472. __le16 max_frame_size;
  1473. u8 params;
  1474. #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
  1475. #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
  1476. #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
  1477. #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
  1478. #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
  1479. #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
  1480. #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
  1481. #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
  1482. #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
  1483. #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
  1484. #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
  1485. #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
  1486. #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
  1487. #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
  1488. u8 tx_timer_priority; /* bitmap */
  1489. __le16 tx_timer_value;
  1490. __le16 fc_refresh_threshold;
  1491. u8 reserved[8];
  1492. };
  1493. I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
  1494. /* Restart Auto-Negotiation (direct 0x605) */
  1495. struct i40e_aqc_set_link_restart_an {
  1496. u8 command;
  1497. #define I40E_AQ_PHY_RESTART_AN 0x02
  1498. #define I40E_AQ_PHY_LINK_ENABLE 0x04
  1499. u8 reserved[15];
  1500. };
  1501. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
  1502. /* Get Link Status cmd & response data structure (direct 0x0607) */
  1503. struct i40e_aqc_get_link_status {
  1504. __le16 command_flags; /* only field set on command */
  1505. #define I40E_AQ_LSE_MASK 0x3
  1506. #define I40E_AQ_LSE_NOP 0x0
  1507. #define I40E_AQ_LSE_DISABLE 0x2
  1508. #define I40E_AQ_LSE_ENABLE 0x3
  1509. /* only response uses this flag */
  1510. #define I40E_AQ_LSE_IS_ENABLED 0x1
  1511. u8 phy_type; /* i40e_aq_phy_type */
  1512. u8 link_speed; /* i40e_aq_link_speed */
  1513. u8 link_info;
  1514. #define I40E_AQ_LINK_UP 0x01 /* obsolete */
  1515. #define I40E_AQ_LINK_UP_FUNCTION 0x01
  1516. #define I40E_AQ_LINK_FAULT 0x02
  1517. #define I40E_AQ_LINK_FAULT_TX 0x04
  1518. #define I40E_AQ_LINK_FAULT_RX 0x08
  1519. #define I40E_AQ_LINK_FAULT_REMOTE 0x10
  1520. #define I40E_AQ_LINK_UP_PORT 0x20
  1521. #define I40E_AQ_MEDIA_AVAILABLE 0x40
  1522. #define I40E_AQ_SIGNAL_DETECT 0x80
  1523. u8 an_info;
  1524. #define I40E_AQ_AN_COMPLETED 0x01
  1525. #define I40E_AQ_LP_AN_ABILITY 0x02
  1526. #define I40E_AQ_PD_FAULT 0x04
  1527. #define I40E_AQ_FEC_EN 0x08
  1528. #define I40E_AQ_PHY_LOW_POWER 0x10
  1529. #define I40E_AQ_LINK_PAUSE_TX 0x20
  1530. #define I40E_AQ_LINK_PAUSE_RX 0x40
  1531. #define I40E_AQ_QUALIFIED_MODULE 0x80
  1532. u8 ext_info;
  1533. #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
  1534. #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
  1535. #define I40E_AQ_LINK_TX_SHIFT 0x02
  1536. #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
  1537. #define I40E_AQ_LINK_TX_ACTIVE 0x00
  1538. #define I40E_AQ_LINK_TX_DRAINED 0x01
  1539. #define I40E_AQ_LINK_TX_FLUSHED 0x03
  1540. #define I40E_AQ_LINK_FORCED_40G 0x10
  1541. u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
  1542. __le16 max_frame_size;
  1543. u8 config;
  1544. #define I40E_AQ_CONFIG_CRC_ENA 0x04
  1545. #define I40E_AQ_CONFIG_PACING_MASK 0x78
  1546. u8 reserved[5];
  1547. };
  1548. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
  1549. /* Set event mask command (direct 0x613) */
  1550. struct i40e_aqc_set_phy_int_mask {
  1551. u8 reserved[8];
  1552. __le16 event_mask;
  1553. #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
  1554. #define I40E_AQ_EVENT_MEDIA_NA 0x0004
  1555. #define I40E_AQ_EVENT_LINK_FAULT 0x0008
  1556. #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
  1557. #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
  1558. #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
  1559. #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
  1560. #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
  1561. #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
  1562. u8 reserved1[6];
  1563. };
  1564. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
  1565. /* Get Local AN advt register (direct 0x0614)
  1566. * Set Local AN advt register (direct 0x0615)
  1567. * Get Link Partner AN advt register (direct 0x0616)
  1568. */
  1569. struct i40e_aqc_an_advt_reg {
  1570. __le32 local_an_reg0;
  1571. __le16 local_an_reg1;
  1572. u8 reserved[10];
  1573. };
  1574. I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
  1575. /* Set Loopback mode (0x0618) */
  1576. struct i40e_aqc_set_lb_mode {
  1577. __le16 lb_mode;
  1578. #define I40E_AQ_LB_PHY_LOCAL 0x01
  1579. #define I40E_AQ_LB_PHY_REMOTE 0x02
  1580. #define I40E_AQ_LB_MAC_LOCAL 0x04
  1581. u8 reserved[14];
  1582. };
  1583. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
  1584. /* Set PHY Debug command (0x0622) */
  1585. struct i40e_aqc_set_phy_debug {
  1586. u8 command_flags;
  1587. #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
  1588. #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
  1589. #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
  1590. I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
  1591. #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
  1592. #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
  1593. #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
  1594. #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
  1595. u8 reserved[15];
  1596. };
  1597. I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
  1598. enum i40e_aq_phy_reg_type {
  1599. I40E_AQC_PHY_REG_INTERNAL = 0x1,
  1600. I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
  1601. I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
  1602. };
  1603. /* NVM Read command (indirect 0x0701)
  1604. * NVM Erase commands (direct 0x0702)
  1605. * NVM Update commands (indirect 0x0703)
  1606. */
  1607. struct i40e_aqc_nvm_update {
  1608. u8 command_flags;
  1609. #define I40E_AQ_NVM_LAST_CMD 0x01
  1610. #define I40E_AQ_NVM_FLASH_ONLY 0x80
  1611. u8 module_pointer;
  1612. __le16 length;
  1613. __le32 offset;
  1614. __le32 addr_high;
  1615. __le32 addr_low;
  1616. };
  1617. I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
  1618. /* NVM Config Read (indirect 0x0704) */
  1619. struct i40e_aqc_nvm_config_read {
  1620. __le16 cmd_flags;
  1621. #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
  1622. #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
  1623. #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
  1624. __le16 element_count;
  1625. __le16 element_id; /* Feature/field ID */
  1626. __le16 element_id_msw; /* MSWord of field ID */
  1627. __le32 address_high;
  1628. __le32 address_low;
  1629. };
  1630. I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
  1631. /* NVM Config Write (indirect 0x0705) */
  1632. struct i40e_aqc_nvm_config_write {
  1633. __le16 cmd_flags;
  1634. __le16 element_count;
  1635. u8 reserved[4];
  1636. __le32 address_high;
  1637. __le32 address_low;
  1638. };
  1639. I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
  1640. /* Used for 0x0704 as well as for 0x0705 commands */
  1641. #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
  1642. #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
  1643. (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
  1644. #define I40E_AQ_ANVM_FEATURE 0
  1645. #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
  1646. struct i40e_aqc_nvm_config_data_feature {
  1647. __le16 feature_id;
  1648. #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
  1649. #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
  1650. #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
  1651. __le16 feature_options;
  1652. __le16 feature_selection;
  1653. };
  1654. I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
  1655. struct i40e_aqc_nvm_config_data_immediate_field {
  1656. __le32 field_id;
  1657. __le32 field_value;
  1658. __le16 field_options;
  1659. __le16 reserved;
  1660. };
  1661. I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
  1662. /* OEM Post Update (indirect 0x0720)
  1663. * no command data struct used
  1664. */
  1665. struct i40e_aqc_nvm_oem_post_update {
  1666. #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
  1667. u8 sel_data;
  1668. u8 reserved[7];
  1669. };
  1670. I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
  1671. struct i40e_aqc_nvm_oem_post_update_buffer {
  1672. u8 str_len;
  1673. u8 dev_addr;
  1674. __le16 eeprom_addr;
  1675. u8 data[36];
  1676. };
  1677. I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
  1678. /* Send to PF command (indirect 0x0801) id is only used by PF
  1679. * Send to VF command (indirect 0x0802) id is only used by PF
  1680. * Send to Peer PF command (indirect 0x0803)
  1681. */
  1682. struct i40e_aqc_pf_vf_message {
  1683. __le32 id;
  1684. u8 reserved[4];
  1685. __le32 addr_high;
  1686. __le32 addr_low;
  1687. };
  1688. I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
  1689. /* Alternate structure */
  1690. /* Direct write (direct 0x0900)
  1691. * Direct read (direct 0x0902)
  1692. */
  1693. struct i40e_aqc_alternate_write {
  1694. __le32 address0;
  1695. __le32 data0;
  1696. __le32 address1;
  1697. __le32 data1;
  1698. };
  1699. I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
  1700. /* Indirect write (indirect 0x0901)
  1701. * Indirect read (indirect 0x0903)
  1702. */
  1703. struct i40e_aqc_alternate_ind_write {
  1704. __le32 address;
  1705. __le32 length;
  1706. __le32 addr_high;
  1707. __le32 addr_low;
  1708. };
  1709. I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
  1710. /* Done alternate write (direct 0x0904)
  1711. * uses i40e_aq_desc
  1712. */
  1713. struct i40e_aqc_alternate_write_done {
  1714. __le16 cmd_flags;
  1715. #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
  1716. #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
  1717. #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
  1718. #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
  1719. u8 reserved[14];
  1720. };
  1721. I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
  1722. /* Set OEM mode (direct 0x0905) */
  1723. struct i40e_aqc_alternate_set_mode {
  1724. __le32 mode;
  1725. #define I40E_AQ_ALTERNATE_MODE_NONE 0
  1726. #define I40E_AQ_ALTERNATE_MODE_OEM 1
  1727. u8 reserved[12];
  1728. };
  1729. I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
  1730. /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
  1731. /* async events 0x10xx */
  1732. /* Lan Queue Overflow Event (direct, 0x1001) */
  1733. struct i40e_aqc_lan_overflow {
  1734. __le32 prtdcb_rupto;
  1735. __le32 otx_ctl;
  1736. u8 reserved[8];
  1737. };
  1738. I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
  1739. /* Get LLDP MIB (indirect 0x0A00) */
  1740. struct i40e_aqc_lldp_get_mib {
  1741. u8 type;
  1742. u8 reserved1;
  1743. #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
  1744. #define I40E_AQ_LLDP_MIB_LOCAL 0x0
  1745. #define I40E_AQ_LLDP_MIB_REMOTE 0x1
  1746. #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
  1747. #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
  1748. #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
  1749. #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
  1750. #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
  1751. #define I40E_AQ_LLDP_TX_SHIFT 0x4
  1752. #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
  1753. /* TX pause flags use I40E_AQ_LINK_TX_* above */
  1754. __le16 local_len;
  1755. __le16 remote_len;
  1756. u8 reserved2[2];
  1757. __le32 addr_high;
  1758. __le32 addr_low;
  1759. };
  1760. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
  1761. /* Configure LLDP MIB Change Event (direct 0x0A01)
  1762. * also used for the event (with type in the command field)
  1763. */
  1764. struct i40e_aqc_lldp_update_mib {
  1765. u8 command;
  1766. #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
  1767. #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
  1768. u8 reserved[7];
  1769. __le32 addr_high;
  1770. __le32 addr_low;
  1771. };
  1772. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
  1773. /* Add LLDP TLV (indirect 0x0A02)
  1774. * Delete LLDP TLV (indirect 0x0A04)
  1775. */
  1776. struct i40e_aqc_lldp_add_tlv {
  1777. u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
  1778. u8 reserved1[1];
  1779. __le16 len;
  1780. u8 reserved2[4];
  1781. __le32 addr_high;
  1782. __le32 addr_low;
  1783. };
  1784. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
  1785. /* Update LLDP TLV (indirect 0x0A03) */
  1786. struct i40e_aqc_lldp_update_tlv {
  1787. u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
  1788. u8 reserved;
  1789. __le16 old_len;
  1790. __le16 new_offset;
  1791. __le16 new_len;
  1792. __le32 addr_high;
  1793. __le32 addr_low;
  1794. };
  1795. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
  1796. /* Stop LLDP (direct 0x0A05) */
  1797. struct i40e_aqc_lldp_stop {
  1798. u8 command;
  1799. #define I40E_AQ_LLDP_AGENT_STOP 0x0
  1800. #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
  1801. u8 reserved[15];
  1802. };
  1803. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
  1804. /* Start LLDP (direct 0x0A06) */
  1805. struct i40e_aqc_lldp_start {
  1806. u8 command;
  1807. #define I40E_AQ_LLDP_AGENT_START 0x1
  1808. u8 reserved[15];
  1809. };
  1810. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
  1811. /* Get CEE DCBX Oper Config (0x0A07)
  1812. * uses the generic descriptor struct
  1813. * returns below as indirect response
  1814. */
  1815. #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
  1816. #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
  1817. #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
  1818. #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
  1819. #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
  1820. #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
  1821. #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
  1822. #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
  1823. #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
  1824. #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
  1825. #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
  1826. #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
  1827. #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
  1828. #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
  1829. #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
  1830. #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
  1831. #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
  1832. #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
  1833. /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
  1834. * word boundary layout issues, which the Linux compilers silently deal
  1835. * with by adding padding, making the actual struct larger than designed.
  1836. * However, the FW compiler for the NIC is less lenient and complains
  1837. * about the struct. Hence, the struct defined here has an extra byte in
  1838. * fields reserved3 and reserved4 to directly acknowledge that padding,
  1839. * and the new length is used in the length check macro.
  1840. */
  1841. struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
  1842. u8 reserved1;
  1843. u8 oper_num_tc;
  1844. u8 oper_prio_tc[4];
  1845. u8 reserved2;
  1846. u8 oper_tc_bw[8];
  1847. u8 oper_pfc_en;
  1848. u8 reserved3[2];
  1849. __le16 oper_app_prio;
  1850. u8 reserved4[2];
  1851. __le16 tlv_status;
  1852. };
  1853. I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
  1854. struct i40e_aqc_get_cee_dcb_cfg_resp {
  1855. u8 oper_num_tc;
  1856. u8 oper_prio_tc[4];
  1857. u8 oper_tc_bw[8];
  1858. u8 oper_pfc_en;
  1859. __le16 oper_app_prio;
  1860. #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
  1861. #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
  1862. #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
  1863. #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
  1864. #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
  1865. #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
  1866. #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
  1867. __le32 tlv_status;
  1868. #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
  1869. #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
  1870. #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
  1871. #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
  1872. #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
  1873. #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
  1874. u8 reserved[12];
  1875. };
  1876. I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
  1877. /* Set Local LLDP MIB (indirect 0x0A08)
  1878. * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
  1879. */
  1880. struct i40e_aqc_lldp_set_local_mib {
  1881. #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
  1882. #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
  1883. #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
  1884. SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
  1885. #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
  1886. #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
  1887. #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
  1888. SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
  1889. #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
  1890. u8 type;
  1891. u8 reserved0;
  1892. __le16 length;
  1893. u8 reserved1[4];
  1894. __le32 address_high;
  1895. __le32 address_low;
  1896. };
  1897. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
  1898. /* Stop/Start LLDP Agent (direct 0x0A09)
  1899. * Used for stopping/starting specific LLDP agent. e.g. DCBx
  1900. */
  1901. struct i40e_aqc_lldp_stop_start_specific_agent {
  1902. #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
  1903. #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
  1904. (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
  1905. u8 command;
  1906. u8 reserved[15];
  1907. };
  1908. I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
  1909. /* Add Udp Tunnel command and completion (direct 0x0B00) */
  1910. struct i40e_aqc_add_udp_tunnel {
  1911. __le16 udp_port;
  1912. u8 reserved0[3];
  1913. u8 protocol_type;
  1914. #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
  1915. #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
  1916. #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
  1917. u8 reserved1[10];
  1918. };
  1919. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
  1920. struct i40e_aqc_add_udp_tunnel_completion {
  1921. __le16 udp_port;
  1922. u8 filter_entry_index;
  1923. u8 multiple_pfs;
  1924. #define I40E_AQC_SINGLE_PF 0x0
  1925. #define I40E_AQC_MULTIPLE_PFS 0x1
  1926. u8 total_filters;
  1927. u8 reserved[11];
  1928. };
  1929. I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
  1930. /* remove UDP Tunnel command (0x0B01) */
  1931. struct i40e_aqc_remove_udp_tunnel {
  1932. u8 reserved[2];
  1933. u8 index; /* 0 to 15 */
  1934. u8 reserved2[13];
  1935. };
  1936. I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
  1937. struct i40e_aqc_del_udp_tunnel_completion {
  1938. __le16 udp_port;
  1939. u8 index; /* 0 to 15 */
  1940. u8 multiple_pfs;
  1941. u8 total_filters_used;
  1942. u8 reserved1[11];
  1943. };
  1944. I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
  1945. struct i40e_aqc_get_set_rss_key {
  1946. #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
  1947. #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
  1948. #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
  1949. I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
  1950. __le16 vsi_id;
  1951. u8 reserved[6];
  1952. __le32 addr_high;
  1953. __le32 addr_low;
  1954. };
  1955. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
  1956. struct i40e_aqc_get_set_rss_key_data {
  1957. u8 standard_rss_key[0x28];
  1958. u8 extended_hash_key[0xc];
  1959. };
  1960. I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
  1961. struct i40e_aqc_get_set_rss_lut {
  1962. #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
  1963. #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
  1964. #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
  1965. I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
  1966. __le16 vsi_id;
  1967. #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
  1968. #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
  1969. I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
  1970. #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
  1971. #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
  1972. __le16 flags;
  1973. u8 reserved[4];
  1974. __le32 addr_high;
  1975. __le32 addr_low;
  1976. };
  1977. I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
  1978. /* tunnel key structure 0x0B10 */
  1979. struct i40e_aqc_tunnel_key_structure {
  1980. u8 key1_off;
  1981. u8 key2_off;
  1982. u8 key1_len; /* 0 to 15 */
  1983. u8 key2_len; /* 0 to 15 */
  1984. u8 flags;
  1985. #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
  1986. /* response flags */
  1987. #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
  1988. #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
  1989. #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
  1990. u8 network_key_index;
  1991. #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
  1992. #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
  1993. #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
  1994. #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
  1995. u8 reserved[10];
  1996. };
  1997. I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
  1998. /* OEM mode commands (direct 0xFE0x) */
  1999. struct i40e_aqc_oem_param_change {
  2000. __le32 param_type;
  2001. #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
  2002. #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
  2003. #define I40E_AQ_OEM_PARAM_MAC 2
  2004. __le32 param_value1;
  2005. __le16 param_value2;
  2006. u8 reserved[6];
  2007. };
  2008. I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
  2009. struct i40e_aqc_oem_state_change {
  2010. __le32 state;
  2011. #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
  2012. #define I40E_AQ_OEM_STATE_LINK_UP 0x1
  2013. u8 reserved[12];
  2014. };
  2015. I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
  2016. /* Initialize OCSD (0xFE02, direct) */
  2017. struct i40e_aqc_opc_oem_ocsd_initialize {
  2018. u8 type_status;
  2019. u8 reserved1[3];
  2020. __le32 ocsd_memory_block_addr_high;
  2021. __le32 ocsd_memory_block_addr_low;
  2022. __le32 requested_update_interval;
  2023. };
  2024. I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
  2025. /* Initialize OCBB (0xFE03, direct) */
  2026. struct i40e_aqc_opc_oem_ocbb_initialize {
  2027. u8 type_status;
  2028. u8 reserved1[3];
  2029. __le32 ocbb_memory_block_addr_high;
  2030. __le32 ocbb_memory_block_addr_low;
  2031. u8 reserved2[4];
  2032. };
  2033. I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
  2034. /* debug commands */
  2035. /* get device id (0xFF00) uses the generic structure */
  2036. /* set test more (0xFF01, internal) */
  2037. struct i40e_acq_set_test_mode {
  2038. u8 mode;
  2039. #define I40E_AQ_TEST_PARTIAL 0
  2040. #define I40E_AQ_TEST_FULL 1
  2041. #define I40E_AQ_TEST_NVM 2
  2042. u8 reserved[3];
  2043. u8 command;
  2044. #define I40E_AQ_TEST_OPEN 0
  2045. #define I40E_AQ_TEST_CLOSE 1
  2046. #define I40E_AQ_TEST_INC 2
  2047. u8 reserved2[3];
  2048. __le32 address_high;
  2049. __le32 address_low;
  2050. };
  2051. I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
  2052. /* Debug Read Register command (0xFF03)
  2053. * Debug Write Register command (0xFF04)
  2054. */
  2055. struct i40e_aqc_debug_reg_read_write {
  2056. __le32 reserved;
  2057. __le32 address;
  2058. __le32 value_high;
  2059. __le32 value_low;
  2060. };
  2061. I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
  2062. /* Scatter/gather Reg Read (indirect 0xFF05)
  2063. * Scatter/gather Reg Write (indirect 0xFF06)
  2064. */
  2065. /* i40e_aq_desc is used for the command */
  2066. struct i40e_aqc_debug_reg_sg_element_data {
  2067. __le32 address;
  2068. __le32 value;
  2069. };
  2070. /* Debug Modify register (direct 0xFF07) */
  2071. struct i40e_aqc_debug_modify_reg {
  2072. __le32 address;
  2073. __le32 value;
  2074. __le32 clear_mask;
  2075. __le32 set_mask;
  2076. };
  2077. I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
  2078. /* dump internal data (0xFF08, indirect) */
  2079. #define I40E_AQ_CLUSTER_ID_AUX 0
  2080. #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
  2081. #define I40E_AQ_CLUSTER_ID_TXSCHED 2
  2082. #define I40E_AQ_CLUSTER_ID_HMC 3
  2083. #define I40E_AQ_CLUSTER_ID_MAC0 4
  2084. #define I40E_AQ_CLUSTER_ID_MAC1 5
  2085. #define I40E_AQ_CLUSTER_ID_MAC2 6
  2086. #define I40E_AQ_CLUSTER_ID_MAC3 7
  2087. #define I40E_AQ_CLUSTER_ID_DCB 8
  2088. #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
  2089. #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
  2090. #define I40E_AQ_CLUSTER_ID_ALTRAM 11
  2091. struct i40e_aqc_debug_dump_internals {
  2092. u8 cluster_id;
  2093. u8 table_id;
  2094. __le16 data_size;
  2095. __le32 idx;
  2096. __le32 address_high;
  2097. __le32 address_low;
  2098. };
  2099. I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
  2100. struct i40e_aqc_debug_modify_internals {
  2101. u8 cluster_id;
  2102. u8 cluster_specific_params[7];
  2103. __le32 address_high;
  2104. __le32 address_low;
  2105. };
  2106. I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
  2107. #endif /* _I40E_ADMINQ_CMD_H_ */