iwl-nvm-parse.c 21 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23. * USA
  24. *
  25. * The full GNU General Public License is included in this distribution
  26. * in the file called COPYING.
  27. *
  28. * Contact Information:
  29. * Intel Linux Wireless <ilw@linux.intel.com>
  30. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31. *
  32. * BSD LICENSE
  33. *
  34. * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
  35. * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
  36. * All rights reserved.
  37. *
  38. * Redistribution and use in source and binary forms, with or without
  39. * modification, are permitted provided that the following conditions
  40. * are met:
  41. *
  42. * * Redistributions of source code must retain the above copyright
  43. * notice, this list of conditions and the following disclaimer.
  44. * * Redistributions in binary form must reproduce the above copyright
  45. * notice, this list of conditions and the following disclaimer in
  46. * the documentation and/or other materials provided with the
  47. * distribution.
  48. * * Neither the name Intel Corporation nor the names of its
  49. * contributors may be used to endorse or promote products derived
  50. * from this software without specific prior written permission.
  51. *
  52. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63. *****************************************************************************/
  64. #include <linux/types.h>
  65. #include <linux/slab.h>
  66. #include <linux/export.h>
  67. #include <linux/etherdevice.h>
  68. #include <linux/pci.h>
  69. #include "iwl-drv.h"
  70. #include "iwl-modparams.h"
  71. #include "iwl-nvm-parse.h"
  72. /* NVM offsets (in words) definitions */
  73. enum wkp_nvm_offsets {
  74. /* NVM HW-Section offset (in words) definitions */
  75. HW_ADDR = 0x15,
  76. /* NVM SW-Section offset (in words) definitions */
  77. NVM_SW_SECTION = 0x1C0,
  78. NVM_VERSION = 0,
  79. RADIO_CFG = 1,
  80. SKU = 2,
  81. N_HW_ADDRS = 3,
  82. NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  83. /* NVM calibration section offset (in words) definitions */
  84. NVM_CALIB_SECTION = 0x2B8,
  85. XTAL_CALIB = 0x316 - NVM_CALIB_SECTION
  86. };
  87. enum family_8000_nvm_offsets {
  88. /* NVM HW-Section offset (in words) definitions */
  89. HW_ADDR0_WFPM_FAMILY_8000 = 0x12,
  90. HW_ADDR1_WFPM_FAMILY_8000 = 0x16,
  91. HW_ADDR0_PCIE_FAMILY_8000 = 0x8A,
  92. HW_ADDR1_PCIE_FAMILY_8000 = 0x8E,
  93. MAC_ADDRESS_OVERRIDE_FAMILY_8000 = 1,
  94. /* NVM SW-Section offset (in words) definitions */
  95. NVM_SW_SECTION_FAMILY_8000 = 0x1C0,
  96. NVM_VERSION_FAMILY_8000 = 0,
  97. RADIO_CFG_FAMILY_8000 = 2,
  98. SKU_FAMILY_8000 = 4,
  99. N_HW_ADDRS_FAMILY_8000 = 5,
  100. /* NVM REGULATORY -Section offset (in words) definitions */
  101. NVM_CHANNELS_FAMILY_8000 = 0,
  102. /* NVM calibration section offset (in words) definitions */
  103. NVM_CALIB_SECTION_FAMILY_8000 = 0x2B8,
  104. XTAL_CALIB_FAMILY_8000 = 0x316 - NVM_CALIB_SECTION_FAMILY_8000
  105. };
  106. /* SKU Capabilities (actual values from NVM definition) */
  107. enum nvm_sku_bits {
  108. NVM_SKU_CAP_BAND_24GHZ = BIT(0),
  109. NVM_SKU_CAP_BAND_52GHZ = BIT(1),
  110. NVM_SKU_CAP_11N_ENABLE = BIT(2),
  111. NVM_SKU_CAP_11AC_ENABLE = BIT(3),
  112. };
  113. /*
  114. * These are the channel numbers in the order that they are stored in the NVM
  115. */
  116. static const u8 iwl_nvm_channels[] = {
  117. /* 2.4 GHz */
  118. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  119. /* 5 GHz */
  120. 36, 40, 44 , 48, 52, 56, 60, 64,
  121. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  122. 149, 153, 157, 161, 165
  123. };
  124. static const u8 iwl_nvm_channels_family_8000[] = {
  125. /* 2.4 GHz */
  126. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  127. /* 5 GHz */
  128. 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  129. 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  130. 149, 153, 157, 161, 165, 169, 173, 177, 181
  131. };
  132. #define IWL_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
  133. #define IWL_NUM_CHANNELS_FAMILY_8000 ARRAY_SIZE(iwl_nvm_channels_family_8000)
  134. #define NUM_2GHZ_CHANNELS 14
  135. #define NUM_2GHZ_CHANNELS_FAMILY_8000 14
  136. #define FIRST_2GHZ_HT_MINUS 5
  137. #define LAST_2GHZ_HT_PLUS 9
  138. #define LAST_5GHZ_HT 161
  139. /* rate data (static) */
  140. static struct ieee80211_rate iwl_cfg80211_rates[] = {
  141. { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
  142. { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
  143. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  144. { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
  145. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  146. { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
  147. .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
  148. { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
  149. { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
  150. { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
  151. { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
  152. { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
  153. { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
  154. { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
  155. { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
  156. };
  157. #define RATES_24_OFFS 0
  158. #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
  159. #define RATES_52_OFFS 4
  160. #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
  161. /**
  162. * enum iwl_nvm_channel_flags - channel flags in NVM
  163. * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
  164. * @NVM_CHANNEL_IBSS: usable as an IBSS channel
  165. * @NVM_CHANNEL_ACTIVE: active scanning allowed
  166. * @NVM_CHANNEL_RADAR: radar detection required
  167. * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
  168. * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
  169. * on same channel on 2.4 or same UNII band on 5.2
  170. * @NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
  171. * @NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
  172. * @NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
  173. * @NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
  174. */
  175. enum iwl_nvm_channel_flags {
  176. NVM_CHANNEL_VALID = BIT(0),
  177. NVM_CHANNEL_IBSS = BIT(1),
  178. NVM_CHANNEL_ACTIVE = BIT(3),
  179. NVM_CHANNEL_RADAR = BIT(4),
  180. NVM_CHANNEL_INDOOR_ONLY = BIT(5),
  181. NVM_CHANNEL_GO_CONCURRENT = BIT(6),
  182. NVM_CHANNEL_WIDE = BIT(8),
  183. NVM_CHANNEL_40MHZ = BIT(9),
  184. NVM_CHANNEL_80MHZ = BIT(10),
  185. NVM_CHANNEL_160MHZ = BIT(11),
  186. };
  187. #define CHECK_AND_PRINT_I(x) \
  188. ((ch_flags & NVM_CHANNEL_##x) ? # x " " : "")
  189. static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
  190. struct iwl_nvm_data *data,
  191. const __le16 * const nvm_ch_flags)
  192. {
  193. int ch_idx;
  194. int n_channels = 0;
  195. struct ieee80211_channel *channel;
  196. u16 ch_flags;
  197. bool is_5ghz;
  198. int num_of_ch, num_2ghz_channels;
  199. const u8 *nvm_chan;
  200. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  201. num_of_ch = IWL_NUM_CHANNELS;
  202. nvm_chan = &iwl_nvm_channels[0];
  203. num_2ghz_channels = NUM_2GHZ_CHANNELS;
  204. } else {
  205. num_of_ch = IWL_NUM_CHANNELS_FAMILY_8000;
  206. nvm_chan = &iwl_nvm_channels_family_8000[0];
  207. num_2ghz_channels = NUM_2GHZ_CHANNELS_FAMILY_8000;
  208. }
  209. for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
  210. ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
  211. if (ch_idx >= num_2ghz_channels &&
  212. !data->sku_cap_band_52GHz_enable)
  213. ch_flags &= ~NVM_CHANNEL_VALID;
  214. if (!(ch_flags & NVM_CHANNEL_VALID)) {
  215. IWL_DEBUG_EEPROM(dev,
  216. "Ch. %d Flags %x [%sGHz] - No traffic\n",
  217. nvm_chan[ch_idx],
  218. ch_flags,
  219. (ch_idx >= num_2ghz_channels) ?
  220. "5.2" : "2.4");
  221. continue;
  222. }
  223. channel = &data->channels[n_channels];
  224. n_channels++;
  225. channel->hw_value = nvm_chan[ch_idx];
  226. channel->band = (ch_idx < num_2ghz_channels) ?
  227. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  228. channel->center_freq =
  229. ieee80211_channel_to_frequency(
  230. channel->hw_value, channel->band);
  231. /* TODO: Need to be dependent to the NVM */
  232. channel->flags = IEEE80211_CHAN_NO_HT40;
  233. if (ch_idx < num_2ghz_channels &&
  234. (ch_flags & NVM_CHANNEL_40MHZ)) {
  235. if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
  236. channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  237. if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
  238. channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  239. } else if (nvm_chan[ch_idx] <= LAST_5GHZ_HT &&
  240. (ch_flags & NVM_CHANNEL_40MHZ)) {
  241. if ((ch_idx - num_2ghz_channels) % 2 == 0)
  242. channel->flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
  243. else
  244. channel->flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
  245. }
  246. if (!(ch_flags & NVM_CHANNEL_80MHZ))
  247. channel->flags |= IEEE80211_CHAN_NO_80MHZ;
  248. if (!(ch_flags & NVM_CHANNEL_160MHZ))
  249. channel->flags |= IEEE80211_CHAN_NO_160MHZ;
  250. if (!(ch_flags & NVM_CHANNEL_IBSS))
  251. channel->flags |= IEEE80211_CHAN_NO_IR;
  252. if (!(ch_flags & NVM_CHANNEL_ACTIVE))
  253. channel->flags |= IEEE80211_CHAN_NO_IR;
  254. if (ch_flags & NVM_CHANNEL_RADAR)
  255. channel->flags |= IEEE80211_CHAN_RADAR;
  256. if (ch_flags & NVM_CHANNEL_INDOOR_ONLY)
  257. channel->flags |= IEEE80211_CHAN_INDOOR_ONLY;
  258. /* Set the GO concurrent flag only in case that NO_IR is set.
  259. * Otherwise it is meaningless
  260. */
  261. if ((ch_flags & NVM_CHANNEL_GO_CONCURRENT) &&
  262. (channel->flags & IEEE80211_CHAN_NO_IR))
  263. channel->flags |= IEEE80211_CHAN_GO_CONCURRENT;
  264. /* Initialize regulatory-based run-time data */
  265. /*
  266. * Default value - highest tx power value. max_power
  267. * is not used in mvm, and is used for backwards compatibility
  268. */
  269. channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
  270. is_5ghz = channel->band == IEEE80211_BAND_5GHZ;
  271. IWL_DEBUG_EEPROM(dev,
  272. "Ch. %d [%sGHz] %s%s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n",
  273. channel->hw_value,
  274. is_5ghz ? "5.2" : "2.4",
  275. CHECK_AND_PRINT_I(VALID),
  276. CHECK_AND_PRINT_I(IBSS),
  277. CHECK_AND_PRINT_I(ACTIVE),
  278. CHECK_AND_PRINT_I(RADAR),
  279. CHECK_AND_PRINT_I(WIDE),
  280. CHECK_AND_PRINT_I(INDOOR_ONLY),
  281. CHECK_AND_PRINT_I(GO_CONCURRENT),
  282. ch_flags,
  283. channel->max_power,
  284. ((ch_flags & NVM_CHANNEL_IBSS) &&
  285. !(ch_flags & NVM_CHANNEL_RADAR))
  286. ? "" : "not ");
  287. }
  288. return n_channels;
  289. }
  290. static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
  291. struct iwl_nvm_data *data,
  292. struct ieee80211_sta_vht_cap *vht_cap,
  293. u8 tx_chains, u8 rx_chains)
  294. {
  295. int num_rx_ants = num_of_ant(rx_chains);
  296. int num_tx_ants = num_of_ant(tx_chains);
  297. unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
  298. IEEE80211_VHT_MAX_AMPDU_1024K);
  299. vht_cap->vht_supported = true;
  300. vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
  301. IEEE80211_VHT_CAP_RXSTBC_1 |
  302. IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
  303. 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
  304. max_ampdu_exponent <<
  305. IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
  306. if (cfg->ht_params->ldpc)
  307. vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
  308. if (num_tx_ants > 1)
  309. vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
  310. else
  311. vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
  312. if (iwlwifi_mod_params.amsdu_size_8K)
  313. vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
  314. vht_cap->vht_mcs.rx_mcs_map =
  315. cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
  316. IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
  317. IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
  318. IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
  319. IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
  320. IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
  321. IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
  322. IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
  323. if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
  324. vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
  325. /* this works because NOT_SUPPORTED == 3 */
  326. vht_cap->vht_mcs.rx_mcs_map |=
  327. cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
  328. }
  329. vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
  330. }
  331. static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
  332. struct iwl_nvm_data *data,
  333. const __le16 *ch_section, bool enable_vht,
  334. u8 tx_chains, u8 rx_chains)
  335. {
  336. int n_channels;
  337. int n_used = 0;
  338. struct ieee80211_supported_band *sband;
  339. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  340. n_channels = iwl_init_channel_map(
  341. dev, cfg, data,
  342. &ch_section[NVM_CHANNELS]);
  343. else
  344. n_channels = iwl_init_channel_map(
  345. dev, cfg, data,
  346. &ch_section[NVM_CHANNELS_FAMILY_8000]);
  347. sband = &data->bands[IEEE80211_BAND_2GHZ];
  348. sband->band = IEEE80211_BAND_2GHZ;
  349. sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
  350. sband->n_bitrates = N_RATES_24;
  351. n_used += iwl_init_sband_channels(data, sband, n_channels,
  352. IEEE80211_BAND_2GHZ);
  353. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_2GHZ,
  354. tx_chains, rx_chains);
  355. sband = &data->bands[IEEE80211_BAND_5GHZ];
  356. sband->band = IEEE80211_BAND_5GHZ;
  357. sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
  358. sband->n_bitrates = N_RATES_52;
  359. n_used += iwl_init_sband_channels(data, sband, n_channels,
  360. IEEE80211_BAND_5GHZ);
  361. iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, IEEE80211_BAND_5GHZ,
  362. tx_chains, rx_chains);
  363. if (enable_vht)
  364. iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
  365. tx_chains, rx_chains);
  366. if (n_channels != n_used)
  367. IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
  368. n_used, n_channels);
  369. }
  370. static int iwl_get_sku(const struct iwl_cfg *cfg,
  371. const __le16 *nvm_sw)
  372. {
  373. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  374. return le16_to_cpup(nvm_sw + SKU);
  375. else
  376. return le32_to_cpup((__le32 *)(nvm_sw + SKU_FAMILY_8000));
  377. }
  378. static int iwl_get_nvm_version(const struct iwl_cfg *cfg,
  379. const __le16 *nvm_sw)
  380. {
  381. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  382. return le16_to_cpup(nvm_sw + NVM_VERSION);
  383. else
  384. return le32_to_cpup((__le32 *)(nvm_sw +
  385. NVM_VERSION_FAMILY_8000));
  386. }
  387. static int iwl_get_radio_cfg(const struct iwl_cfg *cfg,
  388. const __le16 *nvm_sw)
  389. {
  390. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  391. return le16_to_cpup(nvm_sw + RADIO_CFG);
  392. else
  393. return le32_to_cpup((__le32 *)(nvm_sw + RADIO_CFG_FAMILY_8000));
  394. }
  395. #define N_HW_ADDRS_MASK_FAMILY_8000 0xF
  396. static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg,
  397. const __le16 *nvm_sw)
  398. {
  399. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  400. return le16_to_cpup(nvm_sw + N_HW_ADDRS);
  401. else
  402. return le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000))
  403. & N_HW_ADDRS_MASK_FAMILY_8000;
  404. }
  405. static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
  406. struct iwl_nvm_data *data,
  407. u32 radio_cfg)
  408. {
  409. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  410. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
  411. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
  412. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
  413. data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
  414. return;
  415. }
  416. /* set the radio configuration for family 8000 */
  417. data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK_FAMILY_8000(radio_cfg);
  418. data->radio_cfg_step = NVM_RF_CFG_STEP_MSK_FAMILY_8000(radio_cfg);
  419. data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK_FAMILY_8000(radio_cfg);
  420. data->radio_cfg_pnum = NVM_RF_CFG_FLAVOR_MSK_FAMILY_8000(radio_cfg);
  421. data->valid_tx_ant = NVM_RF_CFG_TX_ANT_MSK_FAMILY_8000(radio_cfg);
  422. data->valid_rx_ant = NVM_RF_CFG_RX_ANT_MSK_FAMILY_8000(radio_cfg);
  423. }
  424. static void iwl_set_hw_address(const struct iwl_cfg *cfg,
  425. struct iwl_nvm_data *data,
  426. const __le16 *nvm_sec)
  427. {
  428. const u8 *hw_addr = (const u8 *)(nvm_sec + HW_ADDR);
  429. /* The byte order is little endian 16 bit, meaning 214365 */
  430. data->hw_addr[0] = hw_addr[1];
  431. data->hw_addr[1] = hw_addr[0];
  432. data->hw_addr[2] = hw_addr[3];
  433. data->hw_addr[3] = hw_addr[2];
  434. data->hw_addr[4] = hw_addr[5];
  435. data->hw_addr[5] = hw_addr[4];
  436. }
  437. static void iwl_set_hw_address_family_8000(struct device *dev,
  438. const struct iwl_cfg *cfg,
  439. struct iwl_nvm_data *data,
  440. const __le16 *mac_override,
  441. const __le16 *nvm_hw)
  442. {
  443. const u8 *hw_addr;
  444. if (mac_override) {
  445. hw_addr = (const u8 *)(mac_override +
  446. MAC_ADDRESS_OVERRIDE_FAMILY_8000);
  447. /* The byte order is little endian 16 bit, meaning 214365 */
  448. data->hw_addr[0] = hw_addr[1];
  449. data->hw_addr[1] = hw_addr[0];
  450. data->hw_addr[2] = hw_addr[3];
  451. data->hw_addr[3] = hw_addr[2];
  452. data->hw_addr[4] = hw_addr[5];
  453. data->hw_addr[5] = hw_addr[4];
  454. if (is_valid_ether_addr(data->hw_addr))
  455. return;
  456. IWL_ERR_DEV(dev,
  457. "mac address from nvm override section is not valid\n");
  458. }
  459. if (nvm_hw) {
  460. /* read the MAC address from OTP */
  461. if (!dev_is_pci(dev) || (data->nvm_version < 0xE08)) {
  462. /* read the mac address from the WFPM location */
  463. hw_addr = (const u8 *)(nvm_hw +
  464. HW_ADDR0_WFPM_FAMILY_8000);
  465. data->hw_addr[0] = hw_addr[3];
  466. data->hw_addr[1] = hw_addr[2];
  467. data->hw_addr[2] = hw_addr[1];
  468. data->hw_addr[3] = hw_addr[0];
  469. hw_addr = (const u8 *)(nvm_hw +
  470. HW_ADDR1_WFPM_FAMILY_8000);
  471. data->hw_addr[4] = hw_addr[1];
  472. data->hw_addr[5] = hw_addr[0];
  473. } else if ((data->nvm_version >= 0xE08) &&
  474. (data->nvm_version < 0xE0B)) {
  475. /* read "reverse order" from the PCIe location */
  476. hw_addr = (const u8 *)(nvm_hw +
  477. HW_ADDR0_PCIE_FAMILY_8000);
  478. data->hw_addr[5] = hw_addr[2];
  479. data->hw_addr[4] = hw_addr[1];
  480. data->hw_addr[3] = hw_addr[0];
  481. hw_addr = (const u8 *)(nvm_hw +
  482. HW_ADDR1_PCIE_FAMILY_8000);
  483. data->hw_addr[2] = hw_addr[3];
  484. data->hw_addr[1] = hw_addr[2];
  485. data->hw_addr[0] = hw_addr[1];
  486. } else {
  487. /* read from the PCIe location */
  488. hw_addr = (const u8 *)(nvm_hw +
  489. HW_ADDR0_PCIE_FAMILY_8000);
  490. data->hw_addr[5] = hw_addr[0];
  491. data->hw_addr[4] = hw_addr[1];
  492. data->hw_addr[3] = hw_addr[2];
  493. hw_addr = (const u8 *)(nvm_hw +
  494. HW_ADDR1_PCIE_FAMILY_8000);
  495. data->hw_addr[2] = hw_addr[1];
  496. data->hw_addr[1] = hw_addr[2];
  497. data->hw_addr[0] = hw_addr[3];
  498. }
  499. if (!is_valid_ether_addr(data->hw_addr))
  500. IWL_ERR_DEV(dev,
  501. "mac address from hw section is not valid\n");
  502. return;
  503. }
  504. IWL_ERR_DEV(dev, "mac address is not found\n");
  505. }
  506. struct iwl_nvm_data *
  507. iwl_parse_nvm_data(struct device *dev, const struct iwl_cfg *cfg,
  508. const __le16 *nvm_hw, const __le16 *nvm_sw,
  509. const __le16 *nvm_calib, const __le16 *regulatory,
  510. const __le16 *mac_override, u8 tx_chains, u8 rx_chains)
  511. {
  512. struct iwl_nvm_data *data;
  513. u32 sku;
  514. u32 radio_cfg;
  515. if (cfg->device_family != IWL_DEVICE_FAMILY_8000)
  516. data = kzalloc(sizeof(*data) +
  517. sizeof(struct ieee80211_channel) *
  518. IWL_NUM_CHANNELS,
  519. GFP_KERNEL);
  520. else
  521. data = kzalloc(sizeof(*data) +
  522. sizeof(struct ieee80211_channel) *
  523. IWL_NUM_CHANNELS_FAMILY_8000,
  524. GFP_KERNEL);
  525. if (!data)
  526. return NULL;
  527. data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
  528. radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw);
  529. iwl_set_radio_cfg(cfg, data, radio_cfg);
  530. if (data->valid_tx_ant)
  531. tx_chains &= data->valid_tx_ant;
  532. if (data->valid_rx_ant)
  533. rx_chains &= data->valid_rx_ant;
  534. sku = iwl_get_sku(cfg, nvm_sw);
  535. data->sku_cap_band_24GHz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
  536. data->sku_cap_band_52GHz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
  537. data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
  538. data->sku_cap_11ac_enable = sku & NVM_SKU_CAP_11AC_ENABLE;
  539. if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
  540. data->sku_cap_11n_enable = false;
  541. data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
  542. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  543. /* Checking for required sections */
  544. if (!nvm_calib) {
  545. IWL_ERR_DEV(dev,
  546. "Can't parse empty Calib NVM sections\n");
  547. kfree(data);
  548. return NULL;
  549. }
  550. /* in family 8000 Xtal calibration values moved to OTP */
  551. data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
  552. data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
  553. }
  554. if (cfg->device_family != IWL_DEVICE_FAMILY_8000) {
  555. iwl_set_hw_address(cfg, data, nvm_hw);
  556. iwl_init_sbands(dev, cfg, data, nvm_sw,
  557. sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
  558. rx_chains);
  559. } else {
  560. /* MAC address in family 8000 */
  561. iwl_set_hw_address_family_8000(dev, cfg, data, mac_override,
  562. nvm_hw);
  563. iwl_init_sbands(dev, cfg, data, regulatory,
  564. sku & NVM_SKU_CAP_11AC_ENABLE, tx_chains,
  565. rx_chains);
  566. }
  567. data->calib_version = 255;
  568. return data;
  569. }
  570. IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);