r8152.c 94 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. /* Version Information */
  28. #define DRIVER_VERSION "v1.08.0 (2015/01/13)"
  29. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  30. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  31. #define MODULENAME "r8152"
  32. #define R8152_PHY_ID 32
  33. #define PLA_IDR 0xc000
  34. #define PLA_RCR 0xc010
  35. #define PLA_RMS 0xc016
  36. #define PLA_RXFIFO_CTRL0 0xc0a0
  37. #define PLA_RXFIFO_CTRL1 0xc0a4
  38. #define PLA_RXFIFO_CTRL2 0xc0a8
  39. #define PLA_DMY_REG0 0xc0b0
  40. #define PLA_FMC 0xc0b4
  41. #define PLA_CFG_WOL 0xc0b6
  42. #define PLA_TEREDO_CFG 0xc0bc
  43. #define PLA_MAR 0xcd00
  44. #define PLA_BACKUP 0xd000
  45. #define PAL_BDC_CR 0xd1a0
  46. #define PLA_TEREDO_TIMER 0xd2cc
  47. #define PLA_REALWOW_TIMER 0xd2e8
  48. #define PLA_LEDSEL 0xdd90
  49. #define PLA_LED_FEATURE 0xdd92
  50. #define PLA_PHYAR 0xde00
  51. #define PLA_BOOT_CTRL 0xe004
  52. #define PLA_GPHY_INTR_IMR 0xe022
  53. #define PLA_EEE_CR 0xe040
  54. #define PLA_EEEP_CR 0xe080
  55. #define PLA_MAC_PWR_CTRL 0xe0c0
  56. #define PLA_MAC_PWR_CTRL2 0xe0ca
  57. #define PLA_MAC_PWR_CTRL3 0xe0cc
  58. #define PLA_MAC_PWR_CTRL4 0xe0ce
  59. #define PLA_WDT6_CTRL 0xe428
  60. #define PLA_TCR0 0xe610
  61. #define PLA_TCR1 0xe612
  62. #define PLA_MTPS 0xe615
  63. #define PLA_TXFIFO_CTRL 0xe618
  64. #define PLA_RSTTALLY 0xe800
  65. #define PLA_CR 0xe813
  66. #define PLA_CRWECR 0xe81c
  67. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  68. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  69. #define PLA_CONFIG5 0xe822
  70. #define PLA_PHY_PWR 0xe84c
  71. #define PLA_OOB_CTRL 0xe84f
  72. #define PLA_CPCR 0xe854
  73. #define PLA_MISC_0 0xe858
  74. #define PLA_MISC_1 0xe85a
  75. #define PLA_OCP_GPHY_BASE 0xe86c
  76. #define PLA_TALLYCNT 0xe890
  77. #define PLA_SFF_STS_7 0xe8de
  78. #define PLA_PHYSTATUS 0xe908
  79. #define PLA_BP_BA 0xfc26
  80. #define PLA_BP_0 0xfc28
  81. #define PLA_BP_1 0xfc2a
  82. #define PLA_BP_2 0xfc2c
  83. #define PLA_BP_3 0xfc2e
  84. #define PLA_BP_4 0xfc30
  85. #define PLA_BP_5 0xfc32
  86. #define PLA_BP_6 0xfc34
  87. #define PLA_BP_7 0xfc36
  88. #define PLA_BP_EN 0xfc38
  89. #define USB_USB2PHY 0xb41e
  90. #define USB_SSPHYLINK2 0xb428
  91. #define USB_U2P3_CTRL 0xb460
  92. #define USB_CSR_DUMMY1 0xb464
  93. #define USB_CSR_DUMMY2 0xb466
  94. #define USB_DEV_STAT 0xb808
  95. #define USB_CONNECT_TIMER 0xcbf8
  96. #define USB_BURST_SIZE 0xcfc0
  97. #define USB_USB_CTRL 0xd406
  98. #define USB_PHY_CTRL 0xd408
  99. #define USB_TX_AGG 0xd40a
  100. #define USB_RX_BUF_TH 0xd40c
  101. #define USB_USB_TIMER 0xd428
  102. #define USB_RX_EARLY_TIMEOUT 0xd42c
  103. #define USB_RX_EARLY_SIZE 0xd42e
  104. #define USB_PM_CTRL_STATUS 0xd432
  105. #define USB_TX_DMA 0xd434
  106. #define USB_TOLERANCE 0xd490
  107. #define USB_LPM_CTRL 0xd41a
  108. #define USB_UPS_CTRL 0xd800
  109. #define USB_MISC_0 0xd81a
  110. #define USB_POWER_CUT 0xd80a
  111. #define USB_AFE_CTRL2 0xd824
  112. #define USB_WDT11_CTRL 0xe43c
  113. #define USB_BP_BA 0xfc26
  114. #define USB_BP_0 0xfc28
  115. #define USB_BP_1 0xfc2a
  116. #define USB_BP_2 0xfc2c
  117. #define USB_BP_3 0xfc2e
  118. #define USB_BP_4 0xfc30
  119. #define USB_BP_5 0xfc32
  120. #define USB_BP_6 0xfc34
  121. #define USB_BP_7 0xfc36
  122. #define USB_BP_EN 0xfc38
  123. /* OCP Registers */
  124. #define OCP_ALDPS_CONFIG 0x2010
  125. #define OCP_EEE_CONFIG1 0x2080
  126. #define OCP_EEE_CONFIG2 0x2092
  127. #define OCP_EEE_CONFIG3 0x2094
  128. #define OCP_BASE_MII 0xa400
  129. #define OCP_EEE_AR 0xa41a
  130. #define OCP_EEE_DATA 0xa41c
  131. #define OCP_PHY_STATUS 0xa420
  132. #define OCP_POWER_CFG 0xa430
  133. #define OCP_EEE_CFG 0xa432
  134. #define OCP_SRAM_ADDR 0xa436
  135. #define OCP_SRAM_DATA 0xa438
  136. #define OCP_DOWN_SPEED 0xa442
  137. #define OCP_EEE_ABLE 0xa5c4
  138. #define OCP_EEE_ADV 0xa5d0
  139. #define OCP_EEE_LPABLE 0xa5d2
  140. #define OCP_ADC_CFG 0xbc06
  141. /* SRAM Register */
  142. #define SRAM_LPF_CFG 0x8012
  143. #define SRAM_10M_AMP1 0x8080
  144. #define SRAM_10M_AMP2 0x8082
  145. #define SRAM_IMPEDANCE 0x8084
  146. /* PLA_RCR */
  147. #define RCR_AAP 0x00000001
  148. #define RCR_APM 0x00000002
  149. #define RCR_AM 0x00000004
  150. #define RCR_AB 0x00000008
  151. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  152. /* PLA_RXFIFO_CTRL0 */
  153. #define RXFIFO_THR1_NORMAL 0x00080002
  154. #define RXFIFO_THR1_OOB 0x01800003
  155. /* PLA_RXFIFO_CTRL1 */
  156. #define RXFIFO_THR2_FULL 0x00000060
  157. #define RXFIFO_THR2_HIGH 0x00000038
  158. #define RXFIFO_THR2_OOB 0x0000004a
  159. #define RXFIFO_THR2_NORMAL 0x00a0
  160. /* PLA_RXFIFO_CTRL2 */
  161. #define RXFIFO_THR3_FULL 0x00000078
  162. #define RXFIFO_THR3_HIGH 0x00000048
  163. #define RXFIFO_THR3_OOB 0x0000005a
  164. #define RXFIFO_THR3_NORMAL 0x0110
  165. /* PLA_TXFIFO_CTRL */
  166. #define TXFIFO_THR_NORMAL 0x00400008
  167. #define TXFIFO_THR_NORMAL2 0x01000008
  168. /* PLA_DMY_REG0 */
  169. #define ECM_ALDPS 0x0002
  170. /* PLA_FMC */
  171. #define FMC_FCR_MCU_EN 0x0001
  172. /* PLA_EEEP_CR */
  173. #define EEEP_CR_EEEP_TX 0x0002
  174. /* PLA_WDT6_CTRL */
  175. #define WDT6_SET_MODE 0x0010
  176. /* PLA_TCR0 */
  177. #define TCR0_TX_EMPTY 0x0800
  178. #define TCR0_AUTO_FIFO 0x0080
  179. /* PLA_TCR1 */
  180. #define VERSION_MASK 0x7cf0
  181. /* PLA_MTPS */
  182. #define MTPS_JUMBO (12 * 1024 / 64)
  183. #define MTPS_DEFAULT (6 * 1024 / 64)
  184. /* PLA_RSTTALLY */
  185. #define TALLY_RESET 0x0001
  186. /* PLA_CR */
  187. #define CR_RST 0x10
  188. #define CR_RE 0x08
  189. #define CR_TE 0x04
  190. /* PLA_CRWECR */
  191. #define CRWECR_NORAML 0x00
  192. #define CRWECR_CONFIG 0xc0
  193. /* PLA_OOB_CTRL */
  194. #define NOW_IS_OOB 0x80
  195. #define TXFIFO_EMPTY 0x20
  196. #define RXFIFO_EMPTY 0x10
  197. #define LINK_LIST_READY 0x02
  198. #define DIS_MCU_CLROOB 0x01
  199. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  200. /* PLA_MISC_1 */
  201. #define RXDY_GATED_EN 0x0008
  202. /* PLA_SFF_STS_7 */
  203. #define RE_INIT_LL 0x8000
  204. #define MCU_BORW_EN 0x4000
  205. /* PLA_CPCR */
  206. #define CPCR_RX_VLAN 0x0040
  207. /* PLA_CFG_WOL */
  208. #define MAGIC_EN 0x0001
  209. /* PLA_TEREDO_CFG */
  210. #define TEREDO_SEL 0x8000
  211. #define TEREDO_WAKE_MASK 0x7f00
  212. #define TEREDO_RS_EVENT_MASK 0x00fe
  213. #define OOB_TEREDO_EN 0x0001
  214. /* PAL_BDC_CR */
  215. #define ALDPS_PROXY_MODE 0x0001
  216. /* PLA_CONFIG34 */
  217. #define LINK_ON_WAKE_EN 0x0010
  218. #define LINK_OFF_WAKE_EN 0x0008
  219. /* PLA_CONFIG5 */
  220. #define BWF_EN 0x0040
  221. #define MWF_EN 0x0020
  222. #define UWF_EN 0x0010
  223. #define LAN_WAKE_EN 0x0002
  224. /* PLA_LED_FEATURE */
  225. #define LED_MODE_MASK 0x0700
  226. /* PLA_PHY_PWR */
  227. #define TX_10M_IDLE_EN 0x0080
  228. #define PFM_PWM_SWITCH 0x0040
  229. /* PLA_MAC_PWR_CTRL */
  230. #define D3_CLK_GATED_EN 0x00004000
  231. #define MCU_CLK_RATIO 0x07010f07
  232. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  233. #define ALDPS_SPDWN_RATIO 0x0f87
  234. /* PLA_MAC_PWR_CTRL2 */
  235. #define EEE_SPDWN_RATIO 0x8007
  236. /* PLA_MAC_PWR_CTRL3 */
  237. #define PKT_AVAIL_SPDWN_EN 0x0100
  238. #define SUSPEND_SPDWN_EN 0x0004
  239. #define U1U2_SPDWN_EN 0x0002
  240. #define L1_SPDWN_EN 0x0001
  241. /* PLA_MAC_PWR_CTRL4 */
  242. #define PWRSAVE_SPDWN_EN 0x1000
  243. #define RXDV_SPDWN_EN 0x0800
  244. #define TX10MIDLE_EN 0x0100
  245. #define TP100_SPDWN_EN 0x0020
  246. #define TP500_SPDWN_EN 0x0010
  247. #define TP1000_SPDWN_EN 0x0008
  248. #define EEE_SPDWN_EN 0x0001
  249. /* PLA_GPHY_INTR_IMR */
  250. #define GPHY_STS_MSK 0x0001
  251. #define SPEED_DOWN_MSK 0x0002
  252. #define SPDWN_RXDV_MSK 0x0004
  253. #define SPDWN_LINKCHG_MSK 0x0008
  254. /* PLA_PHYAR */
  255. #define PHYAR_FLAG 0x80000000
  256. /* PLA_EEE_CR */
  257. #define EEE_RX_EN 0x0001
  258. #define EEE_TX_EN 0x0002
  259. /* PLA_BOOT_CTRL */
  260. #define AUTOLOAD_DONE 0x0002
  261. /* USB_USB2PHY */
  262. #define USB2PHY_SUSPEND 0x0001
  263. #define USB2PHY_L1 0x0002
  264. /* USB_SSPHYLINK2 */
  265. #define pwd_dn_scale_mask 0x3ffe
  266. #define pwd_dn_scale(x) ((x) << 1)
  267. /* USB_CSR_DUMMY1 */
  268. #define DYNAMIC_BURST 0x0001
  269. /* USB_CSR_DUMMY2 */
  270. #define EP4_FULL_FC 0x0001
  271. /* USB_DEV_STAT */
  272. #define STAT_SPEED_MASK 0x0006
  273. #define STAT_SPEED_HIGH 0x0000
  274. #define STAT_SPEED_FULL 0x0002
  275. /* USB_TX_AGG */
  276. #define TX_AGG_MAX_THRESHOLD 0x03
  277. /* USB_RX_BUF_TH */
  278. #define RX_THR_SUPPER 0x0c350180
  279. #define RX_THR_HIGH 0x7a120180
  280. #define RX_THR_SLOW 0xffff0180
  281. /* USB_TX_DMA */
  282. #define TEST_MODE_DISABLE 0x00000001
  283. #define TX_SIZE_ADJUST1 0x00000100
  284. /* USB_UPS_CTRL */
  285. #define POWER_CUT 0x0100
  286. /* USB_PM_CTRL_STATUS */
  287. #define RESUME_INDICATE 0x0001
  288. /* USB_USB_CTRL */
  289. #define RX_AGG_DISABLE 0x0010
  290. /* USB_U2P3_CTRL */
  291. #define U2P3_ENABLE 0x0001
  292. /* USB_POWER_CUT */
  293. #define PWR_EN 0x0001
  294. #define PHASE2_EN 0x0008
  295. /* USB_MISC_0 */
  296. #define PCUT_STATUS 0x0001
  297. /* USB_RX_EARLY_TIMEOUT */
  298. #define COALESCE_SUPER 85000U
  299. #define COALESCE_HIGH 250000U
  300. #define COALESCE_SLOW 524280U
  301. /* USB_WDT11_CTRL */
  302. #define TIMER11_EN 0x0001
  303. /* USB_LPM_CTRL */
  304. /* bit 4 ~ 5: fifo empty boundary */
  305. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  306. /* bit 2 ~ 3: LMP timer */
  307. #define LPM_TIMER_MASK 0x0c
  308. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  309. #define LPM_TIMER_500US 0x0c /* 500 us */
  310. #define ROK_EXIT_LPM 0x02
  311. /* USB_AFE_CTRL2 */
  312. #define SEN_VAL_MASK 0xf800
  313. #define SEN_VAL_NORMAL 0xa000
  314. #define SEL_RXIDLE 0x0100
  315. /* OCP_ALDPS_CONFIG */
  316. #define ENPWRSAVE 0x8000
  317. #define ENPDNPS 0x0200
  318. #define LINKENA 0x0100
  319. #define DIS_SDSAVE 0x0010
  320. /* OCP_PHY_STATUS */
  321. #define PHY_STAT_MASK 0x0007
  322. #define PHY_STAT_LAN_ON 3
  323. #define PHY_STAT_PWRDN 5
  324. /* OCP_POWER_CFG */
  325. #define EEE_CLKDIV_EN 0x8000
  326. #define EN_ALDPS 0x0004
  327. #define EN_10M_PLLOFF 0x0001
  328. /* OCP_EEE_CONFIG1 */
  329. #define RG_TXLPI_MSK_HFDUP 0x8000
  330. #define RG_MATCLR_EN 0x4000
  331. #define EEE_10_CAP 0x2000
  332. #define EEE_NWAY_EN 0x1000
  333. #define TX_QUIET_EN 0x0200
  334. #define RX_QUIET_EN 0x0100
  335. #define sd_rise_time_mask 0x0070
  336. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  337. #define RG_RXLPI_MSK_HFDUP 0x0008
  338. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  339. /* OCP_EEE_CONFIG2 */
  340. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  341. #define RG_DACQUIET_EN 0x0400
  342. #define RG_LDVQUIET_EN 0x0200
  343. #define RG_CKRSEL 0x0020
  344. #define RG_EEEPRG_EN 0x0010
  345. /* OCP_EEE_CONFIG3 */
  346. #define fast_snr_mask 0xff80
  347. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  348. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  349. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  350. /* OCP_EEE_AR */
  351. /* bit[15:14] function */
  352. #define FUN_ADDR 0x0000
  353. #define FUN_DATA 0x4000
  354. /* bit[4:0] device addr */
  355. /* OCP_EEE_CFG */
  356. #define CTAP_SHORT_EN 0x0040
  357. #define EEE10_EN 0x0010
  358. /* OCP_DOWN_SPEED */
  359. #define EN_10M_BGOFF 0x0080
  360. /* OCP_ADC_CFG */
  361. #define CKADSEL_L 0x0100
  362. #define ADC_EN 0x0080
  363. #define EN_EMI_L 0x0040
  364. /* SRAM_LPF_CFG */
  365. #define LPF_AUTO_TUNE 0x8000
  366. /* SRAM_10M_AMP1 */
  367. #define GDAC_IB_UPALL 0x0008
  368. /* SRAM_10M_AMP2 */
  369. #define AMP_DN 0x0200
  370. /* SRAM_IMPEDANCE */
  371. #define RX_DRIVING_MASK 0x6000
  372. enum rtl_register_content {
  373. _1000bps = 0x10,
  374. _100bps = 0x08,
  375. _10bps = 0x04,
  376. LINK_STATUS = 0x02,
  377. FULL_DUP = 0x01,
  378. };
  379. #define RTL8152_MAX_TX 4
  380. #define RTL8152_MAX_RX 10
  381. #define INTBUFSIZE 2
  382. #define CRC_SIZE 4
  383. #define TX_ALIGN 4
  384. #define RX_ALIGN 8
  385. #define INTR_LINK 0x0004
  386. #define RTL8152_REQT_READ 0xc0
  387. #define RTL8152_REQT_WRITE 0x40
  388. #define RTL8152_REQ_GET_REGS 0x05
  389. #define RTL8152_REQ_SET_REGS 0x05
  390. #define BYTE_EN_DWORD 0xff
  391. #define BYTE_EN_WORD 0x33
  392. #define BYTE_EN_BYTE 0x11
  393. #define BYTE_EN_SIX_BYTES 0x3f
  394. #define BYTE_EN_START_MASK 0x0f
  395. #define BYTE_EN_END_MASK 0xf0
  396. #define RTL8153_MAX_PACKET 9216 /* 9K */
  397. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  398. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  399. #define RTL8153_RMS RTL8153_MAX_PACKET
  400. #define RTL8152_TX_TIMEOUT (5 * HZ)
  401. #define RTL8152_NAPI_WEIGHT 64
  402. /* rtl8152 flags */
  403. enum rtl8152_flags {
  404. RTL8152_UNPLUG = 0,
  405. RTL8152_SET_RX_MODE,
  406. WORK_ENABLE,
  407. RTL8152_LINK_CHG,
  408. SELECTIVE_SUSPEND,
  409. PHY_RESET,
  410. SCHEDULE_NAPI,
  411. };
  412. /* Define these values to match your device */
  413. #define VENDOR_ID_REALTEK 0x0bda
  414. #define VENDOR_ID_SAMSUNG 0x04e8
  415. #define MCU_TYPE_PLA 0x0100
  416. #define MCU_TYPE_USB 0x0000
  417. struct tally_counter {
  418. __le64 tx_packets;
  419. __le64 rx_packets;
  420. __le64 tx_errors;
  421. __le32 rx_errors;
  422. __le16 rx_missed;
  423. __le16 align_errors;
  424. __le32 tx_one_collision;
  425. __le32 tx_multi_collision;
  426. __le64 rx_unicast;
  427. __le64 rx_broadcast;
  428. __le32 rx_multicast;
  429. __le16 tx_aborted;
  430. __le16 tx_underrun;
  431. };
  432. struct rx_desc {
  433. __le32 opts1;
  434. #define RX_LEN_MASK 0x7fff
  435. __le32 opts2;
  436. #define RD_UDP_CS BIT(23)
  437. #define RD_TCP_CS BIT(22)
  438. #define RD_IPV6_CS BIT(20)
  439. #define RD_IPV4_CS BIT(19)
  440. __le32 opts3;
  441. #define IPF BIT(23) /* IP checksum fail */
  442. #define UDPF BIT(22) /* UDP checksum fail */
  443. #define TCPF BIT(21) /* TCP checksum fail */
  444. #define RX_VLAN_TAG BIT(16)
  445. __le32 opts4;
  446. __le32 opts5;
  447. __le32 opts6;
  448. };
  449. struct tx_desc {
  450. __le32 opts1;
  451. #define TX_FS BIT(31) /* First segment of a packet */
  452. #define TX_LS BIT(30) /* Final segment of a packet */
  453. #define GTSENDV4 BIT(28)
  454. #define GTSENDV6 BIT(27)
  455. #define GTTCPHO_SHIFT 18
  456. #define GTTCPHO_MAX 0x7fU
  457. #define TX_LEN_MAX 0x3ffffU
  458. __le32 opts2;
  459. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  460. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  461. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  462. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  463. #define MSS_SHIFT 17
  464. #define MSS_MAX 0x7ffU
  465. #define TCPHO_SHIFT 17
  466. #define TCPHO_MAX 0x7ffU
  467. #define TX_VLAN_TAG BIT(16)
  468. };
  469. struct r8152;
  470. struct rx_agg {
  471. struct list_head list;
  472. struct urb *urb;
  473. struct r8152 *context;
  474. void *buffer;
  475. void *head;
  476. };
  477. struct tx_agg {
  478. struct list_head list;
  479. struct urb *urb;
  480. struct r8152 *context;
  481. void *buffer;
  482. void *head;
  483. u32 skb_num;
  484. u32 skb_len;
  485. };
  486. struct r8152 {
  487. unsigned long flags;
  488. struct usb_device *udev;
  489. struct napi_struct napi;
  490. struct usb_interface *intf;
  491. struct net_device *netdev;
  492. struct urb *intr_urb;
  493. struct tx_agg tx_info[RTL8152_MAX_TX];
  494. struct rx_agg rx_info[RTL8152_MAX_RX];
  495. struct list_head rx_done, tx_free;
  496. struct sk_buff_head tx_queue, rx_queue;
  497. spinlock_t rx_lock, tx_lock;
  498. struct delayed_work schedule;
  499. struct mii_if_info mii;
  500. struct mutex control; /* use for hw setting */
  501. struct rtl_ops {
  502. void (*init)(struct r8152 *);
  503. int (*enable)(struct r8152 *);
  504. void (*disable)(struct r8152 *);
  505. void (*up)(struct r8152 *);
  506. void (*down)(struct r8152 *);
  507. void (*unload)(struct r8152 *);
  508. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  509. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  510. } rtl_ops;
  511. int intr_interval;
  512. u32 saved_wolopts;
  513. u32 msg_enable;
  514. u32 tx_qlen;
  515. u32 coalesce;
  516. u16 ocp_base;
  517. u8 *intr_buff;
  518. u8 version;
  519. };
  520. enum rtl_version {
  521. RTL_VER_UNKNOWN = 0,
  522. RTL_VER_01,
  523. RTL_VER_02,
  524. RTL_VER_03,
  525. RTL_VER_04,
  526. RTL_VER_05,
  527. RTL_VER_MAX
  528. };
  529. enum tx_csum_stat {
  530. TX_CSUM_SUCCESS = 0,
  531. TX_CSUM_TSO,
  532. TX_CSUM_NONE
  533. };
  534. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  535. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  536. */
  537. static const int multicast_filter_limit = 32;
  538. static unsigned int agg_buf_sz = 16384;
  539. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  540. VLAN_ETH_HLEN - VLAN_HLEN)
  541. static
  542. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  543. {
  544. int ret;
  545. void *tmp;
  546. tmp = kmalloc(size, GFP_KERNEL);
  547. if (!tmp)
  548. return -ENOMEM;
  549. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  550. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  551. value, index, tmp, size, 500);
  552. memcpy(data, tmp, size);
  553. kfree(tmp);
  554. return ret;
  555. }
  556. static
  557. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  558. {
  559. int ret;
  560. void *tmp;
  561. tmp = kmemdup(data, size, GFP_KERNEL);
  562. if (!tmp)
  563. return -ENOMEM;
  564. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  565. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  566. value, index, tmp, size, 500);
  567. kfree(tmp);
  568. return ret;
  569. }
  570. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  571. void *data, u16 type)
  572. {
  573. u16 limit = 64;
  574. int ret = 0;
  575. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  576. return -ENODEV;
  577. /* both size and indix must be 4 bytes align */
  578. if ((size & 3) || !size || (index & 3) || !data)
  579. return -EPERM;
  580. if ((u32)index + (u32)size > 0xffff)
  581. return -EPERM;
  582. while (size) {
  583. if (size > limit) {
  584. ret = get_registers(tp, index, type, limit, data);
  585. if (ret < 0)
  586. break;
  587. index += limit;
  588. data += limit;
  589. size -= limit;
  590. } else {
  591. ret = get_registers(tp, index, type, size, data);
  592. if (ret < 0)
  593. break;
  594. index += size;
  595. data += size;
  596. size = 0;
  597. break;
  598. }
  599. }
  600. if (ret == -ENODEV)
  601. set_bit(RTL8152_UNPLUG, &tp->flags);
  602. return ret;
  603. }
  604. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  605. u16 size, void *data, u16 type)
  606. {
  607. int ret;
  608. u16 byteen_start, byteen_end, byen;
  609. u16 limit = 512;
  610. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  611. return -ENODEV;
  612. /* both size and indix must be 4 bytes align */
  613. if ((size & 3) || !size || (index & 3) || !data)
  614. return -EPERM;
  615. if ((u32)index + (u32)size > 0xffff)
  616. return -EPERM;
  617. byteen_start = byteen & BYTE_EN_START_MASK;
  618. byteen_end = byteen & BYTE_EN_END_MASK;
  619. byen = byteen_start | (byteen_start << 4);
  620. ret = set_registers(tp, index, type | byen, 4, data);
  621. if (ret < 0)
  622. goto error1;
  623. index += 4;
  624. data += 4;
  625. size -= 4;
  626. if (size) {
  627. size -= 4;
  628. while (size) {
  629. if (size > limit) {
  630. ret = set_registers(tp, index,
  631. type | BYTE_EN_DWORD,
  632. limit, data);
  633. if (ret < 0)
  634. goto error1;
  635. index += limit;
  636. data += limit;
  637. size -= limit;
  638. } else {
  639. ret = set_registers(tp, index,
  640. type | BYTE_EN_DWORD,
  641. size, data);
  642. if (ret < 0)
  643. goto error1;
  644. index += size;
  645. data += size;
  646. size = 0;
  647. break;
  648. }
  649. }
  650. byen = byteen_end | (byteen_end >> 4);
  651. ret = set_registers(tp, index, type | byen, 4, data);
  652. if (ret < 0)
  653. goto error1;
  654. }
  655. error1:
  656. if (ret == -ENODEV)
  657. set_bit(RTL8152_UNPLUG, &tp->flags);
  658. return ret;
  659. }
  660. static inline
  661. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  662. {
  663. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  664. }
  665. static inline
  666. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  667. {
  668. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  669. }
  670. static inline
  671. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  672. {
  673. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  674. }
  675. static inline
  676. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  677. {
  678. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  679. }
  680. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  681. {
  682. __le32 data;
  683. generic_ocp_read(tp, index, sizeof(data), &data, type);
  684. return __le32_to_cpu(data);
  685. }
  686. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  687. {
  688. __le32 tmp = __cpu_to_le32(data);
  689. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  690. }
  691. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  692. {
  693. u32 data;
  694. __le32 tmp;
  695. u8 shift = index & 2;
  696. index &= ~3;
  697. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  698. data = __le32_to_cpu(tmp);
  699. data >>= (shift * 8);
  700. data &= 0xffff;
  701. return (u16)data;
  702. }
  703. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  704. {
  705. u32 mask = 0xffff;
  706. __le32 tmp;
  707. u16 byen = BYTE_EN_WORD;
  708. u8 shift = index & 2;
  709. data &= mask;
  710. if (index & 2) {
  711. byen <<= shift;
  712. mask <<= (shift * 8);
  713. data <<= (shift * 8);
  714. index &= ~3;
  715. }
  716. tmp = __cpu_to_le32(data);
  717. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  718. }
  719. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  720. {
  721. u32 data;
  722. __le32 tmp;
  723. u8 shift = index & 3;
  724. index &= ~3;
  725. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  726. data = __le32_to_cpu(tmp);
  727. data >>= (shift * 8);
  728. data &= 0xff;
  729. return (u8)data;
  730. }
  731. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  732. {
  733. u32 mask = 0xff;
  734. __le32 tmp;
  735. u16 byen = BYTE_EN_BYTE;
  736. u8 shift = index & 3;
  737. data &= mask;
  738. if (index & 3) {
  739. byen <<= shift;
  740. mask <<= (shift * 8);
  741. data <<= (shift * 8);
  742. index &= ~3;
  743. }
  744. tmp = __cpu_to_le32(data);
  745. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  746. }
  747. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  748. {
  749. u16 ocp_base, ocp_index;
  750. ocp_base = addr & 0xf000;
  751. if (ocp_base != tp->ocp_base) {
  752. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  753. tp->ocp_base = ocp_base;
  754. }
  755. ocp_index = (addr & 0x0fff) | 0xb000;
  756. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  757. }
  758. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  759. {
  760. u16 ocp_base, ocp_index;
  761. ocp_base = addr & 0xf000;
  762. if (ocp_base != tp->ocp_base) {
  763. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  764. tp->ocp_base = ocp_base;
  765. }
  766. ocp_index = (addr & 0x0fff) | 0xb000;
  767. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  768. }
  769. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  770. {
  771. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  772. }
  773. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  774. {
  775. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  776. }
  777. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  778. {
  779. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  780. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  781. }
  782. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  783. {
  784. struct r8152 *tp = netdev_priv(netdev);
  785. int ret;
  786. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  787. return -ENODEV;
  788. if (phy_id != R8152_PHY_ID)
  789. return -EINVAL;
  790. ret = r8152_mdio_read(tp, reg);
  791. return ret;
  792. }
  793. static
  794. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  795. {
  796. struct r8152 *tp = netdev_priv(netdev);
  797. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  798. return;
  799. if (phy_id != R8152_PHY_ID)
  800. return;
  801. r8152_mdio_write(tp, reg, val);
  802. }
  803. static int
  804. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  805. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  806. {
  807. struct r8152 *tp = netdev_priv(netdev);
  808. struct sockaddr *addr = p;
  809. int ret = -EADDRNOTAVAIL;
  810. if (!is_valid_ether_addr(addr->sa_data))
  811. goto out1;
  812. ret = usb_autopm_get_interface(tp->intf);
  813. if (ret < 0)
  814. goto out1;
  815. mutex_lock(&tp->control);
  816. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  817. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  818. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  819. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  820. mutex_unlock(&tp->control);
  821. usb_autopm_put_interface(tp->intf);
  822. out1:
  823. return ret;
  824. }
  825. static int set_ethernet_addr(struct r8152 *tp)
  826. {
  827. struct net_device *dev = tp->netdev;
  828. struct sockaddr sa;
  829. int ret;
  830. if (tp->version == RTL_VER_01)
  831. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  832. else
  833. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  834. if (ret < 0) {
  835. netif_err(tp, probe, dev, "Get ether addr fail\n");
  836. } else if (!is_valid_ether_addr(sa.sa_data)) {
  837. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  838. sa.sa_data);
  839. eth_hw_addr_random(dev);
  840. ether_addr_copy(sa.sa_data, dev->dev_addr);
  841. ret = rtl8152_set_mac_address(dev, &sa);
  842. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  843. sa.sa_data);
  844. } else {
  845. if (tp->version == RTL_VER_01)
  846. ether_addr_copy(dev->dev_addr, sa.sa_data);
  847. else
  848. ret = rtl8152_set_mac_address(dev, &sa);
  849. }
  850. return ret;
  851. }
  852. static void read_bulk_callback(struct urb *urb)
  853. {
  854. struct net_device *netdev;
  855. int status = urb->status;
  856. struct rx_agg *agg;
  857. struct r8152 *tp;
  858. agg = urb->context;
  859. if (!agg)
  860. return;
  861. tp = agg->context;
  862. if (!tp)
  863. return;
  864. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  865. return;
  866. if (!test_bit(WORK_ENABLE, &tp->flags))
  867. return;
  868. netdev = tp->netdev;
  869. /* When link down, the driver would cancel all bulks. */
  870. /* This avoid the re-submitting bulk */
  871. if (!netif_carrier_ok(netdev))
  872. return;
  873. usb_mark_last_busy(tp->udev);
  874. switch (status) {
  875. case 0:
  876. if (urb->actual_length < ETH_ZLEN)
  877. break;
  878. spin_lock(&tp->rx_lock);
  879. list_add_tail(&agg->list, &tp->rx_done);
  880. spin_unlock(&tp->rx_lock);
  881. napi_schedule(&tp->napi);
  882. return;
  883. case -ESHUTDOWN:
  884. set_bit(RTL8152_UNPLUG, &tp->flags);
  885. netif_device_detach(tp->netdev);
  886. return;
  887. case -ENOENT:
  888. return; /* the urb is in unlink state */
  889. case -ETIME:
  890. if (net_ratelimit())
  891. netdev_warn(netdev, "maybe reset is needed?\n");
  892. break;
  893. default:
  894. if (net_ratelimit())
  895. netdev_warn(netdev, "Rx status %d\n", status);
  896. break;
  897. }
  898. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  899. }
  900. static void write_bulk_callback(struct urb *urb)
  901. {
  902. struct net_device_stats *stats;
  903. struct net_device *netdev;
  904. struct tx_agg *agg;
  905. struct r8152 *tp;
  906. int status = urb->status;
  907. agg = urb->context;
  908. if (!agg)
  909. return;
  910. tp = agg->context;
  911. if (!tp)
  912. return;
  913. netdev = tp->netdev;
  914. stats = &netdev->stats;
  915. if (status) {
  916. if (net_ratelimit())
  917. netdev_warn(netdev, "Tx status %d\n", status);
  918. stats->tx_errors += agg->skb_num;
  919. } else {
  920. stats->tx_packets += agg->skb_num;
  921. stats->tx_bytes += agg->skb_len;
  922. }
  923. spin_lock(&tp->tx_lock);
  924. list_add_tail(&agg->list, &tp->tx_free);
  925. spin_unlock(&tp->tx_lock);
  926. usb_autopm_put_interface_async(tp->intf);
  927. if (!netif_carrier_ok(netdev))
  928. return;
  929. if (!test_bit(WORK_ENABLE, &tp->flags))
  930. return;
  931. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  932. return;
  933. if (!skb_queue_empty(&tp->tx_queue))
  934. napi_schedule(&tp->napi);
  935. }
  936. static void intr_callback(struct urb *urb)
  937. {
  938. struct r8152 *tp;
  939. __le16 *d;
  940. int status = urb->status;
  941. int res;
  942. tp = urb->context;
  943. if (!tp)
  944. return;
  945. if (!test_bit(WORK_ENABLE, &tp->flags))
  946. return;
  947. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  948. return;
  949. switch (status) {
  950. case 0: /* success */
  951. break;
  952. case -ECONNRESET: /* unlink */
  953. case -ESHUTDOWN:
  954. netif_device_detach(tp->netdev);
  955. case -ENOENT:
  956. case -EPROTO:
  957. netif_info(tp, intr, tp->netdev,
  958. "Stop submitting intr, status %d\n", status);
  959. return;
  960. case -EOVERFLOW:
  961. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  962. goto resubmit;
  963. /* -EPIPE: should clear the halt */
  964. default:
  965. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  966. goto resubmit;
  967. }
  968. d = urb->transfer_buffer;
  969. if (INTR_LINK & __le16_to_cpu(d[0])) {
  970. if (!netif_carrier_ok(tp->netdev)) {
  971. set_bit(RTL8152_LINK_CHG, &tp->flags);
  972. schedule_delayed_work(&tp->schedule, 0);
  973. }
  974. } else {
  975. if (netif_carrier_ok(tp->netdev)) {
  976. set_bit(RTL8152_LINK_CHG, &tp->flags);
  977. schedule_delayed_work(&tp->schedule, 0);
  978. }
  979. }
  980. resubmit:
  981. res = usb_submit_urb(urb, GFP_ATOMIC);
  982. if (res == -ENODEV) {
  983. set_bit(RTL8152_UNPLUG, &tp->flags);
  984. netif_device_detach(tp->netdev);
  985. } else if (res) {
  986. netif_err(tp, intr, tp->netdev,
  987. "can't resubmit intr, status %d\n", res);
  988. }
  989. }
  990. static inline void *rx_agg_align(void *data)
  991. {
  992. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  993. }
  994. static inline void *tx_agg_align(void *data)
  995. {
  996. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  997. }
  998. static void free_all_mem(struct r8152 *tp)
  999. {
  1000. int i;
  1001. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1002. usb_free_urb(tp->rx_info[i].urb);
  1003. tp->rx_info[i].urb = NULL;
  1004. kfree(tp->rx_info[i].buffer);
  1005. tp->rx_info[i].buffer = NULL;
  1006. tp->rx_info[i].head = NULL;
  1007. }
  1008. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1009. usb_free_urb(tp->tx_info[i].urb);
  1010. tp->tx_info[i].urb = NULL;
  1011. kfree(tp->tx_info[i].buffer);
  1012. tp->tx_info[i].buffer = NULL;
  1013. tp->tx_info[i].head = NULL;
  1014. }
  1015. usb_free_urb(tp->intr_urb);
  1016. tp->intr_urb = NULL;
  1017. kfree(tp->intr_buff);
  1018. tp->intr_buff = NULL;
  1019. }
  1020. static int alloc_all_mem(struct r8152 *tp)
  1021. {
  1022. struct net_device *netdev = tp->netdev;
  1023. struct usb_interface *intf = tp->intf;
  1024. struct usb_host_interface *alt = intf->cur_altsetting;
  1025. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1026. struct urb *urb;
  1027. int node, i;
  1028. u8 *buf;
  1029. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1030. spin_lock_init(&tp->rx_lock);
  1031. spin_lock_init(&tp->tx_lock);
  1032. INIT_LIST_HEAD(&tp->tx_free);
  1033. skb_queue_head_init(&tp->tx_queue);
  1034. skb_queue_head_init(&tp->rx_queue);
  1035. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1036. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1037. if (!buf)
  1038. goto err1;
  1039. if (buf != rx_agg_align(buf)) {
  1040. kfree(buf);
  1041. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1042. node);
  1043. if (!buf)
  1044. goto err1;
  1045. }
  1046. urb = usb_alloc_urb(0, GFP_KERNEL);
  1047. if (!urb) {
  1048. kfree(buf);
  1049. goto err1;
  1050. }
  1051. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1052. tp->rx_info[i].context = tp;
  1053. tp->rx_info[i].urb = urb;
  1054. tp->rx_info[i].buffer = buf;
  1055. tp->rx_info[i].head = rx_agg_align(buf);
  1056. }
  1057. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1058. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1059. if (!buf)
  1060. goto err1;
  1061. if (buf != tx_agg_align(buf)) {
  1062. kfree(buf);
  1063. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1064. node);
  1065. if (!buf)
  1066. goto err1;
  1067. }
  1068. urb = usb_alloc_urb(0, GFP_KERNEL);
  1069. if (!urb) {
  1070. kfree(buf);
  1071. goto err1;
  1072. }
  1073. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1074. tp->tx_info[i].context = tp;
  1075. tp->tx_info[i].urb = urb;
  1076. tp->tx_info[i].buffer = buf;
  1077. tp->tx_info[i].head = tx_agg_align(buf);
  1078. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1079. }
  1080. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1081. if (!tp->intr_urb)
  1082. goto err1;
  1083. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1084. if (!tp->intr_buff)
  1085. goto err1;
  1086. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1087. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1088. tp->intr_buff, INTBUFSIZE, intr_callback,
  1089. tp, tp->intr_interval);
  1090. return 0;
  1091. err1:
  1092. free_all_mem(tp);
  1093. return -ENOMEM;
  1094. }
  1095. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1096. {
  1097. struct tx_agg *agg = NULL;
  1098. unsigned long flags;
  1099. if (list_empty(&tp->tx_free))
  1100. return NULL;
  1101. spin_lock_irqsave(&tp->tx_lock, flags);
  1102. if (!list_empty(&tp->tx_free)) {
  1103. struct list_head *cursor;
  1104. cursor = tp->tx_free.next;
  1105. list_del_init(cursor);
  1106. agg = list_entry(cursor, struct tx_agg, list);
  1107. }
  1108. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1109. return agg;
  1110. }
  1111. /* r8152_csum_workaround()
  1112. * The hw limites the value the transport offset. When the offset is out of the
  1113. * range, calculate the checksum by sw.
  1114. */
  1115. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1116. struct sk_buff_head *list)
  1117. {
  1118. if (skb_shinfo(skb)->gso_size) {
  1119. netdev_features_t features = tp->netdev->features;
  1120. struct sk_buff_head seg_list;
  1121. struct sk_buff *segs, *nskb;
  1122. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1123. segs = skb_gso_segment(skb, features);
  1124. if (IS_ERR(segs) || !segs)
  1125. goto drop;
  1126. __skb_queue_head_init(&seg_list);
  1127. do {
  1128. nskb = segs;
  1129. segs = segs->next;
  1130. nskb->next = NULL;
  1131. __skb_queue_tail(&seg_list, nskb);
  1132. } while (segs);
  1133. skb_queue_splice(&seg_list, list);
  1134. dev_kfree_skb(skb);
  1135. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1136. if (skb_checksum_help(skb) < 0)
  1137. goto drop;
  1138. __skb_queue_head(list, skb);
  1139. } else {
  1140. struct net_device_stats *stats;
  1141. drop:
  1142. stats = &tp->netdev->stats;
  1143. stats->tx_dropped++;
  1144. dev_kfree_skb(skb);
  1145. }
  1146. }
  1147. /* msdn_giant_send_check()
  1148. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1149. * packet length for IPv6 TCP large packets.
  1150. */
  1151. static int msdn_giant_send_check(struct sk_buff *skb)
  1152. {
  1153. const struct ipv6hdr *ipv6h;
  1154. struct tcphdr *th;
  1155. int ret;
  1156. ret = skb_cow_head(skb, 0);
  1157. if (ret)
  1158. return ret;
  1159. ipv6h = ipv6_hdr(skb);
  1160. th = tcp_hdr(skb);
  1161. th->check = 0;
  1162. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1163. return ret;
  1164. }
  1165. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1166. {
  1167. if (skb_vlan_tag_present(skb)) {
  1168. u32 opts2;
  1169. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1170. desc->opts2 |= cpu_to_le32(opts2);
  1171. }
  1172. }
  1173. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1174. {
  1175. u32 opts2 = le32_to_cpu(desc->opts2);
  1176. if (opts2 & RX_VLAN_TAG)
  1177. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1178. swab16(opts2 & 0xffff));
  1179. }
  1180. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1181. struct sk_buff *skb, u32 len, u32 transport_offset)
  1182. {
  1183. u32 mss = skb_shinfo(skb)->gso_size;
  1184. u32 opts1, opts2 = 0;
  1185. int ret = TX_CSUM_SUCCESS;
  1186. WARN_ON_ONCE(len > TX_LEN_MAX);
  1187. opts1 = len | TX_FS | TX_LS;
  1188. if (mss) {
  1189. if (transport_offset > GTTCPHO_MAX) {
  1190. netif_warn(tp, tx_err, tp->netdev,
  1191. "Invalid transport offset 0x%x for TSO\n",
  1192. transport_offset);
  1193. ret = TX_CSUM_TSO;
  1194. goto unavailable;
  1195. }
  1196. switch (vlan_get_protocol(skb)) {
  1197. case htons(ETH_P_IP):
  1198. opts1 |= GTSENDV4;
  1199. break;
  1200. case htons(ETH_P_IPV6):
  1201. if (msdn_giant_send_check(skb)) {
  1202. ret = TX_CSUM_TSO;
  1203. goto unavailable;
  1204. }
  1205. opts1 |= GTSENDV6;
  1206. break;
  1207. default:
  1208. WARN_ON_ONCE(1);
  1209. break;
  1210. }
  1211. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1212. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1213. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1214. u8 ip_protocol;
  1215. if (transport_offset > TCPHO_MAX) {
  1216. netif_warn(tp, tx_err, tp->netdev,
  1217. "Invalid transport offset 0x%x\n",
  1218. transport_offset);
  1219. ret = TX_CSUM_NONE;
  1220. goto unavailable;
  1221. }
  1222. switch (vlan_get_protocol(skb)) {
  1223. case htons(ETH_P_IP):
  1224. opts2 |= IPV4_CS;
  1225. ip_protocol = ip_hdr(skb)->protocol;
  1226. break;
  1227. case htons(ETH_P_IPV6):
  1228. opts2 |= IPV6_CS;
  1229. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1230. break;
  1231. default:
  1232. ip_protocol = IPPROTO_RAW;
  1233. break;
  1234. }
  1235. if (ip_protocol == IPPROTO_TCP)
  1236. opts2 |= TCP_CS;
  1237. else if (ip_protocol == IPPROTO_UDP)
  1238. opts2 |= UDP_CS;
  1239. else
  1240. WARN_ON_ONCE(1);
  1241. opts2 |= transport_offset << TCPHO_SHIFT;
  1242. }
  1243. desc->opts2 = cpu_to_le32(opts2);
  1244. desc->opts1 = cpu_to_le32(opts1);
  1245. unavailable:
  1246. return ret;
  1247. }
  1248. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1249. {
  1250. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1251. int remain, ret;
  1252. u8 *tx_data;
  1253. __skb_queue_head_init(&skb_head);
  1254. spin_lock(&tx_queue->lock);
  1255. skb_queue_splice_init(tx_queue, &skb_head);
  1256. spin_unlock(&tx_queue->lock);
  1257. tx_data = agg->head;
  1258. agg->skb_num = 0;
  1259. agg->skb_len = 0;
  1260. remain = agg_buf_sz;
  1261. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1262. struct tx_desc *tx_desc;
  1263. struct sk_buff *skb;
  1264. unsigned int len;
  1265. u32 offset;
  1266. skb = __skb_dequeue(&skb_head);
  1267. if (!skb)
  1268. break;
  1269. len = skb->len + sizeof(*tx_desc);
  1270. if (len > remain) {
  1271. __skb_queue_head(&skb_head, skb);
  1272. break;
  1273. }
  1274. tx_data = tx_agg_align(tx_data);
  1275. tx_desc = (struct tx_desc *)tx_data;
  1276. offset = (u32)skb_transport_offset(skb);
  1277. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1278. r8152_csum_workaround(tp, skb, &skb_head);
  1279. continue;
  1280. }
  1281. rtl_tx_vlan_tag(tx_desc, skb);
  1282. tx_data += sizeof(*tx_desc);
  1283. len = skb->len;
  1284. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1285. struct net_device_stats *stats = &tp->netdev->stats;
  1286. stats->tx_dropped++;
  1287. dev_kfree_skb_any(skb);
  1288. tx_data -= sizeof(*tx_desc);
  1289. continue;
  1290. }
  1291. tx_data += len;
  1292. agg->skb_len += len;
  1293. agg->skb_num++;
  1294. dev_kfree_skb_any(skb);
  1295. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1296. }
  1297. if (!skb_queue_empty(&skb_head)) {
  1298. spin_lock(&tx_queue->lock);
  1299. skb_queue_splice(&skb_head, tx_queue);
  1300. spin_unlock(&tx_queue->lock);
  1301. }
  1302. netif_tx_lock(tp->netdev);
  1303. if (netif_queue_stopped(tp->netdev) &&
  1304. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1305. netif_wake_queue(tp->netdev);
  1306. netif_tx_unlock(tp->netdev);
  1307. ret = usb_autopm_get_interface_async(tp->intf);
  1308. if (ret < 0)
  1309. goto out_tx_fill;
  1310. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1311. agg->head, (int)(tx_data - (u8 *)agg->head),
  1312. (usb_complete_t)write_bulk_callback, agg);
  1313. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1314. if (ret < 0)
  1315. usb_autopm_put_interface_async(tp->intf);
  1316. out_tx_fill:
  1317. return ret;
  1318. }
  1319. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1320. {
  1321. u8 checksum = CHECKSUM_NONE;
  1322. u32 opts2, opts3;
  1323. if (tp->version == RTL_VER_01)
  1324. goto return_result;
  1325. opts2 = le32_to_cpu(rx_desc->opts2);
  1326. opts3 = le32_to_cpu(rx_desc->opts3);
  1327. if (opts2 & RD_IPV4_CS) {
  1328. if (opts3 & IPF)
  1329. checksum = CHECKSUM_NONE;
  1330. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1331. checksum = CHECKSUM_NONE;
  1332. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1333. checksum = CHECKSUM_NONE;
  1334. else
  1335. checksum = CHECKSUM_UNNECESSARY;
  1336. } else if (RD_IPV6_CS) {
  1337. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1338. checksum = CHECKSUM_UNNECESSARY;
  1339. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1340. checksum = CHECKSUM_UNNECESSARY;
  1341. }
  1342. return_result:
  1343. return checksum;
  1344. }
  1345. static int rx_bottom(struct r8152 *tp, int budget)
  1346. {
  1347. unsigned long flags;
  1348. struct list_head *cursor, *next, rx_queue;
  1349. int ret = 0, work_done = 0;
  1350. if (!skb_queue_empty(&tp->rx_queue)) {
  1351. while (work_done < budget) {
  1352. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1353. struct net_device *netdev = tp->netdev;
  1354. struct net_device_stats *stats = &netdev->stats;
  1355. unsigned int pkt_len;
  1356. if (!skb)
  1357. break;
  1358. pkt_len = skb->len;
  1359. napi_gro_receive(&tp->napi, skb);
  1360. work_done++;
  1361. stats->rx_packets++;
  1362. stats->rx_bytes += pkt_len;
  1363. }
  1364. }
  1365. if (list_empty(&tp->rx_done))
  1366. goto out1;
  1367. INIT_LIST_HEAD(&rx_queue);
  1368. spin_lock_irqsave(&tp->rx_lock, flags);
  1369. list_splice_init(&tp->rx_done, &rx_queue);
  1370. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1371. list_for_each_safe(cursor, next, &rx_queue) {
  1372. struct rx_desc *rx_desc;
  1373. struct rx_agg *agg;
  1374. int len_used = 0;
  1375. struct urb *urb;
  1376. u8 *rx_data;
  1377. list_del_init(cursor);
  1378. agg = list_entry(cursor, struct rx_agg, list);
  1379. urb = agg->urb;
  1380. if (urb->actual_length < ETH_ZLEN)
  1381. goto submit;
  1382. rx_desc = agg->head;
  1383. rx_data = agg->head;
  1384. len_used += sizeof(struct rx_desc);
  1385. while (urb->actual_length > len_used) {
  1386. struct net_device *netdev = tp->netdev;
  1387. struct net_device_stats *stats = &netdev->stats;
  1388. unsigned int pkt_len;
  1389. struct sk_buff *skb;
  1390. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1391. if (pkt_len < ETH_ZLEN)
  1392. break;
  1393. len_used += pkt_len;
  1394. if (urb->actual_length < len_used)
  1395. break;
  1396. pkt_len -= CRC_SIZE;
  1397. rx_data += sizeof(struct rx_desc);
  1398. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1399. if (!skb) {
  1400. stats->rx_dropped++;
  1401. goto find_next_rx;
  1402. }
  1403. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1404. memcpy(skb->data, rx_data, pkt_len);
  1405. skb_put(skb, pkt_len);
  1406. skb->protocol = eth_type_trans(skb, netdev);
  1407. rtl_rx_vlan_tag(rx_desc, skb);
  1408. if (work_done < budget) {
  1409. napi_gro_receive(&tp->napi, skb);
  1410. work_done++;
  1411. stats->rx_packets++;
  1412. stats->rx_bytes += pkt_len;
  1413. } else {
  1414. __skb_queue_tail(&tp->rx_queue, skb);
  1415. }
  1416. find_next_rx:
  1417. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1418. rx_desc = (struct rx_desc *)rx_data;
  1419. len_used = (int)(rx_data - (u8 *)agg->head);
  1420. len_used += sizeof(struct rx_desc);
  1421. }
  1422. submit:
  1423. if (!ret) {
  1424. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1425. } else {
  1426. urb->actual_length = 0;
  1427. list_add_tail(&agg->list, next);
  1428. }
  1429. }
  1430. if (!list_empty(&rx_queue)) {
  1431. spin_lock_irqsave(&tp->rx_lock, flags);
  1432. list_splice_tail(&rx_queue, &tp->rx_done);
  1433. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1434. }
  1435. out1:
  1436. return work_done;
  1437. }
  1438. static void tx_bottom(struct r8152 *tp)
  1439. {
  1440. int res;
  1441. do {
  1442. struct tx_agg *agg;
  1443. if (skb_queue_empty(&tp->tx_queue))
  1444. break;
  1445. agg = r8152_get_tx_agg(tp);
  1446. if (!agg)
  1447. break;
  1448. res = r8152_tx_agg_fill(tp, agg);
  1449. if (res) {
  1450. struct net_device *netdev = tp->netdev;
  1451. if (res == -ENODEV) {
  1452. set_bit(RTL8152_UNPLUG, &tp->flags);
  1453. netif_device_detach(netdev);
  1454. } else {
  1455. struct net_device_stats *stats = &netdev->stats;
  1456. unsigned long flags;
  1457. netif_warn(tp, tx_err, netdev,
  1458. "failed tx_urb %d\n", res);
  1459. stats->tx_dropped += agg->skb_num;
  1460. spin_lock_irqsave(&tp->tx_lock, flags);
  1461. list_add_tail(&agg->list, &tp->tx_free);
  1462. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1463. }
  1464. }
  1465. } while (res == 0);
  1466. }
  1467. static void bottom_half(struct r8152 *tp)
  1468. {
  1469. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1470. return;
  1471. if (!test_bit(WORK_ENABLE, &tp->flags))
  1472. return;
  1473. /* When link down, the driver would cancel all bulks. */
  1474. /* This avoid the re-submitting bulk */
  1475. if (!netif_carrier_ok(tp->netdev))
  1476. return;
  1477. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1478. tx_bottom(tp);
  1479. }
  1480. static int r8152_poll(struct napi_struct *napi, int budget)
  1481. {
  1482. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1483. int work_done;
  1484. work_done = rx_bottom(tp, budget);
  1485. bottom_half(tp);
  1486. if (work_done < budget) {
  1487. napi_complete(napi);
  1488. if (!list_empty(&tp->rx_done))
  1489. napi_schedule(napi);
  1490. }
  1491. return work_done;
  1492. }
  1493. static
  1494. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1495. {
  1496. int ret;
  1497. /* The rx would be stopped, so skip submitting */
  1498. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1499. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1500. return 0;
  1501. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1502. agg->head, agg_buf_sz,
  1503. (usb_complete_t)read_bulk_callback, agg);
  1504. ret = usb_submit_urb(agg->urb, mem_flags);
  1505. if (ret == -ENODEV) {
  1506. set_bit(RTL8152_UNPLUG, &tp->flags);
  1507. netif_device_detach(tp->netdev);
  1508. } else if (ret) {
  1509. struct urb *urb = agg->urb;
  1510. unsigned long flags;
  1511. urb->actual_length = 0;
  1512. spin_lock_irqsave(&tp->rx_lock, flags);
  1513. list_add_tail(&agg->list, &tp->rx_done);
  1514. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1515. netif_err(tp, rx_err, tp->netdev,
  1516. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1517. napi_schedule(&tp->napi);
  1518. }
  1519. return ret;
  1520. }
  1521. static void rtl_drop_queued_tx(struct r8152 *tp)
  1522. {
  1523. struct net_device_stats *stats = &tp->netdev->stats;
  1524. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1525. struct sk_buff *skb;
  1526. if (skb_queue_empty(tx_queue))
  1527. return;
  1528. __skb_queue_head_init(&skb_head);
  1529. spin_lock_bh(&tx_queue->lock);
  1530. skb_queue_splice_init(tx_queue, &skb_head);
  1531. spin_unlock_bh(&tx_queue->lock);
  1532. while ((skb = __skb_dequeue(&skb_head))) {
  1533. dev_kfree_skb(skb);
  1534. stats->tx_dropped++;
  1535. }
  1536. }
  1537. static void rtl8152_tx_timeout(struct net_device *netdev)
  1538. {
  1539. struct r8152 *tp = netdev_priv(netdev);
  1540. int i;
  1541. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1542. for (i = 0; i < RTL8152_MAX_TX; i++)
  1543. usb_unlink_urb(tp->tx_info[i].urb);
  1544. }
  1545. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1546. {
  1547. struct r8152 *tp = netdev_priv(netdev);
  1548. if (netif_carrier_ok(netdev)) {
  1549. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1550. schedule_delayed_work(&tp->schedule, 0);
  1551. }
  1552. }
  1553. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1554. {
  1555. struct r8152 *tp = netdev_priv(netdev);
  1556. u32 mc_filter[2]; /* Multicast hash filter */
  1557. __le32 tmp[2];
  1558. u32 ocp_data;
  1559. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1560. netif_stop_queue(netdev);
  1561. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1562. ocp_data &= ~RCR_ACPT_ALL;
  1563. ocp_data |= RCR_AB | RCR_APM;
  1564. if (netdev->flags & IFF_PROMISC) {
  1565. /* Unconditionally log net taps. */
  1566. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1567. ocp_data |= RCR_AM | RCR_AAP;
  1568. mc_filter[1] = 0xffffffff;
  1569. mc_filter[0] = 0xffffffff;
  1570. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1571. (netdev->flags & IFF_ALLMULTI)) {
  1572. /* Too many to filter perfectly -- accept all multicasts. */
  1573. ocp_data |= RCR_AM;
  1574. mc_filter[1] = 0xffffffff;
  1575. mc_filter[0] = 0xffffffff;
  1576. } else {
  1577. struct netdev_hw_addr *ha;
  1578. mc_filter[1] = 0;
  1579. mc_filter[0] = 0;
  1580. netdev_for_each_mc_addr(ha, netdev) {
  1581. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1582. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1583. ocp_data |= RCR_AM;
  1584. }
  1585. }
  1586. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1587. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1588. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1589. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1590. netif_wake_queue(netdev);
  1591. }
  1592. static netdev_features_t
  1593. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1594. netdev_features_t features)
  1595. {
  1596. u32 mss = skb_shinfo(skb)->gso_size;
  1597. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1598. int offset = skb_transport_offset(skb);
  1599. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1600. features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
  1601. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1602. features &= ~NETIF_F_GSO_MASK;
  1603. return features;
  1604. }
  1605. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1606. struct net_device *netdev)
  1607. {
  1608. struct r8152 *tp = netdev_priv(netdev);
  1609. skb_tx_timestamp(skb);
  1610. skb_queue_tail(&tp->tx_queue, skb);
  1611. if (!list_empty(&tp->tx_free)) {
  1612. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1613. set_bit(SCHEDULE_NAPI, &tp->flags);
  1614. schedule_delayed_work(&tp->schedule, 0);
  1615. } else {
  1616. usb_mark_last_busy(tp->udev);
  1617. napi_schedule(&tp->napi);
  1618. }
  1619. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1620. netif_stop_queue(netdev);
  1621. }
  1622. return NETDEV_TX_OK;
  1623. }
  1624. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1625. {
  1626. u32 ocp_data;
  1627. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1628. ocp_data &= ~FMC_FCR_MCU_EN;
  1629. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1630. ocp_data |= FMC_FCR_MCU_EN;
  1631. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1632. }
  1633. static void rtl8152_nic_reset(struct r8152 *tp)
  1634. {
  1635. int i;
  1636. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1637. for (i = 0; i < 1000; i++) {
  1638. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1639. break;
  1640. usleep_range(100, 400);
  1641. }
  1642. }
  1643. static void set_tx_qlen(struct r8152 *tp)
  1644. {
  1645. struct net_device *netdev = tp->netdev;
  1646. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1647. sizeof(struct tx_desc));
  1648. }
  1649. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1650. {
  1651. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1652. }
  1653. static void rtl_set_eee_plus(struct r8152 *tp)
  1654. {
  1655. u32 ocp_data;
  1656. u8 speed;
  1657. speed = rtl8152_get_speed(tp);
  1658. if (speed & _10bps) {
  1659. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1660. ocp_data |= EEEP_CR_EEEP_TX;
  1661. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1662. } else {
  1663. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1664. ocp_data &= ~EEEP_CR_EEEP_TX;
  1665. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1666. }
  1667. }
  1668. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1669. {
  1670. u32 ocp_data;
  1671. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1672. if (enable)
  1673. ocp_data |= RXDY_GATED_EN;
  1674. else
  1675. ocp_data &= ~RXDY_GATED_EN;
  1676. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1677. }
  1678. static int rtl_start_rx(struct r8152 *tp)
  1679. {
  1680. int i, ret = 0;
  1681. napi_disable(&tp->napi);
  1682. INIT_LIST_HEAD(&tp->rx_done);
  1683. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1684. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1685. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1686. if (ret)
  1687. break;
  1688. }
  1689. napi_enable(&tp->napi);
  1690. if (ret && ++i < RTL8152_MAX_RX) {
  1691. struct list_head rx_queue;
  1692. unsigned long flags;
  1693. INIT_LIST_HEAD(&rx_queue);
  1694. do {
  1695. struct rx_agg *agg = &tp->rx_info[i++];
  1696. struct urb *urb = agg->urb;
  1697. urb->actual_length = 0;
  1698. list_add_tail(&agg->list, &rx_queue);
  1699. } while (i < RTL8152_MAX_RX);
  1700. spin_lock_irqsave(&tp->rx_lock, flags);
  1701. list_splice_tail(&rx_queue, &tp->rx_done);
  1702. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1703. }
  1704. return ret;
  1705. }
  1706. static int rtl_stop_rx(struct r8152 *tp)
  1707. {
  1708. int i;
  1709. for (i = 0; i < RTL8152_MAX_RX; i++)
  1710. usb_kill_urb(tp->rx_info[i].urb);
  1711. while (!skb_queue_empty(&tp->rx_queue))
  1712. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1713. return 0;
  1714. }
  1715. static int rtl_enable(struct r8152 *tp)
  1716. {
  1717. u32 ocp_data;
  1718. r8152b_reset_packet_filter(tp);
  1719. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1720. ocp_data |= CR_RE | CR_TE;
  1721. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1722. rxdy_gated_en(tp, false);
  1723. return 0;
  1724. }
  1725. static int rtl8152_enable(struct r8152 *tp)
  1726. {
  1727. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1728. return -ENODEV;
  1729. set_tx_qlen(tp);
  1730. rtl_set_eee_plus(tp);
  1731. return rtl_enable(tp);
  1732. }
  1733. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1734. {
  1735. u32 ocp_data = tp->coalesce / 8;
  1736. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1737. }
  1738. static void r8153_set_rx_early_size(struct r8152 *tp)
  1739. {
  1740. u32 mtu = tp->netdev->mtu;
  1741. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
  1742. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1743. }
  1744. static int rtl8153_enable(struct r8152 *tp)
  1745. {
  1746. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1747. return -ENODEV;
  1748. set_tx_qlen(tp);
  1749. rtl_set_eee_plus(tp);
  1750. r8153_set_rx_early_timeout(tp);
  1751. r8153_set_rx_early_size(tp);
  1752. return rtl_enable(tp);
  1753. }
  1754. static void rtl_disable(struct r8152 *tp)
  1755. {
  1756. u32 ocp_data;
  1757. int i;
  1758. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1759. rtl_drop_queued_tx(tp);
  1760. return;
  1761. }
  1762. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1763. ocp_data &= ~RCR_ACPT_ALL;
  1764. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1765. rtl_drop_queued_tx(tp);
  1766. for (i = 0; i < RTL8152_MAX_TX; i++)
  1767. usb_kill_urb(tp->tx_info[i].urb);
  1768. rxdy_gated_en(tp, true);
  1769. for (i = 0; i < 1000; i++) {
  1770. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1771. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1772. break;
  1773. usleep_range(1000, 2000);
  1774. }
  1775. for (i = 0; i < 1000; i++) {
  1776. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1777. break;
  1778. usleep_range(1000, 2000);
  1779. }
  1780. rtl_stop_rx(tp);
  1781. rtl8152_nic_reset(tp);
  1782. }
  1783. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1784. {
  1785. u32 ocp_data;
  1786. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1787. if (enable)
  1788. ocp_data |= POWER_CUT;
  1789. else
  1790. ocp_data &= ~POWER_CUT;
  1791. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1792. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1793. ocp_data &= ~RESUME_INDICATE;
  1794. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1795. }
  1796. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1797. {
  1798. u32 ocp_data;
  1799. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1800. if (enable)
  1801. ocp_data |= CPCR_RX_VLAN;
  1802. else
  1803. ocp_data &= ~CPCR_RX_VLAN;
  1804. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1805. }
  1806. static int rtl8152_set_features(struct net_device *dev,
  1807. netdev_features_t features)
  1808. {
  1809. netdev_features_t changed = features ^ dev->features;
  1810. struct r8152 *tp = netdev_priv(dev);
  1811. int ret;
  1812. ret = usb_autopm_get_interface(tp->intf);
  1813. if (ret < 0)
  1814. goto out;
  1815. mutex_lock(&tp->control);
  1816. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1817. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1818. rtl_rx_vlan_en(tp, true);
  1819. else
  1820. rtl_rx_vlan_en(tp, false);
  1821. }
  1822. mutex_unlock(&tp->control);
  1823. usb_autopm_put_interface(tp->intf);
  1824. out:
  1825. return ret;
  1826. }
  1827. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1828. static u32 __rtl_get_wol(struct r8152 *tp)
  1829. {
  1830. u32 ocp_data;
  1831. u32 wolopts = 0;
  1832. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1833. if (!(ocp_data & LAN_WAKE_EN))
  1834. return 0;
  1835. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1836. if (ocp_data & LINK_ON_WAKE_EN)
  1837. wolopts |= WAKE_PHY;
  1838. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1839. if (ocp_data & UWF_EN)
  1840. wolopts |= WAKE_UCAST;
  1841. if (ocp_data & BWF_EN)
  1842. wolopts |= WAKE_BCAST;
  1843. if (ocp_data & MWF_EN)
  1844. wolopts |= WAKE_MCAST;
  1845. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1846. if (ocp_data & MAGIC_EN)
  1847. wolopts |= WAKE_MAGIC;
  1848. return wolopts;
  1849. }
  1850. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1851. {
  1852. u32 ocp_data;
  1853. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1854. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1855. ocp_data &= ~LINK_ON_WAKE_EN;
  1856. if (wolopts & WAKE_PHY)
  1857. ocp_data |= LINK_ON_WAKE_EN;
  1858. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1859. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1860. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1861. if (wolopts & WAKE_UCAST)
  1862. ocp_data |= UWF_EN;
  1863. if (wolopts & WAKE_BCAST)
  1864. ocp_data |= BWF_EN;
  1865. if (wolopts & WAKE_MCAST)
  1866. ocp_data |= MWF_EN;
  1867. if (wolopts & WAKE_ANY)
  1868. ocp_data |= LAN_WAKE_EN;
  1869. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1870. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1871. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1872. ocp_data &= ~MAGIC_EN;
  1873. if (wolopts & WAKE_MAGIC)
  1874. ocp_data |= MAGIC_EN;
  1875. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1876. if (wolopts & WAKE_ANY)
  1877. device_set_wakeup_enable(&tp->udev->dev, true);
  1878. else
  1879. device_set_wakeup_enable(&tp->udev->dev, false);
  1880. }
  1881. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1882. {
  1883. if (enable) {
  1884. u32 ocp_data;
  1885. __rtl_set_wol(tp, WAKE_ANY);
  1886. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1887. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1888. ocp_data |= LINK_OFF_WAKE_EN;
  1889. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1890. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1891. } else {
  1892. __rtl_set_wol(tp, tp->saved_wolopts);
  1893. }
  1894. }
  1895. static void rtl_phy_reset(struct r8152 *tp)
  1896. {
  1897. u16 data;
  1898. int i;
  1899. clear_bit(PHY_RESET, &tp->flags);
  1900. data = r8152_mdio_read(tp, MII_BMCR);
  1901. /* don't reset again before the previous one complete */
  1902. if (data & BMCR_RESET)
  1903. return;
  1904. data |= BMCR_RESET;
  1905. r8152_mdio_write(tp, MII_BMCR, data);
  1906. for (i = 0; i < 50; i++) {
  1907. msleep(20);
  1908. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1909. break;
  1910. }
  1911. }
  1912. static void r8153_teredo_off(struct r8152 *tp)
  1913. {
  1914. u32 ocp_data;
  1915. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1916. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1917. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1918. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1919. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1920. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1921. }
  1922. static void r8152b_disable_aldps(struct r8152 *tp)
  1923. {
  1924. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1925. msleep(20);
  1926. }
  1927. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1928. {
  1929. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1930. LINKENA | DIS_SDSAVE);
  1931. }
  1932. static void rtl8152_disable(struct r8152 *tp)
  1933. {
  1934. r8152b_disable_aldps(tp);
  1935. rtl_disable(tp);
  1936. r8152b_enable_aldps(tp);
  1937. }
  1938. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1939. {
  1940. u16 data;
  1941. data = r8152_mdio_read(tp, MII_BMCR);
  1942. if (data & BMCR_PDOWN) {
  1943. data &= ~BMCR_PDOWN;
  1944. r8152_mdio_write(tp, MII_BMCR, data);
  1945. }
  1946. set_bit(PHY_RESET, &tp->flags);
  1947. }
  1948. static void r8152b_exit_oob(struct r8152 *tp)
  1949. {
  1950. u32 ocp_data;
  1951. int i;
  1952. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1953. ocp_data &= ~RCR_ACPT_ALL;
  1954. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1955. rxdy_gated_en(tp, true);
  1956. r8153_teredo_off(tp);
  1957. r8152b_hw_phy_cfg(tp);
  1958. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1959. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1960. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1961. ocp_data &= ~NOW_IS_OOB;
  1962. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1963. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1964. ocp_data &= ~MCU_BORW_EN;
  1965. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1966. for (i = 0; i < 1000; i++) {
  1967. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1968. if (ocp_data & LINK_LIST_READY)
  1969. break;
  1970. usleep_range(1000, 2000);
  1971. }
  1972. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1973. ocp_data |= RE_INIT_LL;
  1974. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1975. for (i = 0; i < 1000; i++) {
  1976. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1977. if (ocp_data & LINK_LIST_READY)
  1978. break;
  1979. usleep_range(1000, 2000);
  1980. }
  1981. rtl8152_nic_reset(tp);
  1982. /* rx share fifo credit full threshold */
  1983. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1984. if (tp->udev->speed == USB_SPEED_FULL ||
  1985. tp->udev->speed == USB_SPEED_LOW) {
  1986. /* rx share fifo credit near full threshold */
  1987. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1988. RXFIFO_THR2_FULL);
  1989. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1990. RXFIFO_THR3_FULL);
  1991. } else {
  1992. /* rx share fifo credit near full threshold */
  1993. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1994. RXFIFO_THR2_HIGH);
  1995. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1996. RXFIFO_THR3_HIGH);
  1997. }
  1998. /* TX share fifo free credit full threshold */
  1999. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2000. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2001. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2002. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2003. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2004. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2005. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2006. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2007. ocp_data |= TCR0_AUTO_FIFO;
  2008. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2009. }
  2010. static void r8152b_enter_oob(struct r8152 *tp)
  2011. {
  2012. u32 ocp_data;
  2013. int i;
  2014. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2015. ocp_data &= ~NOW_IS_OOB;
  2016. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2017. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2018. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2019. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2020. rtl_disable(tp);
  2021. for (i = 0; i < 1000; i++) {
  2022. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2023. if (ocp_data & LINK_LIST_READY)
  2024. break;
  2025. usleep_range(1000, 2000);
  2026. }
  2027. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2028. ocp_data |= RE_INIT_LL;
  2029. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2030. for (i = 0; i < 1000; i++) {
  2031. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2032. if (ocp_data & LINK_LIST_READY)
  2033. break;
  2034. usleep_range(1000, 2000);
  2035. }
  2036. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2037. rtl_rx_vlan_en(tp, true);
  2038. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2039. ocp_data |= ALDPS_PROXY_MODE;
  2040. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2041. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2042. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2043. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2044. rxdy_gated_en(tp, false);
  2045. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2046. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2047. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2048. }
  2049. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2050. {
  2051. u32 ocp_data;
  2052. u16 data;
  2053. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2054. data = r8152_mdio_read(tp, MII_BMCR);
  2055. if (data & BMCR_PDOWN) {
  2056. data &= ~BMCR_PDOWN;
  2057. r8152_mdio_write(tp, MII_BMCR, data);
  2058. }
  2059. if (tp->version == RTL_VER_03) {
  2060. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2061. data &= ~CTAP_SHORT_EN;
  2062. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2063. }
  2064. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2065. data |= EEE_CLKDIV_EN;
  2066. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2067. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2068. data |= EN_10M_BGOFF;
  2069. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2070. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2071. data |= EN_10M_PLLOFF;
  2072. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2073. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2074. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2075. ocp_data |= PFM_PWM_SWITCH;
  2076. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2077. /* Enable LPF corner auto tune */
  2078. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2079. /* Adjust 10M Amplitude */
  2080. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2081. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2082. set_bit(PHY_RESET, &tp->flags);
  2083. }
  2084. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  2085. {
  2086. u8 u1u2[8];
  2087. if (enable)
  2088. memset(u1u2, 0xff, sizeof(u1u2));
  2089. else
  2090. memset(u1u2, 0x00, sizeof(u1u2));
  2091. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  2092. }
  2093. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  2094. {
  2095. u32 ocp_data;
  2096. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  2097. if (enable)
  2098. ocp_data |= U2P3_ENABLE;
  2099. else
  2100. ocp_data &= ~U2P3_ENABLE;
  2101. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  2102. }
  2103. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  2104. {
  2105. u32 ocp_data;
  2106. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  2107. if (enable)
  2108. ocp_data |= PWR_EN | PHASE2_EN;
  2109. else
  2110. ocp_data &= ~(PWR_EN | PHASE2_EN);
  2111. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  2112. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  2113. ocp_data &= ~PCUT_STATUS;
  2114. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  2115. }
  2116. static void r8153_first_init(struct r8152 *tp)
  2117. {
  2118. u32 ocp_data;
  2119. int i;
  2120. rxdy_gated_en(tp, true);
  2121. r8153_teredo_off(tp);
  2122. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2123. ocp_data &= ~RCR_ACPT_ALL;
  2124. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2125. r8153_hw_phy_cfg(tp);
  2126. rtl8152_nic_reset(tp);
  2127. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2128. ocp_data &= ~NOW_IS_OOB;
  2129. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2130. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2131. ocp_data &= ~MCU_BORW_EN;
  2132. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2133. for (i = 0; i < 1000; i++) {
  2134. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2135. if (ocp_data & LINK_LIST_READY)
  2136. break;
  2137. usleep_range(1000, 2000);
  2138. }
  2139. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2140. ocp_data |= RE_INIT_LL;
  2141. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2142. for (i = 0; i < 1000; i++) {
  2143. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2144. if (ocp_data & LINK_LIST_READY)
  2145. break;
  2146. usleep_range(1000, 2000);
  2147. }
  2148. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2149. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2150. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2151. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2152. ocp_data |= TCR0_AUTO_FIFO;
  2153. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2154. rtl8152_nic_reset(tp);
  2155. /* rx share fifo credit full threshold */
  2156. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2157. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2158. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2159. /* TX share fifo free credit full threshold */
  2160. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2161. /* rx aggregation */
  2162. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2163. ocp_data &= ~RX_AGG_DISABLE;
  2164. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2165. }
  2166. static void r8153_enter_oob(struct r8152 *tp)
  2167. {
  2168. u32 ocp_data;
  2169. int i;
  2170. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2171. ocp_data &= ~NOW_IS_OOB;
  2172. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2173. rtl_disable(tp);
  2174. for (i = 0; i < 1000; i++) {
  2175. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2176. if (ocp_data & LINK_LIST_READY)
  2177. break;
  2178. usleep_range(1000, 2000);
  2179. }
  2180. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2181. ocp_data |= RE_INIT_LL;
  2182. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2183. for (i = 0; i < 1000; i++) {
  2184. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2185. if (ocp_data & LINK_LIST_READY)
  2186. break;
  2187. usleep_range(1000, 2000);
  2188. }
  2189. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2190. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2191. ocp_data &= ~TEREDO_WAKE_MASK;
  2192. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2193. rtl_rx_vlan_en(tp, true);
  2194. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2195. ocp_data |= ALDPS_PROXY_MODE;
  2196. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2197. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2198. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2199. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2200. rxdy_gated_en(tp, false);
  2201. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2202. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2203. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2204. }
  2205. static void r8153_disable_aldps(struct r8152 *tp)
  2206. {
  2207. u16 data;
  2208. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2209. data &= ~EN_ALDPS;
  2210. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2211. msleep(20);
  2212. }
  2213. static void r8153_enable_aldps(struct r8152 *tp)
  2214. {
  2215. u16 data;
  2216. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2217. data |= EN_ALDPS;
  2218. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2219. }
  2220. static void rtl8153_disable(struct r8152 *tp)
  2221. {
  2222. r8153_disable_aldps(tp);
  2223. rtl_disable(tp);
  2224. r8153_enable_aldps(tp);
  2225. }
  2226. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2227. {
  2228. u16 bmcr, anar, gbcr;
  2229. int ret = 0;
  2230. cancel_delayed_work_sync(&tp->schedule);
  2231. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2232. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2233. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2234. if (tp->mii.supports_gmii) {
  2235. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2236. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2237. } else {
  2238. gbcr = 0;
  2239. }
  2240. if (autoneg == AUTONEG_DISABLE) {
  2241. if (speed == SPEED_10) {
  2242. bmcr = 0;
  2243. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2244. } else if (speed == SPEED_100) {
  2245. bmcr = BMCR_SPEED100;
  2246. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2247. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2248. bmcr = BMCR_SPEED1000;
  2249. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2250. } else {
  2251. ret = -EINVAL;
  2252. goto out;
  2253. }
  2254. if (duplex == DUPLEX_FULL)
  2255. bmcr |= BMCR_FULLDPLX;
  2256. } else {
  2257. if (speed == SPEED_10) {
  2258. if (duplex == DUPLEX_FULL)
  2259. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2260. else
  2261. anar |= ADVERTISE_10HALF;
  2262. } else if (speed == SPEED_100) {
  2263. if (duplex == DUPLEX_FULL) {
  2264. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2265. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2266. } else {
  2267. anar |= ADVERTISE_10HALF;
  2268. anar |= ADVERTISE_100HALF;
  2269. }
  2270. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2271. if (duplex == DUPLEX_FULL) {
  2272. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2273. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2274. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2275. } else {
  2276. anar |= ADVERTISE_10HALF;
  2277. anar |= ADVERTISE_100HALF;
  2278. gbcr |= ADVERTISE_1000HALF;
  2279. }
  2280. } else {
  2281. ret = -EINVAL;
  2282. goto out;
  2283. }
  2284. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2285. }
  2286. if (test_bit(PHY_RESET, &tp->flags))
  2287. bmcr |= BMCR_RESET;
  2288. if (tp->mii.supports_gmii)
  2289. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2290. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2291. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2292. if (test_bit(PHY_RESET, &tp->flags)) {
  2293. int i;
  2294. clear_bit(PHY_RESET, &tp->flags);
  2295. for (i = 0; i < 50; i++) {
  2296. msleep(20);
  2297. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2298. break;
  2299. }
  2300. }
  2301. out:
  2302. return ret;
  2303. }
  2304. static void rtl8152_up(struct r8152 *tp)
  2305. {
  2306. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2307. return;
  2308. r8152b_disable_aldps(tp);
  2309. r8152b_exit_oob(tp);
  2310. r8152b_enable_aldps(tp);
  2311. }
  2312. static void rtl8152_down(struct r8152 *tp)
  2313. {
  2314. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2315. rtl_drop_queued_tx(tp);
  2316. return;
  2317. }
  2318. r8152_power_cut_en(tp, false);
  2319. r8152b_disable_aldps(tp);
  2320. r8152b_enter_oob(tp);
  2321. r8152b_enable_aldps(tp);
  2322. }
  2323. static void rtl8153_up(struct r8152 *tp)
  2324. {
  2325. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2326. return;
  2327. r8153_disable_aldps(tp);
  2328. r8153_first_init(tp);
  2329. r8153_enable_aldps(tp);
  2330. }
  2331. static void rtl8153_down(struct r8152 *tp)
  2332. {
  2333. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2334. rtl_drop_queued_tx(tp);
  2335. return;
  2336. }
  2337. r8153_u1u2en(tp, false);
  2338. r8153_power_cut_en(tp, false);
  2339. r8153_disable_aldps(tp);
  2340. r8153_enter_oob(tp);
  2341. r8153_enable_aldps(tp);
  2342. }
  2343. static void set_carrier(struct r8152 *tp)
  2344. {
  2345. struct net_device *netdev = tp->netdev;
  2346. u8 speed;
  2347. clear_bit(RTL8152_LINK_CHG, &tp->flags);
  2348. speed = rtl8152_get_speed(tp);
  2349. if (speed & LINK_STATUS) {
  2350. if (!netif_carrier_ok(netdev)) {
  2351. tp->rtl_ops.enable(tp);
  2352. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2353. netif_carrier_on(netdev);
  2354. rtl_start_rx(tp);
  2355. }
  2356. } else {
  2357. if (netif_carrier_ok(netdev)) {
  2358. netif_carrier_off(netdev);
  2359. napi_disable(&tp->napi);
  2360. tp->rtl_ops.disable(tp);
  2361. napi_enable(&tp->napi);
  2362. }
  2363. }
  2364. }
  2365. static void rtl_work_func_t(struct work_struct *work)
  2366. {
  2367. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2368. /* If the device is unplugged or !netif_running(), the workqueue
  2369. * doesn't need to wake the device, and could return directly.
  2370. */
  2371. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2372. return;
  2373. if (usb_autopm_get_interface(tp->intf) < 0)
  2374. return;
  2375. if (!test_bit(WORK_ENABLE, &tp->flags))
  2376. goto out1;
  2377. if (!mutex_trylock(&tp->control)) {
  2378. schedule_delayed_work(&tp->schedule, 0);
  2379. goto out1;
  2380. }
  2381. if (test_bit(RTL8152_LINK_CHG, &tp->flags))
  2382. set_carrier(tp);
  2383. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2384. _rtl8152_set_rx_mode(tp->netdev);
  2385. /* don't schedule napi before linking */
  2386. if (test_bit(SCHEDULE_NAPI, &tp->flags) &&
  2387. netif_carrier_ok(tp->netdev)) {
  2388. clear_bit(SCHEDULE_NAPI, &tp->flags);
  2389. napi_schedule(&tp->napi);
  2390. }
  2391. if (test_bit(PHY_RESET, &tp->flags))
  2392. rtl_phy_reset(tp);
  2393. mutex_unlock(&tp->control);
  2394. out1:
  2395. usb_autopm_put_interface(tp->intf);
  2396. }
  2397. static int rtl8152_open(struct net_device *netdev)
  2398. {
  2399. struct r8152 *tp = netdev_priv(netdev);
  2400. int res = 0;
  2401. res = alloc_all_mem(tp);
  2402. if (res)
  2403. goto out;
  2404. netif_carrier_off(netdev);
  2405. res = usb_autopm_get_interface(tp->intf);
  2406. if (res < 0) {
  2407. free_all_mem(tp);
  2408. goto out;
  2409. }
  2410. mutex_lock(&tp->control);
  2411. /* The WORK_ENABLE may be set when autoresume occurs */
  2412. if (test_bit(WORK_ENABLE, &tp->flags)) {
  2413. clear_bit(WORK_ENABLE, &tp->flags);
  2414. usb_kill_urb(tp->intr_urb);
  2415. cancel_delayed_work_sync(&tp->schedule);
  2416. /* disable the tx/rx, if the workqueue has enabled them. */
  2417. if (netif_carrier_ok(netdev))
  2418. tp->rtl_ops.disable(tp);
  2419. }
  2420. tp->rtl_ops.up(tp);
  2421. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2422. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2423. DUPLEX_FULL);
  2424. netif_carrier_off(netdev);
  2425. netif_start_queue(netdev);
  2426. set_bit(WORK_ENABLE, &tp->flags);
  2427. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2428. if (res) {
  2429. if (res == -ENODEV)
  2430. netif_device_detach(tp->netdev);
  2431. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2432. res);
  2433. free_all_mem(tp);
  2434. } else {
  2435. napi_enable(&tp->napi);
  2436. }
  2437. mutex_unlock(&tp->control);
  2438. usb_autopm_put_interface(tp->intf);
  2439. out:
  2440. return res;
  2441. }
  2442. static int rtl8152_close(struct net_device *netdev)
  2443. {
  2444. struct r8152 *tp = netdev_priv(netdev);
  2445. int res = 0;
  2446. napi_disable(&tp->napi);
  2447. clear_bit(WORK_ENABLE, &tp->flags);
  2448. usb_kill_urb(tp->intr_urb);
  2449. cancel_delayed_work_sync(&tp->schedule);
  2450. netif_stop_queue(netdev);
  2451. res = usb_autopm_get_interface(tp->intf);
  2452. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2453. rtl_drop_queued_tx(tp);
  2454. rtl_stop_rx(tp);
  2455. } else {
  2456. mutex_lock(&tp->control);
  2457. /* The autosuspend may have been enabled and wouldn't
  2458. * be disable when autoresume occurs, because the
  2459. * netif_running() would be false.
  2460. */
  2461. rtl_runtime_suspend_enable(tp, false);
  2462. tp->rtl_ops.down(tp);
  2463. mutex_unlock(&tp->control);
  2464. usb_autopm_put_interface(tp->intf);
  2465. }
  2466. free_all_mem(tp);
  2467. return res;
  2468. }
  2469. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2470. {
  2471. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2472. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2473. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2474. }
  2475. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2476. {
  2477. u16 data;
  2478. r8152_mmd_indirect(tp, dev, reg);
  2479. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2480. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2481. return data;
  2482. }
  2483. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2484. {
  2485. r8152_mmd_indirect(tp, dev, reg);
  2486. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2487. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2488. }
  2489. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2490. {
  2491. u16 config1, config2, config3;
  2492. u32 ocp_data;
  2493. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2494. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2495. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2496. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2497. if (enable) {
  2498. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2499. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2500. config1 |= sd_rise_time(1);
  2501. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2502. config3 |= fast_snr(42);
  2503. } else {
  2504. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2505. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2506. RX_QUIET_EN);
  2507. config1 |= sd_rise_time(7);
  2508. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2509. config3 |= fast_snr(511);
  2510. }
  2511. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2512. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2513. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2514. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2515. }
  2516. static void r8152b_enable_eee(struct r8152 *tp)
  2517. {
  2518. r8152_eee_en(tp, true);
  2519. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2520. }
  2521. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2522. {
  2523. u32 ocp_data;
  2524. u16 config;
  2525. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2526. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2527. if (enable) {
  2528. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2529. config |= EEE10_EN;
  2530. } else {
  2531. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2532. config &= ~EEE10_EN;
  2533. }
  2534. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2535. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2536. }
  2537. static void r8153_enable_eee(struct r8152 *tp)
  2538. {
  2539. r8153_eee_en(tp, true);
  2540. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2541. }
  2542. static void r8152b_enable_fc(struct r8152 *tp)
  2543. {
  2544. u16 anar;
  2545. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2546. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2547. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2548. }
  2549. static void rtl_tally_reset(struct r8152 *tp)
  2550. {
  2551. u32 ocp_data;
  2552. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2553. ocp_data |= TALLY_RESET;
  2554. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2555. }
  2556. static void r8152b_init(struct r8152 *tp)
  2557. {
  2558. u32 ocp_data;
  2559. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2560. return;
  2561. r8152b_disable_aldps(tp);
  2562. if (tp->version == RTL_VER_01) {
  2563. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2564. ocp_data &= ~LED_MODE_MASK;
  2565. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2566. }
  2567. r8152_power_cut_en(tp, false);
  2568. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2569. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2570. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2571. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2572. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2573. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2574. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2575. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2576. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2577. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2578. r8152b_enable_eee(tp);
  2579. r8152b_enable_aldps(tp);
  2580. r8152b_enable_fc(tp);
  2581. rtl_tally_reset(tp);
  2582. /* enable rx aggregation */
  2583. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2584. ocp_data &= ~RX_AGG_DISABLE;
  2585. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2586. }
  2587. static void r8153_init(struct r8152 *tp)
  2588. {
  2589. u32 ocp_data;
  2590. int i;
  2591. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2592. return;
  2593. r8153_disable_aldps(tp);
  2594. r8153_u1u2en(tp, false);
  2595. for (i = 0; i < 500; i++) {
  2596. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2597. AUTOLOAD_DONE)
  2598. break;
  2599. msleep(20);
  2600. }
  2601. for (i = 0; i < 500; i++) {
  2602. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2603. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2604. break;
  2605. msleep(20);
  2606. }
  2607. r8153_u2p3en(tp, false);
  2608. if (tp->version == RTL_VER_04) {
  2609. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2610. ocp_data &= ~pwd_dn_scale_mask;
  2611. ocp_data |= pwd_dn_scale(96);
  2612. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2613. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2614. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2615. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2616. } else if (tp->version == RTL_VER_05) {
  2617. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2618. ocp_data &= ~ECM_ALDPS;
  2619. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2620. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2621. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2622. ocp_data &= ~DYNAMIC_BURST;
  2623. else
  2624. ocp_data |= DYNAMIC_BURST;
  2625. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2626. }
  2627. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2628. ocp_data |= EP4_FULL_FC;
  2629. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2630. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2631. ocp_data &= ~TIMER11_EN;
  2632. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2633. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2634. ocp_data &= ~LED_MODE_MASK;
  2635. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2636. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2637. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2638. ocp_data |= LPM_TIMER_500MS;
  2639. else
  2640. ocp_data |= LPM_TIMER_500US;
  2641. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2642. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2643. ocp_data &= ~SEN_VAL_MASK;
  2644. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2645. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2646. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2647. r8153_power_cut_en(tp, false);
  2648. r8153_u1u2en(tp, true);
  2649. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2650. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2651. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2652. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2653. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2654. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2655. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2656. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2657. EEE_SPDWN_EN);
  2658. r8153_enable_eee(tp);
  2659. r8153_enable_aldps(tp);
  2660. r8152b_enable_fc(tp);
  2661. rtl_tally_reset(tp);
  2662. }
  2663. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2664. {
  2665. struct r8152 *tp = usb_get_intfdata(intf);
  2666. struct net_device *netdev = tp->netdev;
  2667. int ret = 0;
  2668. mutex_lock(&tp->control);
  2669. if (PMSG_IS_AUTO(message)) {
  2670. if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
  2671. ret = -EBUSY;
  2672. goto out1;
  2673. }
  2674. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2675. } else {
  2676. netif_device_detach(netdev);
  2677. }
  2678. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2679. clear_bit(WORK_ENABLE, &tp->flags);
  2680. usb_kill_urb(tp->intr_urb);
  2681. napi_disable(&tp->napi);
  2682. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2683. rtl_stop_rx(tp);
  2684. rtl_runtime_suspend_enable(tp, true);
  2685. } else {
  2686. cancel_delayed_work_sync(&tp->schedule);
  2687. tp->rtl_ops.down(tp);
  2688. }
  2689. napi_enable(&tp->napi);
  2690. }
  2691. out1:
  2692. mutex_unlock(&tp->control);
  2693. return ret;
  2694. }
  2695. static int rtl8152_resume(struct usb_interface *intf)
  2696. {
  2697. struct r8152 *tp = usb_get_intfdata(intf);
  2698. mutex_lock(&tp->control);
  2699. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2700. tp->rtl_ops.init(tp);
  2701. netif_device_attach(tp->netdev);
  2702. }
  2703. if (netif_running(tp->netdev)) {
  2704. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2705. rtl_runtime_suspend_enable(tp, false);
  2706. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2707. set_bit(WORK_ENABLE, &tp->flags);
  2708. if (netif_carrier_ok(tp->netdev))
  2709. rtl_start_rx(tp);
  2710. } else {
  2711. tp->rtl_ops.up(tp);
  2712. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2713. tp->mii.supports_gmii ?
  2714. SPEED_1000 : SPEED_100,
  2715. DUPLEX_FULL);
  2716. netif_carrier_off(tp->netdev);
  2717. set_bit(WORK_ENABLE, &tp->flags);
  2718. }
  2719. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2720. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2721. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2722. }
  2723. mutex_unlock(&tp->control);
  2724. return 0;
  2725. }
  2726. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2727. {
  2728. struct r8152 *tp = netdev_priv(dev);
  2729. if (usb_autopm_get_interface(tp->intf) < 0)
  2730. return;
  2731. mutex_lock(&tp->control);
  2732. wol->supported = WAKE_ANY;
  2733. wol->wolopts = __rtl_get_wol(tp);
  2734. mutex_unlock(&tp->control);
  2735. usb_autopm_put_interface(tp->intf);
  2736. }
  2737. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2738. {
  2739. struct r8152 *tp = netdev_priv(dev);
  2740. int ret;
  2741. ret = usb_autopm_get_interface(tp->intf);
  2742. if (ret < 0)
  2743. goto out_set_wol;
  2744. mutex_lock(&tp->control);
  2745. __rtl_set_wol(tp, wol->wolopts);
  2746. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2747. mutex_unlock(&tp->control);
  2748. usb_autopm_put_interface(tp->intf);
  2749. out_set_wol:
  2750. return ret;
  2751. }
  2752. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2753. {
  2754. struct r8152 *tp = netdev_priv(dev);
  2755. return tp->msg_enable;
  2756. }
  2757. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2758. {
  2759. struct r8152 *tp = netdev_priv(dev);
  2760. tp->msg_enable = value;
  2761. }
  2762. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2763. struct ethtool_drvinfo *info)
  2764. {
  2765. struct r8152 *tp = netdev_priv(netdev);
  2766. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2767. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2768. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2769. }
  2770. static
  2771. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2772. {
  2773. struct r8152 *tp = netdev_priv(netdev);
  2774. int ret;
  2775. if (!tp->mii.mdio_read)
  2776. return -EOPNOTSUPP;
  2777. ret = usb_autopm_get_interface(tp->intf);
  2778. if (ret < 0)
  2779. goto out;
  2780. mutex_lock(&tp->control);
  2781. ret = mii_ethtool_gset(&tp->mii, cmd);
  2782. mutex_unlock(&tp->control);
  2783. usb_autopm_put_interface(tp->intf);
  2784. out:
  2785. return ret;
  2786. }
  2787. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2788. {
  2789. struct r8152 *tp = netdev_priv(dev);
  2790. int ret;
  2791. ret = usb_autopm_get_interface(tp->intf);
  2792. if (ret < 0)
  2793. goto out;
  2794. mutex_lock(&tp->control);
  2795. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  2796. mutex_unlock(&tp->control);
  2797. usb_autopm_put_interface(tp->intf);
  2798. out:
  2799. return ret;
  2800. }
  2801. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  2802. "tx_packets",
  2803. "rx_packets",
  2804. "tx_errors",
  2805. "rx_errors",
  2806. "rx_missed",
  2807. "align_errors",
  2808. "tx_single_collisions",
  2809. "tx_multi_collisions",
  2810. "rx_unicast",
  2811. "rx_broadcast",
  2812. "rx_multicast",
  2813. "tx_aborted",
  2814. "tx_underrun",
  2815. };
  2816. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  2817. {
  2818. switch (sset) {
  2819. case ETH_SS_STATS:
  2820. return ARRAY_SIZE(rtl8152_gstrings);
  2821. default:
  2822. return -EOPNOTSUPP;
  2823. }
  2824. }
  2825. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  2826. struct ethtool_stats *stats, u64 *data)
  2827. {
  2828. struct r8152 *tp = netdev_priv(dev);
  2829. struct tally_counter tally;
  2830. if (usb_autopm_get_interface(tp->intf) < 0)
  2831. return;
  2832. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  2833. usb_autopm_put_interface(tp->intf);
  2834. data[0] = le64_to_cpu(tally.tx_packets);
  2835. data[1] = le64_to_cpu(tally.rx_packets);
  2836. data[2] = le64_to_cpu(tally.tx_errors);
  2837. data[3] = le32_to_cpu(tally.rx_errors);
  2838. data[4] = le16_to_cpu(tally.rx_missed);
  2839. data[5] = le16_to_cpu(tally.align_errors);
  2840. data[6] = le32_to_cpu(tally.tx_one_collision);
  2841. data[7] = le32_to_cpu(tally.tx_multi_collision);
  2842. data[8] = le64_to_cpu(tally.rx_unicast);
  2843. data[9] = le64_to_cpu(tally.rx_broadcast);
  2844. data[10] = le32_to_cpu(tally.rx_multicast);
  2845. data[11] = le16_to_cpu(tally.tx_aborted);
  2846. data[12] = le16_to_cpu(tally.tx_underrun);
  2847. }
  2848. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  2849. {
  2850. switch (stringset) {
  2851. case ETH_SS_STATS:
  2852. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  2853. break;
  2854. }
  2855. }
  2856. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2857. {
  2858. u32 ocp_data, lp, adv, supported = 0;
  2859. u16 val;
  2860. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  2861. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2862. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  2863. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2864. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  2865. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2866. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2867. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2868. eee->eee_enabled = !!ocp_data;
  2869. eee->eee_active = !!(supported & adv & lp);
  2870. eee->supported = supported;
  2871. eee->advertised = adv;
  2872. eee->lp_advertised = lp;
  2873. return 0;
  2874. }
  2875. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2876. {
  2877. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2878. r8152_eee_en(tp, eee->eee_enabled);
  2879. if (!eee->eee_enabled)
  2880. val = 0;
  2881. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  2882. return 0;
  2883. }
  2884. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2885. {
  2886. u32 ocp_data, lp, adv, supported = 0;
  2887. u16 val;
  2888. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  2889. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  2890. val = ocp_reg_read(tp, OCP_EEE_ADV);
  2891. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  2892. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  2893. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  2894. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2895. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  2896. eee->eee_enabled = !!ocp_data;
  2897. eee->eee_active = !!(supported & adv & lp);
  2898. eee->supported = supported;
  2899. eee->advertised = adv;
  2900. eee->lp_advertised = lp;
  2901. return 0;
  2902. }
  2903. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  2904. {
  2905. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  2906. r8153_eee_en(tp, eee->eee_enabled);
  2907. if (!eee->eee_enabled)
  2908. val = 0;
  2909. ocp_reg_write(tp, OCP_EEE_ADV, val);
  2910. return 0;
  2911. }
  2912. static int
  2913. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  2914. {
  2915. struct r8152 *tp = netdev_priv(net);
  2916. int ret;
  2917. ret = usb_autopm_get_interface(tp->intf);
  2918. if (ret < 0)
  2919. goto out;
  2920. mutex_lock(&tp->control);
  2921. ret = tp->rtl_ops.eee_get(tp, edata);
  2922. mutex_unlock(&tp->control);
  2923. usb_autopm_put_interface(tp->intf);
  2924. out:
  2925. return ret;
  2926. }
  2927. static int
  2928. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  2929. {
  2930. struct r8152 *tp = netdev_priv(net);
  2931. int ret;
  2932. ret = usb_autopm_get_interface(tp->intf);
  2933. if (ret < 0)
  2934. goto out;
  2935. mutex_lock(&tp->control);
  2936. ret = tp->rtl_ops.eee_set(tp, edata);
  2937. if (!ret)
  2938. ret = mii_nway_restart(&tp->mii);
  2939. mutex_unlock(&tp->control);
  2940. usb_autopm_put_interface(tp->intf);
  2941. out:
  2942. return ret;
  2943. }
  2944. static int rtl8152_nway_reset(struct net_device *dev)
  2945. {
  2946. struct r8152 *tp = netdev_priv(dev);
  2947. int ret;
  2948. ret = usb_autopm_get_interface(tp->intf);
  2949. if (ret < 0)
  2950. goto out;
  2951. mutex_lock(&tp->control);
  2952. ret = mii_nway_restart(&tp->mii);
  2953. mutex_unlock(&tp->control);
  2954. usb_autopm_put_interface(tp->intf);
  2955. out:
  2956. return ret;
  2957. }
  2958. static int rtl8152_get_coalesce(struct net_device *netdev,
  2959. struct ethtool_coalesce *coalesce)
  2960. {
  2961. struct r8152 *tp = netdev_priv(netdev);
  2962. switch (tp->version) {
  2963. case RTL_VER_01:
  2964. case RTL_VER_02:
  2965. return -EOPNOTSUPP;
  2966. default:
  2967. break;
  2968. }
  2969. coalesce->rx_coalesce_usecs = tp->coalesce;
  2970. return 0;
  2971. }
  2972. static int rtl8152_set_coalesce(struct net_device *netdev,
  2973. struct ethtool_coalesce *coalesce)
  2974. {
  2975. struct r8152 *tp = netdev_priv(netdev);
  2976. int ret;
  2977. switch (tp->version) {
  2978. case RTL_VER_01:
  2979. case RTL_VER_02:
  2980. return -EOPNOTSUPP;
  2981. default:
  2982. break;
  2983. }
  2984. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  2985. return -EINVAL;
  2986. ret = usb_autopm_get_interface(tp->intf);
  2987. if (ret < 0)
  2988. return ret;
  2989. mutex_lock(&tp->control);
  2990. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  2991. tp->coalesce = coalesce->rx_coalesce_usecs;
  2992. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  2993. r8153_set_rx_early_timeout(tp);
  2994. }
  2995. mutex_unlock(&tp->control);
  2996. usb_autopm_put_interface(tp->intf);
  2997. return ret;
  2998. }
  2999. static struct ethtool_ops ops = {
  3000. .get_drvinfo = rtl8152_get_drvinfo,
  3001. .get_settings = rtl8152_get_settings,
  3002. .set_settings = rtl8152_set_settings,
  3003. .get_link = ethtool_op_get_link,
  3004. .nway_reset = rtl8152_nway_reset,
  3005. .get_msglevel = rtl8152_get_msglevel,
  3006. .set_msglevel = rtl8152_set_msglevel,
  3007. .get_wol = rtl8152_get_wol,
  3008. .set_wol = rtl8152_set_wol,
  3009. .get_strings = rtl8152_get_strings,
  3010. .get_sset_count = rtl8152_get_sset_count,
  3011. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3012. .get_coalesce = rtl8152_get_coalesce,
  3013. .set_coalesce = rtl8152_set_coalesce,
  3014. .get_eee = rtl_ethtool_get_eee,
  3015. .set_eee = rtl_ethtool_set_eee,
  3016. };
  3017. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3018. {
  3019. struct r8152 *tp = netdev_priv(netdev);
  3020. struct mii_ioctl_data *data = if_mii(rq);
  3021. int res;
  3022. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3023. return -ENODEV;
  3024. res = usb_autopm_get_interface(tp->intf);
  3025. if (res < 0)
  3026. goto out;
  3027. switch (cmd) {
  3028. case SIOCGMIIPHY:
  3029. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3030. break;
  3031. case SIOCGMIIREG:
  3032. mutex_lock(&tp->control);
  3033. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3034. mutex_unlock(&tp->control);
  3035. break;
  3036. case SIOCSMIIREG:
  3037. if (!capable(CAP_NET_ADMIN)) {
  3038. res = -EPERM;
  3039. break;
  3040. }
  3041. mutex_lock(&tp->control);
  3042. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3043. mutex_unlock(&tp->control);
  3044. break;
  3045. default:
  3046. res = -EOPNOTSUPP;
  3047. }
  3048. usb_autopm_put_interface(tp->intf);
  3049. out:
  3050. return res;
  3051. }
  3052. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3053. {
  3054. struct r8152 *tp = netdev_priv(dev);
  3055. int ret;
  3056. switch (tp->version) {
  3057. case RTL_VER_01:
  3058. case RTL_VER_02:
  3059. return eth_change_mtu(dev, new_mtu);
  3060. default:
  3061. break;
  3062. }
  3063. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3064. return -EINVAL;
  3065. ret = usb_autopm_get_interface(tp->intf);
  3066. if (ret < 0)
  3067. return ret;
  3068. mutex_lock(&tp->control);
  3069. dev->mtu = new_mtu;
  3070. if (netif_running(dev) && netif_carrier_ok(dev))
  3071. r8153_set_rx_early_size(tp);
  3072. mutex_unlock(&tp->control);
  3073. usb_autopm_put_interface(tp->intf);
  3074. return ret;
  3075. }
  3076. static const struct net_device_ops rtl8152_netdev_ops = {
  3077. .ndo_open = rtl8152_open,
  3078. .ndo_stop = rtl8152_close,
  3079. .ndo_do_ioctl = rtl8152_ioctl,
  3080. .ndo_start_xmit = rtl8152_start_xmit,
  3081. .ndo_tx_timeout = rtl8152_tx_timeout,
  3082. .ndo_set_features = rtl8152_set_features,
  3083. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3084. .ndo_set_mac_address = rtl8152_set_mac_address,
  3085. .ndo_change_mtu = rtl8152_change_mtu,
  3086. .ndo_validate_addr = eth_validate_addr,
  3087. .ndo_features_check = rtl8152_features_check,
  3088. };
  3089. static void r8152b_get_version(struct r8152 *tp)
  3090. {
  3091. u32 ocp_data;
  3092. u16 version;
  3093. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3094. version = (u16)(ocp_data & VERSION_MASK);
  3095. switch (version) {
  3096. case 0x4c00:
  3097. tp->version = RTL_VER_01;
  3098. break;
  3099. case 0x4c10:
  3100. tp->version = RTL_VER_02;
  3101. break;
  3102. case 0x5c00:
  3103. tp->version = RTL_VER_03;
  3104. tp->mii.supports_gmii = 1;
  3105. break;
  3106. case 0x5c10:
  3107. tp->version = RTL_VER_04;
  3108. tp->mii.supports_gmii = 1;
  3109. break;
  3110. case 0x5c20:
  3111. tp->version = RTL_VER_05;
  3112. tp->mii.supports_gmii = 1;
  3113. break;
  3114. default:
  3115. netif_info(tp, probe, tp->netdev,
  3116. "Unknown version 0x%04x\n", version);
  3117. break;
  3118. }
  3119. }
  3120. static void rtl8152_unload(struct r8152 *tp)
  3121. {
  3122. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3123. return;
  3124. if (tp->version != RTL_VER_01)
  3125. r8152_power_cut_en(tp, true);
  3126. }
  3127. static void rtl8153_unload(struct r8152 *tp)
  3128. {
  3129. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3130. return;
  3131. r8153_power_cut_en(tp, false);
  3132. }
  3133. static int rtl_ops_init(struct r8152 *tp)
  3134. {
  3135. struct rtl_ops *ops = &tp->rtl_ops;
  3136. int ret = 0;
  3137. switch (tp->version) {
  3138. case RTL_VER_01:
  3139. case RTL_VER_02:
  3140. ops->init = r8152b_init;
  3141. ops->enable = rtl8152_enable;
  3142. ops->disable = rtl8152_disable;
  3143. ops->up = rtl8152_up;
  3144. ops->down = rtl8152_down;
  3145. ops->unload = rtl8152_unload;
  3146. ops->eee_get = r8152_get_eee;
  3147. ops->eee_set = r8152_set_eee;
  3148. break;
  3149. case RTL_VER_03:
  3150. case RTL_VER_04:
  3151. case RTL_VER_05:
  3152. ops->init = r8153_init;
  3153. ops->enable = rtl8153_enable;
  3154. ops->disable = rtl8153_disable;
  3155. ops->up = rtl8153_up;
  3156. ops->down = rtl8153_down;
  3157. ops->unload = rtl8153_unload;
  3158. ops->eee_get = r8153_get_eee;
  3159. ops->eee_set = r8153_set_eee;
  3160. break;
  3161. default:
  3162. ret = -ENODEV;
  3163. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3164. break;
  3165. }
  3166. return ret;
  3167. }
  3168. static int rtl8152_probe(struct usb_interface *intf,
  3169. const struct usb_device_id *id)
  3170. {
  3171. struct usb_device *udev = interface_to_usbdev(intf);
  3172. struct r8152 *tp;
  3173. struct net_device *netdev;
  3174. int ret;
  3175. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3176. usb_driver_set_configuration(udev, 1);
  3177. return -ENODEV;
  3178. }
  3179. usb_reset_device(udev);
  3180. netdev = alloc_etherdev(sizeof(struct r8152));
  3181. if (!netdev) {
  3182. dev_err(&intf->dev, "Out of memory\n");
  3183. return -ENOMEM;
  3184. }
  3185. SET_NETDEV_DEV(netdev, &intf->dev);
  3186. tp = netdev_priv(netdev);
  3187. tp->msg_enable = 0x7FFF;
  3188. tp->udev = udev;
  3189. tp->netdev = netdev;
  3190. tp->intf = intf;
  3191. r8152b_get_version(tp);
  3192. ret = rtl_ops_init(tp);
  3193. if (ret)
  3194. goto out;
  3195. mutex_init(&tp->control);
  3196. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3197. netdev->netdev_ops = &rtl8152_netdev_ops;
  3198. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3199. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3200. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3201. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3202. NETIF_F_HW_VLAN_CTAG_TX;
  3203. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3204. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3205. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3206. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3207. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3208. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3209. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3210. netdev->ethtool_ops = &ops;
  3211. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3212. tp->mii.dev = netdev;
  3213. tp->mii.mdio_read = read_mii_word;
  3214. tp->mii.mdio_write = write_mii_word;
  3215. tp->mii.phy_id_mask = 0x3f;
  3216. tp->mii.reg_num_mask = 0x1f;
  3217. tp->mii.phy_id = R8152_PHY_ID;
  3218. switch (udev->speed) {
  3219. case USB_SPEED_SUPER:
  3220. tp->coalesce = COALESCE_SUPER;
  3221. break;
  3222. case USB_SPEED_HIGH:
  3223. tp->coalesce = COALESCE_HIGH;
  3224. break;
  3225. default:
  3226. tp->coalesce = COALESCE_SLOW;
  3227. break;
  3228. }
  3229. intf->needs_remote_wakeup = 1;
  3230. tp->rtl_ops.init(tp);
  3231. set_ethernet_addr(tp);
  3232. usb_set_intfdata(intf, tp);
  3233. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3234. ret = register_netdev(netdev);
  3235. if (ret != 0) {
  3236. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3237. goto out1;
  3238. }
  3239. tp->saved_wolopts = __rtl_get_wol(tp);
  3240. if (tp->saved_wolopts)
  3241. device_set_wakeup_enable(&udev->dev, true);
  3242. else
  3243. device_set_wakeup_enable(&udev->dev, false);
  3244. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3245. return 0;
  3246. out1:
  3247. netif_napi_del(&tp->napi);
  3248. usb_set_intfdata(intf, NULL);
  3249. out:
  3250. free_netdev(netdev);
  3251. return ret;
  3252. }
  3253. static void rtl8152_disconnect(struct usb_interface *intf)
  3254. {
  3255. struct r8152 *tp = usb_get_intfdata(intf);
  3256. usb_set_intfdata(intf, NULL);
  3257. if (tp) {
  3258. struct usb_device *udev = tp->udev;
  3259. if (udev->state == USB_STATE_NOTATTACHED)
  3260. set_bit(RTL8152_UNPLUG, &tp->flags);
  3261. netif_napi_del(&tp->napi);
  3262. unregister_netdev(tp->netdev);
  3263. tp->rtl_ops.unload(tp);
  3264. free_netdev(tp->netdev);
  3265. }
  3266. }
  3267. #define REALTEK_USB_DEVICE(vend, prod) \
  3268. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3269. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3270. .idVendor = (vend), \
  3271. .idProduct = (prod), \
  3272. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3273. }, \
  3274. { \
  3275. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3276. USB_DEVICE_ID_MATCH_DEVICE, \
  3277. .idVendor = (vend), \
  3278. .idProduct = (prod), \
  3279. .bInterfaceClass = USB_CLASS_COMM, \
  3280. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3281. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3282. /* table of devices that work with this driver */
  3283. static struct usb_device_id rtl8152_table[] = {
  3284. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3285. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3286. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3287. {}
  3288. };
  3289. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3290. static struct usb_driver rtl8152_driver = {
  3291. .name = MODULENAME,
  3292. .id_table = rtl8152_table,
  3293. .probe = rtl8152_probe,
  3294. .disconnect = rtl8152_disconnect,
  3295. .suspend = rtl8152_suspend,
  3296. .resume = rtl8152_resume,
  3297. .reset_resume = rtl8152_resume,
  3298. .supports_autosuspend = 1,
  3299. .disable_hub_initiated_lpm = 1,
  3300. };
  3301. module_usb_driver(rtl8152_driver);
  3302. MODULE_AUTHOR(DRIVER_AUTHOR);
  3303. MODULE_DESCRIPTION(DRIVER_DESC);
  3304. MODULE_LICENSE("GPL");