mv88e6352.c 17 KB

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  1. /*
  2. * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
  3. *
  4. * Copyright (c) 2014 Guenter Roeck
  5. *
  6. * Derived from mv88e6123_61_65.c
  7. * Copyright (c) 2008-2009 Marvell Semiconductor
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/jiffies.h>
  16. #include <linux/list.h>
  17. #include <linux/module.h>
  18. #include <linux/netdevice.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/phy.h>
  21. #include <net/dsa.h>
  22. #include "mv88e6xxx.h"
  23. static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
  24. {
  25. struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
  26. int ret;
  27. if (bus == NULL)
  28. return NULL;
  29. ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
  30. if (ret >= 0) {
  31. if ((ret & 0xfff0) == 0x1760)
  32. return "Marvell 88E6176";
  33. if (ret == 0x3521)
  34. return "Marvell 88E6352 (A0)";
  35. if (ret == 0x3522)
  36. return "Marvell 88E6352 (A1)";
  37. if ((ret & 0xfff0) == 0x3520)
  38. return "Marvell 88E6352";
  39. }
  40. return NULL;
  41. }
  42. static int mv88e6352_switch_reset(struct dsa_switch *ds)
  43. {
  44. unsigned long timeout;
  45. int ret;
  46. int i;
  47. /* Set all ports to the disabled state. */
  48. for (i = 0; i < 7; i++) {
  49. ret = REG_READ(REG_PORT(i), 0x04);
  50. REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
  51. }
  52. /* Wait for transmit queues to drain. */
  53. usleep_range(2000, 4000);
  54. /* Reset the switch. Keep PPU active (bit 14, undocumented).
  55. * The PPU needs to be active to support indirect phy register
  56. * accesses through global registers 0x18 and 0x19.
  57. */
  58. REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
  59. /* Wait up to one second for reset to complete. */
  60. timeout = jiffies + 1 * HZ;
  61. while (time_before(jiffies, timeout)) {
  62. ret = REG_READ(REG_GLOBAL, 0x00);
  63. if ((ret & 0x8800) == 0x8800)
  64. break;
  65. usleep_range(1000, 2000);
  66. }
  67. if (time_after(jiffies, timeout))
  68. return -ETIMEDOUT;
  69. return 0;
  70. }
  71. static int mv88e6352_setup_global(struct dsa_switch *ds)
  72. {
  73. int ret;
  74. int i;
  75. /* Discard packets with excessive collisions,
  76. * mask all interrupt sources, enable PPU (bit 14, undocumented).
  77. */
  78. REG_WRITE(REG_GLOBAL, 0x04, 0x6000);
  79. /* Set the default address aging time to 5 minutes, and
  80. * enable address learn messages to be sent to all message
  81. * ports.
  82. */
  83. REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
  84. /* Configure the priority mapping registers. */
  85. ret = mv88e6xxx_config_prio(ds);
  86. if (ret < 0)
  87. return ret;
  88. /* Configure the upstream port, and configure the upstream
  89. * port as the port to which ingress and egress monitor frames
  90. * are to be sent.
  91. */
  92. REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
  93. /* Disable remote management for now, and set the switch's
  94. * DSA device number.
  95. */
  96. REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
  97. /* Send all frames with destination addresses matching
  98. * 01:80:c2:00:00:2x to the CPU port.
  99. */
  100. REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
  101. /* Send all frames with destination addresses matching
  102. * 01:80:c2:00:00:0x to the CPU port.
  103. */
  104. REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
  105. /* Disable the loopback filter, disable flow control
  106. * messages, disable flood broadcast override, disable
  107. * removing of provider tags, disable ATU age violation
  108. * interrupts, disable tag flow control, force flow
  109. * control priority to the highest, and send all special
  110. * multicast frames to the CPU at the highest priority.
  111. */
  112. REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
  113. /* Program the DSA routing table. */
  114. for (i = 0; i < 32; i++) {
  115. int nexthop = 0x1f;
  116. if (i != ds->index && i < ds->dst->pd->nr_chips)
  117. nexthop = ds->pd->rtable[i] & 0x1f;
  118. REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
  119. }
  120. /* Clear all trunk masks. */
  121. for (i = 0; i < 8; i++)
  122. REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f);
  123. /* Clear all trunk mappings. */
  124. for (i = 0; i < 16; i++)
  125. REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
  126. /* Disable ingress rate limiting by resetting all ingress
  127. * rate limit registers to their initial state.
  128. */
  129. for (i = 0; i < 7; i++)
  130. REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
  131. /* Initialise cross-chip port VLAN table to reset defaults. */
  132. REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
  133. /* Clear the priority override table. */
  134. for (i = 0; i < 16; i++)
  135. REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
  136. /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
  137. return 0;
  138. }
  139. static int mv88e6352_setup_port(struct dsa_switch *ds, int p)
  140. {
  141. int addr = REG_PORT(p);
  142. u16 val;
  143. /* MAC Forcing register: don't force link, speed, duplex
  144. * or flow control state to any particular values on physical
  145. * ports, but force the CPU port and all DSA ports to 1000 Mb/s
  146. * full duplex.
  147. */
  148. if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
  149. REG_WRITE(addr, 0x01, 0x003e);
  150. else
  151. REG_WRITE(addr, 0x01, 0x0003);
  152. /* Do not limit the period of time that this port can be
  153. * paused for by the remote end or the period of time that
  154. * this port can pause the remote end.
  155. */
  156. REG_WRITE(addr, 0x02, 0x0000);
  157. /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
  158. * disable Header mode, enable IGMP/MLD snooping, disable VLAN
  159. * tunneling, determine priority by looking at 802.1p and IP
  160. * priority fields (IP prio has precedence), and set STP state
  161. * to Forwarding.
  162. *
  163. * If this is the CPU link, use DSA or EDSA tagging depending
  164. * on which tagging mode was configured.
  165. *
  166. * If this is a link to another switch, use DSA tagging mode.
  167. *
  168. * If this is the upstream port for this switch, enable
  169. * forwarding of unknown unicasts and multicasts.
  170. */
  171. val = 0x0433;
  172. if (dsa_is_cpu_port(ds, p)) {
  173. if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
  174. val |= 0x3300;
  175. else
  176. val |= 0x0100;
  177. }
  178. if (ds->dsa_port_mask & (1 << p))
  179. val |= 0x0100;
  180. if (p == dsa_upstream_port(ds))
  181. val |= 0x000c;
  182. REG_WRITE(addr, 0x04, val);
  183. /* Port Control 1: disable trunking. Also, if this is the
  184. * CPU port, enable learn messages to be sent to this port.
  185. */
  186. REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
  187. /* Port based VLAN map: give each port its own address
  188. * database, allow the CPU port to talk to each of the 'real'
  189. * ports, and allow each of the 'real' ports to only talk to
  190. * the upstream port.
  191. */
  192. val = (p & 0xf) << 12;
  193. if (dsa_is_cpu_port(ds, p))
  194. val |= ds->phys_port_mask;
  195. else
  196. val |= 1 << dsa_upstream_port(ds);
  197. REG_WRITE(addr, 0x06, val);
  198. /* Default VLAN ID and priority: don't set a default VLAN
  199. * ID, and set the default packet priority to zero.
  200. */
  201. REG_WRITE(addr, 0x07, 0x0000);
  202. /* Port Control 2: don't force a good FCS, set the maximum
  203. * frame size to 10240 bytes, don't let the switch add or
  204. * strip 802.1q tags, don't discard tagged or untagged frames
  205. * on this port, do a destination address lookup on all
  206. * received packets as usual, disable ARP mirroring and don't
  207. * send a copy of all transmitted/received frames on this port
  208. * to the CPU.
  209. */
  210. REG_WRITE(addr, 0x08, 0x2080);
  211. /* Egress rate control: disable egress rate control. */
  212. REG_WRITE(addr, 0x09, 0x0001);
  213. /* Egress rate control 2: disable egress rate control. */
  214. REG_WRITE(addr, 0x0a, 0x0000);
  215. /* Port Association Vector: when learning source addresses
  216. * of packets, add the address to the address database using
  217. * a port bitmap that has only the bit for this port set and
  218. * the other bits clear.
  219. */
  220. REG_WRITE(addr, 0x0b, 1 << p);
  221. /* Port ATU control: disable limiting the number of address
  222. * database entries that this port is allowed to use.
  223. */
  224. REG_WRITE(addr, 0x0c, 0x0000);
  225. /* Priority Override: disable DA, SA and VTU priority override. */
  226. REG_WRITE(addr, 0x0d, 0x0000);
  227. /* Port Ethertype: use the Ethertype DSA Ethertype value. */
  228. REG_WRITE(addr, 0x0f, ETH_P_EDSA);
  229. /* Tag Remap: use an identity 802.1p prio -> switch prio
  230. * mapping.
  231. */
  232. REG_WRITE(addr, 0x18, 0x3210);
  233. /* Tag Remap 2: use an identity 802.1p prio -> switch prio
  234. * mapping.
  235. */
  236. REG_WRITE(addr, 0x19, 0x7654);
  237. return 0;
  238. }
  239. #ifdef CONFIG_NET_DSA_HWMON
  240. static int mv88e6352_phy_page_read(struct dsa_switch *ds,
  241. int port, int page, int reg)
  242. {
  243. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  244. int ret;
  245. mutex_lock(&ps->phy_mutex);
  246. ret = mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
  247. if (ret < 0)
  248. goto error;
  249. ret = mv88e6xxx_phy_read_indirect(ds, port, reg);
  250. error:
  251. mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
  252. mutex_unlock(&ps->phy_mutex);
  253. return ret;
  254. }
  255. static int mv88e6352_phy_page_write(struct dsa_switch *ds,
  256. int port, int page, int reg, int val)
  257. {
  258. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  259. int ret;
  260. mutex_lock(&ps->phy_mutex);
  261. ret = mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
  262. if (ret < 0)
  263. goto error;
  264. ret = mv88e6xxx_phy_write_indirect(ds, port, reg, val);
  265. error:
  266. mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
  267. mutex_unlock(&ps->phy_mutex);
  268. return ret;
  269. }
  270. static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp)
  271. {
  272. int ret;
  273. *temp = 0;
  274. ret = mv88e6352_phy_page_read(ds, 0, 6, 27);
  275. if (ret < 0)
  276. return ret;
  277. *temp = (ret & 0xff) - 25;
  278. return 0;
  279. }
  280. static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp)
  281. {
  282. int ret;
  283. *temp = 0;
  284. ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
  285. if (ret < 0)
  286. return ret;
  287. *temp = (((ret >> 8) & 0x1f) * 5) - 25;
  288. return 0;
  289. }
  290. static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp)
  291. {
  292. int ret;
  293. ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
  294. if (ret < 0)
  295. return ret;
  296. temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
  297. return mv88e6352_phy_page_write(ds, 0, 6, 26,
  298. (ret & 0xe0ff) | (temp << 8));
  299. }
  300. static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
  301. {
  302. int ret;
  303. *alarm = false;
  304. ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
  305. if (ret < 0)
  306. return ret;
  307. *alarm = !!(ret & 0x40);
  308. return 0;
  309. }
  310. #endif /* CONFIG_NET_DSA_HWMON */
  311. static int mv88e6352_setup(struct dsa_switch *ds)
  312. {
  313. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  314. int ret;
  315. int i;
  316. mutex_init(&ps->smi_mutex);
  317. mutex_init(&ps->stats_mutex);
  318. mutex_init(&ps->phy_mutex);
  319. mutex_init(&ps->eeprom_mutex);
  320. ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
  321. ret = mv88e6352_switch_reset(ds);
  322. if (ret < 0)
  323. return ret;
  324. /* @@@ initialise vtu and atu */
  325. ret = mv88e6352_setup_global(ds);
  326. if (ret < 0)
  327. return ret;
  328. for (i = 0; i < 7; i++) {
  329. ret = mv88e6352_setup_port(ds, i);
  330. if (ret < 0)
  331. return ret;
  332. }
  333. return 0;
  334. }
  335. static int mv88e6352_port_to_phy_addr(int port)
  336. {
  337. if (port >= 0 && port <= 4)
  338. return port;
  339. return -EINVAL;
  340. }
  341. static int
  342. mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum)
  343. {
  344. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  345. int addr = mv88e6352_port_to_phy_addr(port);
  346. int ret;
  347. if (addr < 0)
  348. return addr;
  349. mutex_lock(&ps->phy_mutex);
  350. ret = mv88e6xxx_phy_read_indirect(ds, addr, regnum);
  351. mutex_unlock(&ps->phy_mutex);
  352. return ret;
  353. }
  354. static int
  355. mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
  356. {
  357. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  358. int addr = mv88e6352_port_to_phy_addr(port);
  359. int ret;
  360. if (addr < 0)
  361. return addr;
  362. mutex_lock(&ps->phy_mutex);
  363. ret = mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
  364. mutex_unlock(&ps->phy_mutex);
  365. return ret;
  366. }
  367. static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = {
  368. { "in_good_octets", 8, 0x00, },
  369. { "in_bad_octets", 4, 0x02, },
  370. { "in_unicast", 4, 0x04, },
  371. { "in_broadcasts", 4, 0x06, },
  372. { "in_multicasts", 4, 0x07, },
  373. { "in_pause", 4, 0x16, },
  374. { "in_undersize", 4, 0x18, },
  375. { "in_fragments", 4, 0x19, },
  376. { "in_oversize", 4, 0x1a, },
  377. { "in_jabber", 4, 0x1b, },
  378. { "in_rx_error", 4, 0x1c, },
  379. { "in_fcs_error", 4, 0x1d, },
  380. { "out_octets", 8, 0x0e, },
  381. { "out_unicast", 4, 0x10, },
  382. { "out_broadcasts", 4, 0x13, },
  383. { "out_multicasts", 4, 0x12, },
  384. { "out_pause", 4, 0x15, },
  385. { "excessive", 4, 0x11, },
  386. { "collisions", 4, 0x1e, },
  387. { "deferred", 4, 0x05, },
  388. { "single", 4, 0x14, },
  389. { "multiple", 4, 0x17, },
  390. { "out_fcs_error", 4, 0x03, },
  391. { "late", 4, 0x1f, },
  392. { "hist_64bytes", 4, 0x08, },
  393. { "hist_65_127bytes", 4, 0x09, },
  394. { "hist_128_255bytes", 4, 0x0a, },
  395. { "hist_256_511bytes", 4, 0x0b, },
  396. { "hist_512_1023bytes", 4, 0x0c, },
  397. { "hist_1024_max_bytes", 4, 0x0d, },
  398. { "sw_in_discards", 4, 0x110, },
  399. { "sw_in_filtered", 2, 0x112, },
  400. { "sw_out_filtered", 2, 0x113, },
  401. };
  402. static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
  403. {
  404. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  405. int ret;
  406. mutex_lock(&ps->eeprom_mutex);
  407. ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
  408. 0xc000 | (addr & 0xff));
  409. if (ret < 0)
  410. goto error;
  411. ret = mv88e6xxx_eeprom_busy_wait(ds);
  412. if (ret < 0)
  413. goto error;
  414. ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15);
  415. error:
  416. mutex_unlock(&ps->eeprom_mutex);
  417. return ret;
  418. }
  419. static int mv88e6352_get_eeprom(struct dsa_switch *ds,
  420. struct ethtool_eeprom *eeprom, u8 *data)
  421. {
  422. int offset;
  423. int len;
  424. int ret;
  425. offset = eeprom->offset;
  426. len = eeprom->len;
  427. eeprom->len = 0;
  428. eeprom->magic = 0xc3ec4951;
  429. ret = mv88e6xxx_eeprom_load_wait(ds);
  430. if (ret < 0)
  431. return ret;
  432. if (offset & 1) {
  433. int word;
  434. word = mv88e6352_read_eeprom_word(ds, offset >> 1);
  435. if (word < 0)
  436. return word;
  437. *data++ = (word >> 8) & 0xff;
  438. offset++;
  439. len--;
  440. eeprom->len++;
  441. }
  442. while (len >= 2) {
  443. int word;
  444. word = mv88e6352_read_eeprom_word(ds, offset >> 1);
  445. if (word < 0)
  446. return word;
  447. *data++ = word & 0xff;
  448. *data++ = (word >> 8) & 0xff;
  449. offset += 2;
  450. len -= 2;
  451. eeprom->len += 2;
  452. }
  453. if (len) {
  454. int word;
  455. word = mv88e6352_read_eeprom_word(ds, offset >> 1);
  456. if (word < 0)
  457. return word;
  458. *data++ = word & 0xff;
  459. offset++;
  460. len--;
  461. eeprom->len++;
  462. }
  463. return 0;
  464. }
  465. static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
  466. {
  467. int ret;
  468. ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14);
  469. if (ret < 0)
  470. return ret;
  471. if (!(ret & 0x0400))
  472. return -EROFS;
  473. return 0;
  474. }
  475. static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
  476. u16 data)
  477. {
  478. struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
  479. int ret;
  480. mutex_lock(&ps->eeprom_mutex);
  481. ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data);
  482. if (ret < 0)
  483. goto error;
  484. ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
  485. 0xb000 | (addr & 0xff));
  486. if (ret < 0)
  487. goto error;
  488. ret = mv88e6xxx_eeprom_busy_wait(ds);
  489. error:
  490. mutex_unlock(&ps->eeprom_mutex);
  491. return ret;
  492. }
  493. static int mv88e6352_set_eeprom(struct dsa_switch *ds,
  494. struct ethtool_eeprom *eeprom, u8 *data)
  495. {
  496. int offset;
  497. int ret;
  498. int len;
  499. if (eeprom->magic != 0xc3ec4951)
  500. return -EINVAL;
  501. ret = mv88e6352_eeprom_is_readonly(ds);
  502. if (ret)
  503. return ret;
  504. offset = eeprom->offset;
  505. len = eeprom->len;
  506. eeprom->len = 0;
  507. ret = mv88e6xxx_eeprom_load_wait(ds);
  508. if (ret < 0)
  509. return ret;
  510. if (offset & 1) {
  511. int word;
  512. word = mv88e6352_read_eeprom_word(ds, offset >> 1);
  513. if (word < 0)
  514. return word;
  515. word = (*data++ << 8) | (word & 0xff);
  516. ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
  517. if (ret < 0)
  518. return ret;
  519. offset++;
  520. len--;
  521. eeprom->len++;
  522. }
  523. while (len >= 2) {
  524. int word;
  525. word = *data++;
  526. word |= *data++ << 8;
  527. ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
  528. if (ret < 0)
  529. return ret;
  530. offset += 2;
  531. len -= 2;
  532. eeprom->len += 2;
  533. }
  534. if (len) {
  535. int word;
  536. word = mv88e6352_read_eeprom_word(ds, offset >> 1);
  537. if (word < 0)
  538. return word;
  539. word = (word & 0xff00) | *data++;
  540. ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
  541. if (ret < 0)
  542. return ret;
  543. offset++;
  544. len--;
  545. eeprom->len++;
  546. }
  547. return 0;
  548. }
  549. static void
  550. mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
  551. {
  552. mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats),
  553. mv88e6352_hw_stats, port, data);
  554. }
  555. static void
  556. mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
  557. {
  558. mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats),
  559. mv88e6352_hw_stats, port, data);
  560. }
  561. static int mv88e6352_get_sset_count(struct dsa_switch *ds)
  562. {
  563. return ARRAY_SIZE(mv88e6352_hw_stats);
  564. }
  565. struct dsa_switch_driver mv88e6352_switch_driver = {
  566. .tag_protocol = DSA_TAG_PROTO_EDSA,
  567. .priv_size = sizeof(struct mv88e6xxx_priv_state),
  568. .probe = mv88e6352_probe,
  569. .setup = mv88e6352_setup,
  570. .set_addr = mv88e6xxx_set_addr_indirect,
  571. .phy_read = mv88e6352_phy_read,
  572. .phy_write = mv88e6352_phy_write,
  573. .poll_link = mv88e6xxx_poll_link,
  574. .get_strings = mv88e6352_get_strings,
  575. .get_ethtool_stats = mv88e6352_get_ethtool_stats,
  576. .get_sset_count = mv88e6352_get_sset_count,
  577. .set_eee = mv88e6xxx_set_eee,
  578. .get_eee = mv88e6xxx_get_eee,
  579. #ifdef CONFIG_NET_DSA_HWMON
  580. .get_temp = mv88e6352_get_temp,
  581. .get_temp_limit = mv88e6352_get_temp_limit,
  582. .set_temp_limit = mv88e6352_set_temp_limit,
  583. .get_temp_alarm = mv88e6352_get_temp_alarm,
  584. #endif
  585. .get_eeprom = mv88e6352_get_eeprom,
  586. .set_eeprom = mv88e6352_set_eeprom,
  587. .get_regs_len = mv88e6xxx_get_regs_len,
  588. .get_regs = mv88e6xxx_get_regs,
  589. };
  590. MODULE_ALIAS("platform:mv88e6352");