jc42.c 15 KB

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  1. /*
  2. * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
  3. *
  4. * Copyright (c) 2010 Ericsson AB.
  5. *
  6. * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
  7. *
  8. * JC42.4 compliant temperature sensors are typically used on memory modules.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/init.h>
  26. #include <linux/slab.h>
  27. #include <linux/jiffies.h>
  28. #include <linux/i2c.h>
  29. #include <linux/hwmon.h>
  30. #include <linux/hwmon-sysfs.h>
  31. #include <linux/err.h>
  32. #include <linux/mutex.h>
  33. /* Addresses to scan */
  34. static const unsigned short normal_i2c[] = {
  35. 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
  36. /* JC42 registers. All registers are 16 bit. */
  37. #define JC42_REG_CAP 0x00
  38. #define JC42_REG_CONFIG 0x01
  39. #define JC42_REG_TEMP_UPPER 0x02
  40. #define JC42_REG_TEMP_LOWER 0x03
  41. #define JC42_REG_TEMP_CRITICAL 0x04
  42. #define JC42_REG_TEMP 0x05
  43. #define JC42_REG_MANID 0x06
  44. #define JC42_REG_DEVICEID 0x07
  45. /* Status bits in temperature register */
  46. #define JC42_ALARM_CRIT_BIT 15
  47. #define JC42_ALARM_MAX_BIT 14
  48. #define JC42_ALARM_MIN_BIT 13
  49. /* Configuration register defines */
  50. #define JC42_CFG_CRIT_ONLY (1 << 2)
  51. #define JC42_CFG_TCRIT_LOCK (1 << 6)
  52. #define JC42_CFG_EVENT_LOCK (1 << 7)
  53. #define JC42_CFG_SHUTDOWN (1 << 8)
  54. #define JC42_CFG_HYST_SHIFT 9
  55. #define JC42_CFG_HYST_MASK (0x03 << 9)
  56. /* Capabilities */
  57. #define JC42_CAP_RANGE (1 << 2)
  58. /* Manufacturer IDs */
  59. #define ADT_MANID 0x11d4 /* Analog Devices */
  60. #define ATMEL_MANID 0x001f /* Atmel */
  61. #define ATMEL_MANID2 0x1114 /* Atmel */
  62. #define MAX_MANID 0x004d /* Maxim */
  63. #define IDT_MANID 0x00b3 /* IDT */
  64. #define MCP_MANID 0x0054 /* Microchip */
  65. #define NXP_MANID 0x1131 /* NXP Semiconductors */
  66. #define ONS_MANID 0x1b09 /* ON Semiconductor */
  67. #define STM_MANID 0x104a /* ST Microelectronics */
  68. /* Supported chips */
  69. /* Analog Devices */
  70. #define ADT7408_DEVID 0x0801
  71. #define ADT7408_DEVID_MASK 0xffff
  72. /* Atmel */
  73. #define AT30TS00_DEVID 0x8201
  74. #define AT30TS00_DEVID_MASK 0xffff
  75. #define AT30TSE004_DEVID 0x2200
  76. #define AT30TSE004_DEVID_MASK 0xffff
  77. /* IDT */
  78. #define TS3000B3_DEVID 0x2903 /* Also matches TSE2002B3 */
  79. #define TS3000B3_DEVID_MASK 0xffff
  80. #define TS3000GB2_DEVID 0x2912 /* Also matches TSE2002GB2 */
  81. #define TS3000GB2_DEVID_MASK 0xffff
  82. /* Maxim */
  83. #define MAX6604_DEVID 0x3e00
  84. #define MAX6604_DEVID_MASK 0xffff
  85. /* Microchip */
  86. #define MCP9804_DEVID 0x0200
  87. #define MCP9804_DEVID_MASK 0xfffc
  88. #define MCP98242_DEVID 0x2000
  89. #define MCP98242_DEVID_MASK 0xfffc
  90. #define MCP98243_DEVID 0x2100
  91. #define MCP98243_DEVID_MASK 0xfffc
  92. #define MCP98244_DEVID 0x2200
  93. #define MCP98244_DEVID_MASK 0xfffc
  94. #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
  95. #define MCP9843_DEVID_MASK 0xfffe
  96. /* NXP */
  97. #define SE97_DEVID 0xa200
  98. #define SE97_DEVID_MASK 0xfffc
  99. #define SE98_DEVID 0xa100
  100. #define SE98_DEVID_MASK 0xfffc
  101. /* ON Semiconductor */
  102. #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
  103. #define CAT6095_DEVID_MASK 0xffe0
  104. /* ST Microelectronics */
  105. #define STTS424_DEVID 0x0101
  106. #define STTS424_DEVID_MASK 0xffff
  107. #define STTS424E_DEVID 0x0000
  108. #define STTS424E_DEVID_MASK 0xfffe
  109. #define STTS2002_DEVID 0x0300
  110. #define STTS2002_DEVID_MASK 0xffff
  111. #define STTS2004_DEVID 0x2201
  112. #define STTS2004_DEVID_MASK 0xffff
  113. #define STTS3000_DEVID 0x0200
  114. #define STTS3000_DEVID_MASK 0xffff
  115. static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
  116. struct jc42_chips {
  117. u16 manid;
  118. u16 devid;
  119. u16 devid_mask;
  120. };
  121. static struct jc42_chips jc42_chips[] = {
  122. { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
  123. { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
  124. { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
  125. { IDT_MANID, TS3000B3_DEVID, TS3000B3_DEVID_MASK },
  126. { IDT_MANID, TS3000GB2_DEVID, TS3000GB2_DEVID_MASK },
  127. { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
  128. { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
  129. { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
  130. { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
  131. { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
  132. { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
  133. { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
  134. { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
  135. { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
  136. { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
  137. { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
  138. { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
  139. { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
  140. { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
  141. };
  142. enum temp_index {
  143. t_input = 0,
  144. t_crit,
  145. t_min,
  146. t_max,
  147. t_num_temp
  148. };
  149. static const u8 temp_regs[t_num_temp] = {
  150. [t_input] = JC42_REG_TEMP,
  151. [t_crit] = JC42_REG_TEMP_CRITICAL,
  152. [t_min] = JC42_REG_TEMP_LOWER,
  153. [t_max] = JC42_REG_TEMP_UPPER,
  154. };
  155. /* Each client has this additional data */
  156. struct jc42_data {
  157. struct i2c_client *client;
  158. struct mutex update_lock; /* protect register access */
  159. bool extended; /* true if extended range supported */
  160. bool valid;
  161. unsigned long last_updated; /* In jiffies */
  162. u16 orig_config; /* original configuration */
  163. u16 config; /* current configuration */
  164. u16 temp[t_num_temp];/* Temperatures */
  165. };
  166. #define JC42_TEMP_MIN_EXTENDED (-40000)
  167. #define JC42_TEMP_MIN 0
  168. #define JC42_TEMP_MAX 125000
  169. static u16 jc42_temp_to_reg(long temp, bool extended)
  170. {
  171. int ntemp = clamp_val(temp,
  172. extended ? JC42_TEMP_MIN_EXTENDED :
  173. JC42_TEMP_MIN, JC42_TEMP_MAX);
  174. /* convert from 0.001 to 0.0625 resolution */
  175. return (ntemp * 2 / 125) & 0x1fff;
  176. }
  177. static int jc42_temp_from_reg(s16 reg)
  178. {
  179. reg = sign_extend32(reg, 12);
  180. /* convert from 0.0625 to 0.001 resolution */
  181. return reg * 125 / 2;
  182. }
  183. static struct jc42_data *jc42_update_device(struct device *dev)
  184. {
  185. struct jc42_data *data = dev_get_drvdata(dev);
  186. struct i2c_client *client = data->client;
  187. struct jc42_data *ret = data;
  188. int i, val;
  189. mutex_lock(&data->update_lock);
  190. if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
  191. for (i = 0; i < t_num_temp; i++) {
  192. val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
  193. if (val < 0) {
  194. ret = ERR_PTR(val);
  195. goto abort;
  196. }
  197. data->temp[i] = val;
  198. }
  199. data->last_updated = jiffies;
  200. data->valid = true;
  201. }
  202. abort:
  203. mutex_unlock(&data->update_lock);
  204. return ret;
  205. }
  206. /* sysfs functions */
  207. static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
  208. char *buf)
  209. {
  210. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  211. struct jc42_data *data = jc42_update_device(dev);
  212. if (IS_ERR(data))
  213. return PTR_ERR(data);
  214. return sprintf(buf, "%d\n",
  215. jc42_temp_from_reg(data->temp[attr->index]));
  216. }
  217. static ssize_t show_temp_hyst(struct device *dev,
  218. struct device_attribute *devattr, char *buf)
  219. {
  220. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  221. struct jc42_data *data = jc42_update_device(dev);
  222. int temp, hyst;
  223. if (IS_ERR(data))
  224. return PTR_ERR(data);
  225. temp = jc42_temp_from_reg(data->temp[attr->index]);
  226. hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
  227. >> JC42_CFG_HYST_SHIFT];
  228. return sprintf(buf, "%d\n", temp - hyst);
  229. }
  230. static ssize_t set_temp(struct device *dev, struct device_attribute *devattr,
  231. const char *buf, size_t count)
  232. {
  233. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  234. struct jc42_data *data = dev_get_drvdata(dev);
  235. int err, ret = count;
  236. int nr = attr->index;
  237. long val;
  238. if (kstrtol(buf, 10, &val) < 0)
  239. return -EINVAL;
  240. mutex_lock(&data->update_lock);
  241. data->temp[nr] = jc42_temp_to_reg(val, data->extended);
  242. err = i2c_smbus_write_word_swapped(data->client, temp_regs[nr],
  243. data->temp[nr]);
  244. if (err < 0)
  245. ret = err;
  246. mutex_unlock(&data->update_lock);
  247. return ret;
  248. }
  249. /*
  250. * JC42.4 compliant chips only support four hysteresis values.
  251. * Pick best choice and go from there.
  252. */
  253. static ssize_t set_temp_crit_hyst(struct device *dev,
  254. struct device_attribute *attr,
  255. const char *buf, size_t count)
  256. {
  257. struct jc42_data *data = dev_get_drvdata(dev);
  258. long val;
  259. int diff, hyst;
  260. int err;
  261. int ret = count;
  262. if (kstrtol(buf, 10, &val) < 0)
  263. return -EINVAL;
  264. val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED :
  265. JC42_TEMP_MIN) - 6000, JC42_TEMP_MAX);
  266. diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
  267. hyst = 0;
  268. if (diff > 0) {
  269. if (diff < 2250)
  270. hyst = 1; /* 1.5 degrees C */
  271. else if (diff < 4500)
  272. hyst = 2; /* 3.0 degrees C */
  273. else
  274. hyst = 3; /* 6.0 degrees C */
  275. }
  276. mutex_lock(&data->update_lock);
  277. data->config = (data->config & ~JC42_CFG_HYST_MASK)
  278. | (hyst << JC42_CFG_HYST_SHIFT);
  279. err = i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
  280. data->config);
  281. if (err < 0)
  282. ret = err;
  283. mutex_unlock(&data->update_lock);
  284. return ret;
  285. }
  286. static ssize_t show_alarm(struct device *dev,
  287. struct device_attribute *attr, char *buf)
  288. {
  289. u16 bit = to_sensor_dev_attr(attr)->index;
  290. struct jc42_data *data = jc42_update_device(dev);
  291. u16 val;
  292. if (IS_ERR(data))
  293. return PTR_ERR(data);
  294. val = data->temp[t_input];
  295. if (bit != JC42_ALARM_CRIT_BIT && (data->config & JC42_CFG_CRIT_ONLY))
  296. val = 0;
  297. return sprintf(buf, "%u\n", (val >> bit) & 1);
  298. }
  299. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, t_input);
  300. static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, set_temp, t_crit);
  301. static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, set_temp, t_min);
  302. static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, set_temp, t_max);
  303. static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_hyst,
  304. set_temp_crit_hyst, t_crit);
  305. static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO, show_temp_hyst, NULL, t_max);
  306. static SENSOR_DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL,
  307. JC42_ALARM_CRIT_BIT);
  308. static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL,
  309. JC42_ALARM_MIN_BIT);
  310. static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL,
  311. JC42_ALARM_MAX_BIT);
  312. static struct attribute *jc42_attributes[] = {
  313. &sensor_dev_attr_temp1_input.dev_attr.attr,
  314. &sensor_dev_attr_temp1_crit.dev_attr.attr,
  315. &sensor_dev_attr_temp1_min.dev_attr.attr,
  316. &sensor_dev_attr_temp1_max.dev_attr.attr,
  317. &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
  318. &sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
  319. &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
  320. &sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
  321. &sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
  322. NULL
  323. };
  324. static umode_t jc42_attribute_mode(struct kobject *kobj,
  325. struct attribute *attr, int index)
  326. {
  327. struct device *dev = container_of(kobj, struct device, kobj);
  328. struct jc42_data *data = dev_get_drvdata(dev);
  329. unsigned int config = data->config;
  330. bool readonly;
  331. if (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr)
  332. readonly = config & JC42_CFG_TCRIT_LOCK;
  333. else if (attr == &sensor_dev_attr_temp1_min.dev_attr.attr ||
  334. attr == &sensor_dev_attr_temp1_max.dev_attr.attr)
  335. readonly = config & JC42_CFG_EVENT_LOCK;
  336. else if (attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)
  337. readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);
  338. else
  339. readonly = true;
  340. return S_IRUGO | (readonly ? 0 : S_IWUSR);
  341. }
  342. static const struct attribute_group jc42_group = {
  343. .attrs = jc42_attributes,
  344. .is_visible = jc42_attribute_mode,
  345. };
  346. __ATTRIBUTE_GROUPS(jc42);
  347. /* Return 0 if detection is successful, -ENODEV otherwise */
  348. static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
  349. {
  350. struct i2c_adapter *adapter = client->adapter;
  351. int i, config, cap, manid, devid;
  352. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
  353. I2C_FUNC_SMBUS_WORD_DATA))
  354. return -ENODEV;
  355. cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
  356. config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
  357. manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
  358. devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
  359. if (cap < 0 || config < 0 || manid < 0 || devid < 0)
  360. return -ENODEV;
  361. if ((cap & 0xff00) || (config & 0xf800))
  362. return -ENODEV;
  363. for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
  364. struct jc42_chips *chip = &jc42_chips[i];
  365. if (manid == chip->manid &&
  366. (devid & chip->devid_mask) == chip->devid) {
  367. strlcpy(info->type, "jc42", I2C_NAME_SIZE);
  368. return 0;
  369. }
  370. }
  371. return -ENODEV;
  372. }
  373. static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id)
  374. {
  375. struct device *dev = &client->dev;
  376. struct device *hwmon_dev;
  377. struct jc42_data *data;
  378. int config, cap;
  379. data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
  380. if (!data)
  381. return -ENOMEM;
  382. data->client = client;
  383. i2c_set_clientdata(client, data);
  384. mutex_init(&data->update_lock);
  385. cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
  386. if (cap < 0)
  387. return cap;
  388. data->extended = !!(cap & JC42_CAP_RANGE);
  389. config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
  390. if (config < 0)
  391. return config;
  392. data->orig_config = config;
  393. if (config & JC42_CFG_SHUTDOWN) {
  394. config &= ~JC42_CFG_SHUTDOWN;
  395. i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
  396. }
  397. data->config = config;
  398. hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
  399. data,
  400. jc42_groups);
  401. return PTR_ERR_OR_ZERO(hwmon_dev);
  402. }
  403. static int jc42_remove(struct i2c_client *client)
  404. {
  405. struct jc42_data *data = i2c_get_clientdata(client);
  406. /* Restore original configuration except hysteresis */
  407. if ((data->config & ~JC42_CFG_HYST_MASK) !=
  408. (data->orig_config & ~JC42_CFG_HYST_MASK)) {
  409. int config;
  410. config = (data->orig_config & ~JC42_CFG_HYST_MASK)
  411. | (data->config & JC42_CFG_HYST_MASK);
  412. i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
  413. }
  414. return 0;
  415. }
  416. #ifdef CONFIG_PM
  417. static int jc42_suspend(struct device *dev)
  418. {
  419. struct jc42_data *data = dev_get_drvdata(dev);
  420. data->config |= JC42_CFG_SHUTDOWN;
  421. i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
  422. data->config);
  423. return 0;
  424. }
  425. static int jc42_resume(struct device *dev)
  426. {
  427. struct jc42_data *data = dev_get_drvdata(dev);
  428. data->config &= ~JC42_CFG_SHUTDOWN;
  429. i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
  430. data->config);
  431. return 0;
  432. }
  433. static const struct dev_pm_ops jc42_dev_pm_ops = {
  434. .suspend = jc42_suspend,
  435. .resume = jc42_resume,
  436. };
  437. #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
  438. #else
  439. #define JC42_DEV_PM_OPS NULL
  440. #endif /* CONFIG_PM */
  441. static const struct i2c_device_id jc42_id[] = {
  442. { "jc42", 0 },
  443. { }
  444. };
  445. MODULE_DEVICE_TABLE(i2c, jc42_id);
  446. static struct i2c_driver jc42_driver = {
  447. .class = I2C_CLASS_SPD,
  448. .driver = {
  449. .name = "jc42",
  450. .pm = JC42_DEV_PM_OPS,
  451. },
  452. .probe = jc42_probe,
  453. .remove = jc42_remove,
  454. .id_table = jc42_id,
  455. .detect = jc42_detect,
  456. .address_list = normal_i2c,
  457. };
  458. module_i2c_driver(jc42_driver);
  459. MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
  460. MODULE_DESCRIPTION("JC42 driver");
  461. MODULE_LICENSE("GPL");