dmaengine.c 30 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. #include <linux/mempool.h>
  66. static DEFINE_MUTEX(dma_list_mutex);
  67. static DEFINE_IDR(dma_idr);
  68. static LIST_HEAD(dma_device_list);
  69. static long dmaengine_ref_count;
  70. /* --- sysfs implementation --- */
  71. /**
  72. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  73. * @dev - device node
  74. *
  75. * Must be called under dma_list_mutex
  76. */
  77. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  78. {
  79. struct dma_chan_dev *chan_dev;
  80. chan_dev = container_of(dev, typeof(*chan_dev), device);
  81. return chan_dev->chan;
  82. }
  83. static ssize_t memcpy_count_show(struct device *dev,
  84. struct device_attribute *attr, char *buf)
  85. {
  86. struct dma_chan *chan;
  87. unsigned long count = 0;
  88. int i;
  89. int err;
  90. mutex_lock(&dma_list_mutex);
  91. chan = dev_to_dma_chan(dev);
  92. if (chan) {
  93. for_each_possible_cpu(i)
  94. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  95. err = sprintf(buf, "%lu\n", count);
  96. } else
  97. err = -ENODEV;
  98. mutex_unlock(&dma_list_mutex);
  99. return err;
  100. }
  101. static DEVICE_ATTR_RO(memcpy_count);
  102. static ssize_t bytes_transferred_show(struct device *dev,
  103. struct device_attribute *attr, char *buf)
  104. {
  105. struct dma_chan *chan;
  106. unsigned long count = 0;
  107. int i;
  108. int err;
  109. mutex_lock(&dma_list_mutex);
  110. chan = dev_to_dma_chan(dev);
  111. if (chan) {
  112. for_each_possible_cpu(i)
  113. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  114. err = sprintf(buf, "%lu\n", count);
  115. } else
  116. err = -ENODEV;
  117. mutex_unlock(&dma_list_mutex);
  118. return err;
  119. }
  120. static DEVICE_ATTR_RO(bytes_transferred);
  121. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  122. char *buf)
  123. {
  124. struct dma_chan *chan;
  125. int err;
  126. mutex_lock(&dma_list_mutex);
  127. chan = dev_to_dma_chan(dev);
  128. if (chan)
  129. err = sprintf(buf, "%d\n", chan->client_count);
  130. else
  131. err = -ENODEV;
  132. mutex_unlock(&dma_list_mutex);
  133. return err;
  134. }
  135. static DEVICE_ATTR_RO(in_use);
  136. static struct attribute *dma_dev_attrs[] = {
  137. &dev_attr_memcpy_count.attr,
  138. &dev_attr_bytes_transferred.attr,
  139. &dev_attr_in_use.attr,
  140. NULL,
  141. };
  142. ATTRIBUTE_GROUPS(dma_dev);
  143. static void chan_dev_release(struct device *dev)
  144. {
  145. struct dma_chan_dev *chan_dev;
  146. chan_dev = container_of(dev, typeof(*chan_dev), device);
  147. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  148. mutex_lock(&dma_list_mutex);
  149. idr_remove(&dma_idr, chan_dev->dev_id);
  150. mutex_unlock(&dma_list_mutex);
  151. kfree(chan_dev->idr_ref);
  152. }
  153. kfree(chan_dev);
  154. }
  155. static struct class dma_devclass = {
  156. .name = "dma",
  157. .dev_groups = dma_dev_groups,
  158. .dev_release = chan_dev_release,
  159. };
  160. /* --- client and device registration --- */
  161. #define dma_device_satisfies_mask(device, mask) \
  162. __dma_device_satisfies_mask((device), &(mask))
  163. static int
  164. __dma_device_satisfies_mask(struct dma_device *device,
  165. const dma_cap_mask_t *want)
  166. {
  167. dma_cap_mask_t has;
  168. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  169. DMA_TX_TYPE_END);
  170. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  171. }
  172. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  173. {
  174. return chan->device->dev->driver->owner;
  175. }
  176. /**
  177. * balance_ref_count - catch up the channel reference count
  178. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  179. *
  180. * balance_ref_count must be called under dma_list_mutex
  181. */
  182. static void balance_ref_count(struct dma_chan *chan)
  183. {
  184. struct module *owner = dma_chan_to_owner(chan);
  185. while (chan->client_count < dmaengine_ref_count) {
  186. __module_get(owner);
  187. chan->client_count++;
  188. }
  189. }
  190. /**
  191. * dma_chan_get - try to grab a dma channel's parent driver module
  192. * @chan - channel to grab
  193. *
  194. * Must be called under dma_list_mutex
  195. */
  196. static int dma_chan_get(struct dma_chan *chan)
  197. {
  198. struct module *owner = dma_chan_to_owner(chan);
  199. int ret;
  200. /* The channel is already in use, update client count */
  201. if (chan->client_count) {
  202. __module_get(owner);
  203. goto out;
  204. }
  205. if (!try_module_get(owner))
  206. return -ENODEV;
  207. /* allocate upon first client reference */
  208. if (chan->device->device_alloc_chan_resources) {
  209. ret = chan->device->device_alloc_chan_resources(chan);
  210. if (ret < 0)
  211. goto err_out;
  212. }
  213. if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  214. balance_ref_count(chan);
  215. out:
  216. chan->client_count++;
  217. return 0;
  218. err_out:
  219. module_put(owner);
  220. return ret;
  221. }
  222. /**
  223. * dma_chan_put - drop a reference to a dma channel's parent driver module
  224. * @chan - channel to release
  225. *
  226. * Must be called under dma_list_mutex
  227. */
  228. static void dma_chan_put(struct dma_chan *chan)
  229. {
  230. /* This channel is not in use, bail out */
  231. if (!chan->client_count)
  232. return;
  233. chan->client_count--;
  234. module_put(dma_chan_to_owner(chan));
  235. /* This channel is not in use anymore, free it */
  236. if (!chan->client_count && chan->device->device_free_chan_resources)
  237. chan->device->device_free_chan_resources(chan);
  238. }
  239. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  240. {
  241. enum dma_status status;
  242. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  243. dma_async_issue_pending(chan);
  244. do {
  245. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  246. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  247. pr_err("%s: timeout!\n", __func__);
  248. return DMA_ERROR;
  249. }
  250. if (status != DMA_IN_PROGRESS)
  251. break;
  252. cpu_relax();
  253. } while (1);
  254. return status;
  255. }
  256. EXPORT_SYMBOL(dma_sync_wait);
  257. /**
  258. * dma_cap_mask_all - enable iteration over all operation types
  259. */
  260. static dma_cap_mask_t dma_cap_mask_all;
  261. /**
  262. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  263. * @chan - associated channel for this entry
  264. */
  265. struct dma_chan_tbl_ent {
  266. struct dma_chan *chan;
  267. };
  268. /**
  269. * channel_table - percpu lookup table for memory-to-memory offload providers
  270. */
  271. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  272. static int __init dma_channel_table_init(void)
  273. {
  274. enum dma_transaction_type cap;
  275. int err = 0;
  276. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  277. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  278. * but are not associated with an operation so they do not need
  279. * an entry in the channel_table
  280. */
  281. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  282. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  283. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  284. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  285. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  286. if (!channel_table[cap]) {
  287. err = -ENOMEM;
  288. break;
  289. }
  290. }
  291. if (err) {
  292. pr_err("initialization failure\n");
  293. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  294. free_percpu(channel_table[cap]);
  295. }
  296. return err;
  297. }
  298. arch_initcall(dma_channel_table_init);
  299. /**
  300. * dma_find_channel - find a channel to carry out the operation
  301. * @tx_type: transaction type
  302. */
  303. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  304. {
  305. return this_cpu_read(channel_table[tx_type]->chan);
  306. }
  307. EXPORT_SYMBOL(dma_find_channel);
  308. /*
  309. * net_dma_find_channel - find a channel for net_dma
  310. * net_dma has alignment requirements
  311. */
  312. struct dma_chan *net_dma_find_channel(void)
  313. {
  314. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  315. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  316. return NULL;
  317. return chan;
  318. }
  319. EXPORT_SYMBOL(net_dma_find_channel);
  320. /**
  321. * dma_issue_pending_all - flush all pending operations across all channels
  322. */
  323. void dma_issue_pending_all(void)
  324. {
  325. struct dma_device *device;
  326. struct dma_chan *chan;
  327. rcu_read_lock();
  328. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  329. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  330. continue;
  331. list_for_each_entry(chan, &device->channels, device_node)
  332. if (chan->client_count)
  333. device->device_issue_pending(chan);
  334. }
  335. rcu_read_unlock();
  336. }
  337. EXPORT_SYMBOL(dma_issue_pending_all);
  338. /**
  339. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  340. */
  341. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  342. {
  343. int node = dev_to_node(chan->device->dev);
  344. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  345. }
  346. /**
  347. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  348. * @cap: capability to match
  349. * @cpu: cpu index which the channel should be close to
  350. *
  351. * If some channels are close to the given cpu, the one with the lowest
  352. * reference count is returned. Otherwise, cpu is ignored and only the
  353. * reference count is taken into account.
  354. * Must be called under dma_list_mutex.
  355. */
  356. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  357. {
  358. struct dma_device *device;
  359. struct dma_chan *chan;
  360. struct dma_chan *min = NULL;
  361. struct dma_chan *localmin = NULL;
  362. list_for_each_entry(device, &dma_device_list, global_node) {
  363. if (!dma_has_cap(cap, device->cap_mask) ||
  364. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  365. continue;
  366. list_for_each_entry(chan, &device->channels, device_node) {
  367. if (!chan->client_count)
  368. continue;
  369. if (!min || chan->table_count < min->table_count)
  370. min = chan;
  371. if (dma_chan_is_local(chan, cpu))
  372. if (!localmin ||
  373. chan->table_count < localmin->table_count)
  374. localmin = chan;
  375. }
  376. }
  377. chan = localmin ? localmin : min;
  378. if (chan)
  379. chan->table_count++;
  380. return chan;
  381. }
  382. /**
  383. * dma_channel_rebalance - redistribute the available channels
  384. *
  385. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  386. * operation type) in the SMP case, and operation isolation (avoid
  387. * multi-tasking channels) in the non-SMP case. Must be called under
  388. * dma_list_mutex.
  389. */
  390. static void dma_channel_rebalance(void)
  391. {
  392. struct dma_chan *chan;
  393. struct dma_device *device;
  394. int cpu;
  395. int cap;
  396. /* undo the last distribution */
  397. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  398. for_each_possible_cpu(cpu)
  399. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  400. list_for_each_entry(device, &dma_device_list, global_node) {
  401. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  402. continue;
  403. list_for_each_entry(chan, &device->channels, device_node)
  404. chan->table_count = 0;
  405. }
  406. /* don't populate the channel_table if no clients are available */
  407. if (!dmaengine_ref_count)
  408. return;
  409. /* redistribute available channels */
  410. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  411. for_each_online_cpu(cpu) {
  412. chan = min_chan(cap, cpu);
  413. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  414. }
  415. }
  416. int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
  417. {
  418. struct dma_device *device;
  419. if (!chan || !caps)
  420. return -EINVAL;
  421. device = chan->device;
  422. /* check if the channel supports slave transactions */
  423. if (!test_bit(DMA_SLAVE, device->cap_mask.bits))
  424. return -ENXIO;
  425. /*
  426. * Check whether it reports it uses the generic slave
  427. * capabilities, if not, that means it doesn't support any
  428. * kind of slave capabilities reporting.
  429. */
  430. if (!device->directions)
  431. return -ENXIO;
  432. caps->src_addr_widths = device->src_addr_widths;
  433. caps->dst_addr_widths = device->dst_addr_widths;
  434. caps->directions = device->directions;
  435. caps->residue_granularity = device->residue_granularity;
  436. caps->cmd_pause = !!device->device_pause;
  437. caps->cmd_terminate = !!device->device_terminate_all;
  438. return 0;
  439. }
  440. EXPORT_SYMBOL_GPL(dma_get_slave_caps);
  441. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  442. struct dma_device *dev,
  443. dma_filter_fn fn, void *fn_param)
  444. {
  445. struct dma_chan *chan;
  446. if (!__dma_device_satisfies_mask(dev, mask)) {
  447. pr_debug("%s: wrong capabilities\n", __func__);
  448. return NULL;
  449. }
  450. /* devices with multiple channels need special handling as we need to
  451. * ensure that all channels are either private or public.
  452. */
  453. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  454. list_for_each_entry(chan, &dev->channels, device_node) {
  455. /* some channels are already publicly allocated */
  456. if (chan->client_count)
  457. return NULL;
  458. }
  459. list_for_each_entry(chan, &dev->channels, device_node) {
  460. if (chan->client_count) {
  461. pr_debug("%s: %s busy\n",
  462. __func__, dma_chan_name(chan));
  463. continue;
  464. }
  465. if (fn && !fn(chan, fn_param)) {
  466. pr_debug("%s: %s filter said false\n",
  467. __func__, dma_chan_name(chan));
  468. continue;
  469. }
  470. return chan;
  471. }
  472. return NULL;
  473. }
  474. /**
  475. * dma_request_slave_channel - try to get specific channel exclusively
  476. * @chan: target channel
  477. */
  478. struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  479. {
  480. int err = -EBUSY;
  481. /* lock against __dma_request_channel */
  482. mutex_lock(&dma_list_mutex);
  483. if (chan->client_count == 0) {
  484. err = dma_chan_get(chan);
  485. if (err)
  486. pr_debug("%s: failed to get %s: (%d)\n",
  487. __func__, dma_chan_name(chan), err);
  488. } else
  489. chan = NULL;
  490. mutex_unlock(&dma_list_mutex);
  491. return chan;
  492. }
  493. EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  494. struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
  495. {
  496. dma_cap_mask_t mask;
  497. struct dma_chan *chan;
  498. int err;
  499. dma_cap_zero(mask);
  500. dma_cap_set(DMA_SLAVE, mask);
  501. /* lock against __dma_request_channel */
  502. mutex_lock(&dma_list_mutex);
  503. chan = private_candidate(&mask, device, NULL, NULL);
  504. if (chan) {
  505. err = dma_chan_get(chan);
  506. if (err) {
  507. pr_debug("%s: failed to get %s: (%d)\n",
  508. __func__, dma_chan_name(chan), err);
  509. chan = NULL;
  510. }
  511. }
  512. mutex_unlock(&dma_list_mutex);
  513. return chan;
  514. }
  515. EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
  516. /**
  517. * __dma_request_channel - try to allocate an exclusive channel
  518. * @mask: capabilities that the channel must satisfy
  519. * @fn: optional callback to disposition available channels
  520. * @fn_param: opaque parameter to pass to dma_filter_fn
  521. *
  522. * Returns pointer to appropriate DMA channel on success or NULL.
  523. */
  524. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  525. dma_filter_fn fn, void *fn_param)
  526. {
  527. struct dma_device *device, *_d;
  528. struct dma_chan *chan = NULL;
  529. int err;
  530. /* Find a channel */
  531. mutex_lock(&dma_list_mutex);
  532. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  533. chan = private_candidate(mask, device, fn, fn_param);
  534. if (chan) {
  535. /* Found a suitable channel, try to grab, prep, and
  536. * return it. We first set DMA_PRIVATE to disable
  537. * balance_ref_count as this channel will not be
  538. * published in the general-purpose allocator
  539. */
  540. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  541. device->privatecnt++;
  542. err = dma_chan_get(chan);
  543. if (err == -ENODEV) {
  544. pr_debug("%s: %s module removed\n",
  545. __func__, dma_chan_name(chan));
  546. list_del_rcu(&device->global_node);
  547. } else if (err)
  548. pr_debug("%s: failed to get %s: (%d)\n",
  549. __func__, dma_chan_name(chan), err);
  550. else
  551. break;
  552. if (--device->privatecnt == 0)
  553. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  554. chan = NULL;
  555. }
  556. }
  557. mutex_unlock(&dma_list_mutex);
  558. pr_debug("%s: %s (%s)\n",
  559. __func__,
  560. chan ? "success" : "fail",
  561. chan ? dma_chan_name(chan) : NULL);
  562. return chan;
  563. }
  564. EXPORT_SYMBOL_GPL(__dma_request_channel);
  565. /**
  566. * dma_request_slave_channel - try to allocate an exclusive slave channel
  567. * @dev: pointer to client device structure
  568. * @name: slave channel name
  569. *
  570. * Returns pointer to appropriate DMA channel on success or an error pointer.
  571. */
  572. struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
  573. const char *name)
  574. {
  575. /* If device-tree is present get slave info from here */
  576. if (dev->of_node)
  577. return of_dma_request_slave_channel(dev->of_node, name);
  578. /* If device was enumerated by ACPI get slave info from here */
  579. if (ACPI_HANDLE(dev))
  580. return acpi_dma_request_slave_chan_by_name(dev, name);
  581. return ERR_PTR(-ENODEV);
  582. }
  583. EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
  584. /**
  585. * dma_request_slave_channel - try to allocate an exclusive slave channel
  586. * @dev: pointer to client device structure
  587. * @name: slave channel name
  588. *
  589. * Returns pointer to appropriate DMA channel on success or NULL.
  590. */
  591. struct dma_chan *dma_request_slave_channel(struct device *dev,
  592. const char *name)
  593. {
  594. struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
  595. if (IS_ERR(ch))
  596. return NULL;
  597. return ch;
  598. }
  599. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  600. void dma_release_channel(struct dma_chan *chan)
  601. {
  602. mutex_lock(&dma_list_mutex);
  603. WARN_ONCE(chan->client_count != 1,
  604. "chan reference count %d != 1\n", chan->client_count);
  605. dma_chan_put(chan);
  606. /* drop PRIVATE cap enabled by __dma_request_channel() */
  607. if (--chan->device->privatecnt == 0)
  608. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  609. mutex_unlock(&dma_list_mutex);
  610. }
  611. EXPORT_SYMBOL_GPL(dma_release_channel);
  612. /**
  613. * dmaengine_get - register interest in dma_channels
  614. */
  615. void dmaengine_get(void)
  616. {
  617. struct dma_device *device, *_d;
  618. struct dma_chan *chan;
  619. int err;
  620. mutex_lock(&dma_list_mutex);
  621. dmaengine_ref_count++;
  622. /* try to grab channels */
  623. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  624. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  625. continue;
  626. list_for_each_entry(chan, &device->channels, device_node) {
  627. err = dma_chan_get(chan);
  628. if (err == -ENODEV) {
  629. /* module removed before we could use it */
  630. list_del_rcu(&device->global_node);
  631. break;
  632. } else if (err)
  633. pr_debug("%s: failed to get %s: (%d)\n",
  634. __func__, dma_chan_name(chan), err);
  635. }
  636. }
  637. /* if this is the first reference and there were channels
  638. * waiting we need to rebalance to get those channels
  639. * incorporated into the channel table
  640. */
  641. if (dmaengine_ref_count == 1)
  642. dma_channel_rebalance();
  643. mutex_unlock(&dma_list_mutex);
  644. }
  645. EXPORT_SYMBOL(dmaengine_get);
  646. /**
  647. * dmaengine_put - let dma drivers be removed when ref_count == 0
  648. */
  649. void dmaengine_put(void)
  650. {
  651. struct dma_device *device;
  652. struct dma_chan *chan;
  653. mutex_lock(&dma_list_mutex);
  654. dmaengine_ref_count--;
  655. BUG_ON(dmaengine_ref_count < 0);
  656. /* drop channel references */
  657. list_for_each_entry(device, &dma_device_list, global_node) {
  658. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  659. continue;
  660. list_for_each_entry(chan, &device->channels, device_node)
  661. dma_chan_put(chan);
  662. }
  663. mutex_unlock(&dma_list_mutex);
  664. }
  665. EXPORT_SYMBOL(dmaengine_put);
  666. static bool device_has_all_tx_types(struct dma_device *device)
  667. {
  668. /* A device that satisfies this test has channels that will never cause
  669. * an async_tx channel switch event as all possible operation types can
  670. * be handled.
  671. */
  672. #ifdef CONFIG_ASYNC_TX_DMA
  673. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  674. return false;
  675. #endif
  676. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  677. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  678. return false;
  679. #endif
  680. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  681. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  682. return false;
  683. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  684. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  685. return false;
  686. #endif
  687. #endif
  688. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  689. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  690. return false;
  691. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  692. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  693. return false;
  694. #endif
  695. #endif
  696. return true;
  697. }
  698. static int get_dma_id(struct dma_device *device)
  699. {
  700. int rc;
  701. mutex_lock(&dma_list_mutex);
  702. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  703. if (rc >= 0)
  704. device->dev_id = rc;
  705. mutex_unlock(&dma_list_mutex);
  706. return rc < 0 ? rc : 0;
  707. }
  708. /**
  709. * dma_async_device_register - registers DMA devices found
  710. * @device: &dma_device
  711. */
  712. int dma_async_device_register(struct dma_device *device)
  713. {
  714. int chancnt = 0, rc;
  715. struct dma_chan* chan;
  716. atomic_t *idr_ref;
  717. if (!device)
  718. return -ENODEV;
  719. /* validate device routines */
  720. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  721. !device->device_prep_dma_memcpy);
  722. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  723. !device->device_prep_dma_xor);
  724. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  725. !device->device_prep_dma_xor_val);
  726. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  727. !device->device_prep_dma_pq);
  728. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  729. !device->device_prep_dma_pq_val);
  730. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  731. !device->device_prep_dma_interrupt);
  732. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  733. !device->device_prep_dma_sg);
  734. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  735. !device->device_prep_dma_cyclic);
  736. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  737. !device->device_prep_interleaved_dma);
  738. BUG_ON(!device->device_tx_status);
  739. BUG_ON(!device->device_issue_pending);
  740. BUG_ON(!device->dev);
  741. WARN(dma_has_cap(DMA_SLAVE, device->cap_mask) && !device->directions,
  742. "this driver doesn't support generic slave capabilities reporting\n");
  743. /* note: this only matters in the
  744. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  745. */
  746. if (device_has_all_tx_types(device))
  747. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  748. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  749. if (!idr_ref)
  750. return -ENOMEM;
  751. rc = get_dma_id(device);
  752. if (rc != 0) {
  753. kfree(idr_ref);
  754. return rc;
  755. }
  756. atomic_set(idr_ref, 0);
  757. /* represent channels in sysfs. Probably want devs too */
  758. list_for_each_entry(chan, &device->channels, device_node) {
  759. rc = -ENOMEM;
  760. chan->local = alloc_percpu(typeof(*chan->local));
  761. if (chan->local == NULL)
  762. goto err_out;
  763. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  764. if (chan->dev == NULL) {
  765. free_percpu(chan->local);
  766. chan->local = NULL;
  767. goto err_out;
  768. }
  769. chan->chan_id = chancnt++;
  770. chan->dev->device.class = &dma_devclass;
  771. chan->dev->device.parent = device->dev;
  772. chan->dev->chan = chan;
  773. chan->dev->idr_ref = idr_ref;
  774. chan->dev->dev_id = device->dev_id;
  775. atomic_inc(idr_ref);
  776. dev_set_name(&chan->dev->device, "dma%dchan%d",
  777. device->dev_id, chan->chan_id);
  778. rc = device_register(&chan->dev->device);
  779. if (rc) {
  780. free_percpu(chan->local);
  781. chan->local = NULL;
  782. kfree(chan->dev);
  783. atomic_dec(idr_ref);
  784. goto err_out;
  785. }
  786. chan->client_count = 0;
  787. }
  788. device->chancnt = chancnt;
  789. mutex_lock(&dma_list_mutex);
  790. /* take references on public channels */
  791. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  792. list_for_each_entry(chan, &device->channels, device_node) {
  793. /* if clients are already waiting for channels we need
  794. * to take references on their behalf
  795. */
  796. if (dma_chan_get(chan) == -ENODEV) {
  797. /* note we can only get here for the first
  798. * channel as the remaining channels are
  799. * guaranteed to get a reference
  800. */
  801. rc = -ENODEV;
  802. mutex_unlock(&dma_list_mutex);
  803. goto err_out;
  804. }
  805. }
  806. list_add_tail_rcu(&device->global_node, &dma_device_list);
  807. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  808. device->privatecnt++; /* Always private */
  809. dma_channel_rebalance();
  810. mutex_unlock(&dma_list_mutex);
  811. return 0;
  812. err_out:
  813. /* if we never registered a channel just release the idr */
  814. if (atomic_read(idr_ref) == 0) {
  815. mutex_lock(&dma_list_mutex);
  816. idr_remove(&dma_idr, device->dev_id);
  817. mutex_unlock(&dma_list_mutex);
  818. kfree(idr_ref);
  819. return rc;
  820. }
  821. list_for_each_entry(chan, &device->channels, device_node) {
  822. if (chan->local == NULL)
  823. continue;
  824. mutex_lock(&dma_list_mutex);
  825. chan->dev->chan = NULL;
  826. mutex_unlock(&dma_list_mutex);
  827. device_unregister(&chan->dev->device);
  828. free_percpu(chan->local);
  829. }
  830. return rc;
  831. }
  832. EXPORT_SYMBOL(dma_async_device_register);
  833. /**
  834. * dma_async_device_unregister - unregister a DMA device
  835. * @device: &dma_device
  836. *
  837. * This routine is called by dma driver exit routines, dmaengine holds module
  838. * references to prevent it being called while channels are in use.
  839. */
  840. void dma_async_device_unregister(struct dma_device *device)
  841. {
  842. struct dma_chan *chan;
  843. mutex_lock(&dma_list_mutex);
  844. list_del_rcu(&device->global_node);
  845. dma_channel_rebalance();
  846. mutex_unlock(&dma_list_mutex);
  847. list_for_each_entry(chan, &device->channels, device_node) {
  848. WARN_ONCE(chan->client_count,
  849. "%s called while %d clients hold a reference\n",
  850. __func__, chan->client_count);
  851. mutex_lock(&dma_list_mutex);
  852. chan->dev->chan = NULL;
  853. mutex_unlock(&dma_list_mutex);
  854. device_unregister(&chan->dev->device);
  855. free_percpu(chan->local);
  856. }
  857. }
  858. EXPORT_SYMBOL(dma_async_device_unregister);
  859. struct dmaengine_unmap_pool {
  860. struct kmem_cache *cache;
  861. const char *name;
  862. mempool_t *pool;
  863. size_t size;
  864. };
  865. #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
  866. static struct dmaengine_unmap_pool unmap_pool[] = {
  867. __UNMAP_POOL(2),
  868. #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
  869. __UNMAP_POOL(16),
  870. __UNMAP_POOL(128),
  871. __UNMAP_POOL(256),
  872. #endif
  873. };
  874. static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
  875. {
  876. int order = get_count_order(nr);
  877. switch (order) {
  878. case 0 ... 1:
  879. return &unmap_pool[0];
  880. case 2 ... 4:
  881. return &unmap_pool[1];
  882. case 5 ... 7:
  883. return &unmap_pool[2];
  884. case 8:
  885. return &unmap_pool[3];
  886. default:
  887. BUG();
  888. return NULL;
  889. }
  890. }
  891. static void dmaengine_unmap(struct kref *kref)
  892. {
  893. struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
  894. struct device *dev = unmap->dev;
  895. int cnt, i;
  896. cnt = unmap->to_cnt;
  897. for (i = 0; i < cnt; i++)
  898. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  899. DMA_TO_DEVICE);
  900. cnt += unmap->from_cnt;
  901. for (; i < cnt; i++)
  902. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  903. DMA_FROM_DEVICE);
  904. cnt += unmap->bidi_cnt;
  905. for (; i < cnt; i++) {
  906. if (unmap->addr[i] == 0)
  907. continue;
  908. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  909. DMA_BIDIRECTIONAL);
  910. }
  911. cnt = unmap->map_cnt;
  912. mempool_free(unmap, __get_unmap_pool(cnt)->pool);
  913. }
  914. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
  915. {
  916. if (unmap)
  917. kref_put(&unmap->kref, dmaengine_unmap);
  918. }
  919. EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
  920. static void dmaengine_destroy_unmap_pool(void)
  921. {
  922. int i;
  923. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  924. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  925. if (p->pool)
  926. mempool_destroy(p->pool);
  927. p->pool = NULL;
  928. if (p->cache)
  929. kmem_cache_destroy(p->cache);
  930. p->cache = NULL;
  931. }
  932. }
  933. static int __init dmaengine_init_unmap_pool(void)
  934. {
  935. int i;
  936. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  937. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  938. size_t size;
  939. size = sizeof(struct dmaengine_unmap_data) +
  940. sizeof(dma_addr_t) * p->size;
  941. p->cache = kmem_cache_create(p->name, size, 0,
  942. SLAB_HWCACHE_ALIGN, NULL);
  943. if (!p->cache)
  944. break;
  945. p->pool = mempool_create_slab_pool(1, p->cache);
  946. if (!p->pool)
  947. break;
  948. }
  949. if (i == ARRAY_SIZE(unmap_pool))
  950. return 0;
  951. dmaengine_destroy_unmap_pool();
  952. return -ENOMEM;
  953. }
  954. struct dmaengine_unmap_data *
  955. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
  956. {
  957. struct dmaengine_unmap_data *unmap;
  958. unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
  959. if (!unmap)
  960. return NULL;
  961. memset(unmap, 0, sizeof(*unmap));
  962. kref_init(&unmap->kref);
  963. unmap->dev = dev;
  964. unmap->map_cnt = nr;
  965. return unmap;
  966. }
  967. EXPORT_SYMBOL(dmaengine_get_unmap_data);
  968. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  969. struct dma_chan *chan)
  970. {
  971. tx->chan = chan;
  972. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  973. spin_lock_init(&tx->lock);
  974. #endif
  975. }
  976. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  977. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  978. * @tx: in-flight transaction to wait on
  979. */
  980. enum dma_status
  981. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  982. {
  983. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  984. if (!tx)
  985. return DMA_COMPLETE;
  986. while (tx->cookie == -EBUSY) {
  987. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  988. pr_err("%s timeout waiting for descriptor submission\n",
  989. __func__);
  990. return DMA_ERROR;
  991. }
  992. cpu_relax();
  993. }
  994. return dma_sync_wait(tx->chan, tx->cookie);
  995. }
  996. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  997. /* dma_run_dependencies - helper routine for dma drivers to process
  998. * (start) dependent operations on their target channel
  999. * @tx: transaction with dependencies
  1000. */
  1001. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  1002. {
  1003. struct dma_async_tx_descriptor *dep = txd_next(tx);
  1004. struct dma_async_tx_descriptor *dep_next;
  1005. struct dma_chan *chan;
  1006. if (!dep)
  1007. return;
  1008. /* we'll submit tx->next now, so clear the link */
  1009. txd_clear_next(tx);
  1010. chan = dep->chan;
  1011. /* keep submitting up until a channel switch is detected
  1012. * in that case we will be called again as a result of
  1013. * processing the interrupt from async_tx_channel_switch
  1014. */
  1015. for (; dep; dep = dep_next) {
  1016. txd_lock(dep);
  1017. txd_clear_parent(dep);
  1018. dep_next = txd_next(dep);
  1019. if (dep_next && dep_next->chan == chan)
  1020. txd_clear_next(dep); /* ->next will be submitted */
  1021. else
  1022. dep_next = NULL; /* submit current dep and terminate */
  1023. txd_unlock(dep);
  1024. dep->tx_submit(dep);
  1025. }
  1026. chan->device->device_issue_pending(chan);
  1027. }
  1028. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  1029. static int __init dma_bus_init(void)
  1030. {
  1031. int err = dmaengine_init_unmap_pool();
  1032. if (err)
  1033. return err;
  1034. return class_register(&dma_devclass);
  1035. }
  1036. arch_initcall(dma_bus_init);