omap_crtc.c 15 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_crtc.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/completion.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc.h>
  23. #include <drm/drm_crtc_helper.h>
  24. #include <drm/drm_mode.h>
  25. #include <drm/drm_plane_helper.h>
  26. #include "omap_drv.h"
  27. #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
  28. struct omap_crtc {
  29. struct drm_crtc base;
  30. const char *name;
  31. enum omap_channel channel;
  32. /*
  33. * Temporary: eventually this will go away, but it is needed
  34. * for now to keep the output's happy. (They only need
  35. * mgr->id.) Eventually this will be replaced w/ something
  36. * more common-panel-framework-y
  37. */
  38. struct omap_overlay_manager *mgr;
  39. struct omap_video_timings timings;
  40. struct omap_drm_irq vblank_irq;
  41. struct omap_drm_irq error_irq;
  42. /* pending event */
  43. struct drm_pending_vblank_event *event;
  44. wait_queue_head_t flip_wait;
  45. struct completion completion;
  46. bool ignore_digit_sync_lost;
  47. };
  48. /* -----------------------------------------------------------------------------
  49. * Helper Functions
  50. */
  51. uint32_t pipe2vbl(struct drm_crtc *crtc)
  52. {
  53. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  54. return dispc_mgr_get_vsync_irq(omap_crtc->channel);
  55. }
  56. struct omap_video_timings *omap_crtc_timings(struct drm_crtc *crtc)
  57. {
  58. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  59. return &omap_crtc->timings;
  60. }
  61. enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
  62. {
  63. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  64. return omap_crtc->channel;
  65. }
  66. /* -----------------------------------------------------------------------------
  67. * DSS Manager Functions
  68. */
  69. /*
  70. * Manager-ops, callbacks from output when they need to configure
  71. * the upstream part of the video pipe.
  72. *
  73. * Most of these we can ignore until we add support for command-mode
  74. * panels.. for video-mode the crtc-helpers already do an adequate
  75. * job of sequencing the setup of the video pipe in the proper order
  76. */
  77. /* ovl-mgr-id -> crtc */
  78. static struct omap_crtc *omap_crtcs[8];
  79. /* we can probably ignore these until we support command-mode panels: */
  80. static int omap_crtc_dss_connect(struct omap_overlay_manager *mgr,
  81. struct omap_dss_device *dst)
  82. {
  83. if (mgr->output)
  84. return -EINVAL;
  85. if ((mgr->supported_outputs & dst->id) == 0)
  86. return -EINVAL;
  87. dst->manager = mgr;
  88. mgr->output = dst;
  89. return 0;
  90. }
  91. static void omap_crtc_dss_disconnect(struct omap_overlay_manager *mgr,
  92. struct omap_dss_device *dst)
  93. {
  94. mgr->output->manager = NULL;
  95. mgr->output = NULL;
  96. }
  97. static void omap_crtc_dss_start_update(struct omap_overlay_manager *mgr)
  98. {
  99. }
  100. /* Called only from the encoder enable/disable and suspend/resume handlers. */
  101. static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
  102. {
  103. struct drm_device *dev = crtc->dev;
  104. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  105. enum omap_channel channel = omap_crtc->channel;
  106. struct omap_irq_wait *wait;
  107. u32 framedone_irq, vsync_irq;
  108. int ret;
  109. if (dispc_mgr_is_enabled(channel) == enable)
  110. return;
  111. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  112. /*
  113. * Digit output produces some sync lost interrupts during the
  114. * first frame when enabling, so we need to ignore those.
  115. */
  116. omap_crtc->ignore_digit_sync_lost = true;
  117. }
  118. framedone_irq = dispc_mgr_get_framedone_irq(channel);
  119. vsync_irq = dispc_mgr_get_vsync_irq(channel);
  120. if (enable) {
  121. wait = omap_irq_wait_init(dev, vsync_irq, 1);
  122. } else {
  123. /*
  124. * When we disable the digit output, we need to wait for
  125. * FRAMEDONE to know that DISPC has finished with the output.
  126. *
  127. * OMAP2/3 does not have FRAMEDONE irq for digit output, and in
  128. * that case we need to use vsync interrupt, and wait for both
  129. * even and odd frames.
  130. */
  131. if (framedone_irq)
  132. wait = omap_irq_wait_init(dev, framedone_irq, 1);
  133. else
  134. wait = omap_irq_wait_init(dev, vsync_irq, 2);
  135. }
  136. dispc_mgr_enable(channel, enable);
  137. ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
  138. if (ret) {
  139. dev_err(dev->dev, "%s: timeout waiting for %s\n",
  140. omap_crtc->name, enable ? "enable" : "disable");
  141. }
  142. if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
  143. omap_crtc->ignore_digit_sync_lost = false;
  144. /* make sure the irq handler sees the value above */
  145. mb();
  146. }
  147. }
  148. static int omap_crtc_dss_enable(struct omap_overlay_manager *mgr)
  149. {
  150. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  151. struct omap_overlay_manager_info info;
  152. memset(&info, 0, sizeof(info));
  153. info.default_color = 0x00000000;
  154. info.trans_key = 0x00000000;
  155. info.trans_key_type = OMAP_DSS_COLOR_KEY_GFX_DST;
  156. info.trans_enabled = false;
  157. dispc_mgr_setup(omap_crtc->channel, &info);
  158. dispc_mgr_set_timings(omap_crtc->channel,
  159. &omap_crtc->timings);
  160. omap_crtc_set_enabled(&omap_crtc->base, true);
  161. return 0;
  162. }
  163. static void omap_crtc_dss_disable(struct omap_overlay_manager *mgr)
  164. {
  165. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  166. omap_crtc_set_enabled(&omap_crtc->base, false);
  167. }
  168. static void omap_crtc_dss_set_timings(struct omap_overlay_manager *mgr,
  169. const struct omap_video_timings *timings)
  170. {
  171. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  172. DBG("%s", omap_crtc->name);
  173. omap_crtc->timings = *timings;
  174. }
  175. static void omap_crtc_dss_set_lcd_config(struct omap_overlay_manager *mgr,
  176. const struct dss_lcd_mgr_config *config)
  177. {
  178. struct omap_crtc *omap_crtc = omap_crtcs[mgr->id];
  179. DBG("%s", omap_crtc->name);
  180. dispc_mgr_set_lcd_config(omap_crtc->channel, config);
  181. }
  182. static int omap_crtc_dss_register_framedone(
  183. struct omap_overlay_manager *mgr,
  184. void (*handler)(void *), void *data)
  185. {
  186. return 0;
  187. }
  188. static void omap_crtc_dss_unregister_framedone(
  189. struct omap_overlay_manager *mgr,
  190. void (*handler)(void *), void *data)
  191. {
  192. }
  193. static const struct dss_mgr_ops mgr_ops = {
  194. .connect = omap_crtc_dss_connect,
  195. .disconnect = omap_crtc_dss_disconnect,
  196. .start_update = omap_crtc_dss_start_update,
  197. .enable = omap_crtc_dss_enable,
  198. .disable = omap_crtc_dss_disable,
  199. .set_timings = omap_crtc_dss_set_timings,
  200. .set_lcd_config = omap_crtc_dss_set_lcd_config,
  201. .register_framedone_handler = omap_crtc_dss_register_framedone,
  202. .unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
  203. };
  204. /* -----------------------------------------------------------------------------
  205. * Setup, Flush and Page Flip
  206. */
  207. static void omap_crtc_complete_page_flip(struct drm_crtc *crtc)
  208. {
  209. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  210. struct drm_pending_vblank_event *event;
  211. struct drm_device *dev = crtc->dev;
  212. unsigned long flags;
  213. spin_lock_irqsave(&dev->event_lock, flags);
  214. event = omap_crtc->event;
  215. omap_crtc->event = NULL;
  216. if (event) {
  217. list_del(&event->base.link);
  218. /*
  219. * Queue the event for delivery if it's still linked to a file
  220. * handle, otherwise just destroy it.
  221. */
  222. if (event->base.file_priv)
  223. drm_crtc_send_vblank_event(crtc, event);
  224. else
  225. event->base.destroy(&event->base);
  226. wake_up(&omap_crtc->flip_wait);
  227. drm_crtc_vblank_put(crtc);
  228. }
  229. spin_unlock_irqrestore(&dev->event_lock, flags);
  230. }
  231. static bool omap_crtc_page_flip_pending(struct drm_crtc *crtc)
  232. {
  233. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  234. struct drm_device *dev = crtc->dev;
  235. unsigned long flags;
  236. bool pending;
  237. spin_lock_irqsave(&dev->event_lock, flags);
  238. pending = omap_crtc->event != NULL;
  239. spin_unlock_irqrestore(&dev->event_lock, flags);
  240. return pending;
  241. }
  242. static void omap_crtc_wait_page_flip(struct drm_crtc *crtc)
  243. {
  244. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  245. if (wait_event_timeout(omap_crtc->flip_wait,
  246. !omap_crtc_page_flip_pending(crtc),
  247. msecs_to_jiffies(50)))
  248. return;
  249. dev_warn(crtc->dev->dev, "page flip timeout!\n");
  250. omap_crtc_complete_page_flip(crtc);
  251. }
  252. static void omap_crtc_error_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  253. {
  254. struct omap_crtc *omap_crtc =
  255. container_of(irq, struct omap_crtc, error_irq);
  256. if (omap_crtc->ignore_digit_sync_lost) {
  257. irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
  258. if (!irqstatus)
  259. return;
  260. }
  261. DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
  262. }
  263. static void omap_crtc_vblank_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  264. {
  265. struct omap_crtc *omap_crtc =
  266. container_of(irq, struct omap_crtc, vblank_irq);
  267. struct drm_device *dev = omap_crtc->base.dev;
  268. if (dispc_mgr_go_busy(omap_crtc->channel))
  269. return;
  270. DBG("%s: apply done", omap_crtc->name);
  271. __omap_irq_unregister(dev, &omap_crtc->vblank_irq);
  272. /* wakeup userspace */
  273. omap_crtc_complete_page_flip(&omap_crtc->base);
  274. complete(&omap_crtc->completion);
  275. }
  276. static int omap_crtc_flush(struct drm_crtc *crtc)
  277. {
  278. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  279. DBG("%s: GO", omap_crtc->name);
  280. WARN_ON(omap_crtc->vblank_irq.registered);
  281. if (dispc_mgr_is_enabled(omap_crtc->channel)) {
  282. dispc_mgr_go(omap_crtc->channel);
  283. omap_irq_register(crtc->dev, &omap_crtc->vblank_irq);
  284. WARN_ON(!wait_for_completion_timeout(&omap_crtc->completion,
  285. msecs_to_jiffies(100)));
  286. reinit_completion(&omap_crtc->completion);
  287. }
  288. return 0;
  289. }
  290. /* -----------------------------------------------------------------------------
  291. * CRTC Functions
  292. */
  293. static void omap_crtc_destroy(struct drm_crtc *crtc)
  294. {
  295. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  296. DBG("%s", omap_crtc->name);
  297. WARN_ON(omap_crtc->vblank_irq.registered);
  298. omap_irq_unregister(crtc->dev, &omap_crtc->error_irq);
  299. drm_crtc_cleanup(crtc);
  300. kfree(omap_crtc);
  301. }
  302. static bool omap_crtc_mode_fixup(struct drm_crtc *crtc,
  303. const struct drm_display_mode *mode,
  304. struct drm_display_mode *adjusted_mode)
  305. {
  306. return true;
  307. }
  308. static void omap_crtc_enable(struct drm_crtc *crtc)
  309. {
  310. struct omap_drm_private *priv = crtc->dev->dev_private;
  311. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  312. unsigned int i;
  313. DBG("%s", omap_crtc->name);
  314. /* Enable all planes associated with the CRTC. */
  315. for (i = 0; i < priv->num_planes; i++) {
  316. struct drm_plane *plane = priv->planes[i];
  317. if (plane->crtc == crtc)
  318. WARN_ON(omap_plane_setup(plane));
  319. }
  320. drm_crtc_vblank_on(crtc);
  321. }
  322. static void omap_crtc_disable(struct drm_crtc *crtc)
  323. {
  324. struct omap_drm_private *priv = crtc->dev->dev_private;
  325. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  326. unsigned int i;
  327. DBG("%s", omap_crtc->name);
  328. omap_crtc_wait_page_flip(crtc);
  329. drm_crtc_vblank_off(crtc);
  330. /* Disable all planes associated with the CRTC. */
  331. for (i = 0; i < priv->num_planes; i++) {
  332. struct drm_plane *plane = priv->planes[i];
  333. if (plane->crtc == crtc)
  334. WARN_ON(omap_plane_setup(plane));
  335. }
  336. }
  337. static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
  338. {
  339. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  340. struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  341. DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
  342. omap_crtc->name, mode->base.id, mode->name,
  343. mode->vrefresh, mode->clock,
  344. mode->hdisplay, mode->hsync_start, mode->hsync_end, mode->htotal,
  345. mode->vdisplay, mode->vsync_start, mode->vsync_end, mode->vtotal,
  346. mode->type, mode->flags);
  347. copy_timings_drm_to_omap(&omap_crtc->timings, mode);
  348. }
  349. static void omap_crtc_atomic_begin(struct drm_crtc *crtc)
  350. {
  351. struct drm_pending_vblank_event *event = crtc->state->event;
  352. struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
  353. struct drm_device *dev = crtc->dev;
  354. unsigned long flags;
  355. if (event) {
  356. WARN_ON(omap_crtc->event);
  357. WARN_ON(drm_crtc_vblank_get(crtc) != 0);
  358. spin_lock_irqsave(&dev->event_lock, flags);
  359. omap_crtc->event = event;
  360. spin_unlock_irqrestore(&dev->event_lock, flags);
  361. }
  362. }
  363. static void omap_crtc_atomic_flush(struct drm_crtc *crtc)
  364. {
  365. omap_crtc_flush(crtc);
  366. crtc->invert_dimensions = !!(crtc->primary->state->rotation &
  367. (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270)));
  368. }
  369. static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
  370. struct drm_crtc_state *state,
  371. struct drm_property *property,
  372. uint64_t val)
  373. {
  374. struct drm_plane_state *plane_state;
  375. struct drm_plane *plane = crtc->primary;
  376. /*
  377. * Delegate property set to the primary plane. Get the plane state and
  378. * set the property directly.
  379. */
  380. plane_state = drm_atomic_get_plane_state(state->state, plane);
  381. if (!plane_state)
  382. return -EINVAL;
  383. return drm_atomic_plane_set_property(plane, plane_state, property, val);
  384. }
  385. static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
  386. const struct drm_crtc_state *state,
  387. struct drm_property *property,
  388. uint64_t *val)
  389. {
  390. /*
  391. * Delegate property get to the primary plane. The
  392. * drm_atomic_plane_get_property() function isn't exported, but can be
  393. * called through drm_object_property_get_value() as that will call
  394. * drm_atomic_get_property() for atomic drivers.
  395. */
  396. return drm_object_property_get_value(&crtc->primary->base, property,
  397. val);
  398. }
  399. static const struct drm_crtc_funcs omap_crtc_funcs = {
  400. .reset = drm_atomic_helper_crtc_reset,
  401. .set_config = drm_atomic_helper_set_config,
  402. .destroy = omap_crtc_destroy,
  403. .page_flip = drm_atomic_helper_page_flip,
  404. .set_property = drm_atomic_helper_crtc_set_property,
  405. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  406. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  407. .atomic_set_property = omap_crtc_atomic_set_property,
  408. .atomic_get_property = omap_crtc_atomic_get_property,
  409. };
  410. static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
  411. .mode_fixup = omap_crtc_mode_fixup,
  412. .mode_set_nofb = omap_crtc_mode_set_nofb,
  413. .disable = omap_crtc_disable,
  414. .enable = omap_crtc_enable,
  415. .atomic_begin = omap_crtc_atomic_begin,
  416. .atomic_flush = omap_crtc_atomic_flush,
  417. };
  418. /* -----------------------------------------------------------------------------
  419. * Init and Cleanup
  420. */
  421. static const char *channel_names[] = {
  422. [OMAP_DSS_CHANNEL_LCD] = "lcd",
  423. [OMAP_DSS_CHANNEL_DIGIT] = "tv",
  424. [OMAP_DSS_CHANNEL_LCD2] = "lcd2",
  425. [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
  426. };
  427. void omap_crtc_pre_init(void)
  428. {
  429. dss_install_mgr_ops(&mgr_ops);
  430. }
  431. void omap_crtc_pre_uninit(void)
  432. {
  433. dss_uninstall_mgr_ops();
  434. }
  435. /* initialize crtc */
  436. struct drm_crtc *omap_crtc_init(struct drm_device *dev,
  437. struct drm_plane *plane, enum omap_channel channel, int id)
  438. {
  439. struct drm_crtc *crtc = NULL;
  440. struct omap_crtc *omap_crtc;
  441. int ret;
  442. DBG("%s", channel_names[channel]);
  443. omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
  444. if (!omap_crtc)
  445. return NULL;
  446. crtc = &omap_crtc->base;
  447. init_waitqueue_head(&omap_crtc->flip_wait);
  448. init_completion(&omap_crtc->completion);
  449. omap_crtc->channel = channel;
  450. omap_crtc->name = channel_names[channel];
  451. omap_crtc->vblank_irq.irqmask = pipe2vbl(crtc);
  452. omap_crtc->vblank_irq.irq = omap_crtc_vblank_irq;
  453. omap_crtc->error_irq.irqmask =
  454. dispc_mgr_get_sync_lost_irq(channel);
  455. omap_crtc->error_irq.irq = omap_crtc_error_irq;
  456. omap_irq_register(dev, &omap_crtc->error_irq);
  457. /* temporary: */
  458. omap_crtc->mgr = omap_dss_get_overlay_manager(channel);
  459. ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
  460. &omap_crtc_funcs);
  461. if (ret < 0) {
  462. kfree(omap_crtc);
  463. return NULL;
  464. }
  465. drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
  466. omap_plane_install_properties(crtc->primary, &crtc->base);
  467. omap_crtcs[channel] = omap_crtc;
  468. return crtc;
  469. }