dce_v10_0.c 117 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <drm/drmP.h>
  24. #include "amdgpu.h"
  25. #include "amdgpu_pm.h"
  26. #include "amdgpu_i2c.h"
  27. #include "vid.h"
  28. #include "atom.h"
  29. #include "amdgpu_atombios.h"
  30. #include "atombios_crtc.h"
  31. #include "atombios_encoders.h"
  32. #include "amdgpu_pll.h"
  33. #include "amdgpu_connectors.h"
  34. #include "dce_v10_0.h"
  35. #include "dce/dce_10_0_d.h"
  36. #include "dce/dce_10_0_sh_mask.h"
  37. #include "dce/dce_10_0_enum.h"
  38. #include "oss/oss_3_0_d.h"
  39. #include "oss/oss_3_0_sh_mask.h"
  40. #include "gmc/gmc_8_1_d.h"
  41. #include "gmc/gmc_8_1_sh_mask.h"
  42. static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
  43. static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
  44. static const u32 crtc_offsets[] =
  45. {
  46. CRTC0_REGISTER_OFFSET,
  47. CRTC1_REGISTER_OFFSET,
  48. CRTC2_REGISTER_OFFSET,
  49. CRTC3_REGISTER_OFFSET,
  50. CRTC4_REGISTER_OFFSET,
  51. CRTC5_REGISTER_OFFSET,
  52. CRTC6_REGISTER_OFFSET
  53. };
  54. static const u32 hpd_offsets[] =
  55. {
  56. HPD0_REGISTER_OFFSET,
  57. HPD1_REGISTER_OFFSET,
  58. HPD2_REGISTER_OFFSET,
  59. HPD3_REGISTER_OFFSET,
  60. HPD4_REGISTER_OFFSET,
  61. HPD5_REGISTER_OFFSET
  62. };
  63. static const uint32_t dig_offsets[] = {
  64. DIG0_REGISTER_OFFSET,
  65. DIG1_REGISTER_OFFSET,
  66. DIG2_REGISTER_OFFSET,
  67. DIG3_REGISTER_OFFSET,
  68. DIG4_REGISTER_OFFSET,
  69. DIG5_REGISTER_OFFSET,
  70. DIG6_REGISTER_OFFSET
  71. };
  72. static const struct {
  73. uint32_t reg;
  74. uint32_t vblank;
  75. uint32_t vline;
  76. uint32_t hpd;
  77. } interrupt_status_offsets[] = { {
  78. .reg = mmDISP_INTERRUPT_STATUS,
  79. .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  80. .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  81. .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  82. }, {
  83. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  84. .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  85. .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  86. .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  87. }, {
  88. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  89. .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  90. .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  91. .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  92. }, {
  93. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
  94. .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
  95. .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
  96. .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
  97. }, {
  98. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
  99. .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
  100. .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
  101. .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
  102. }, {
  103. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
  104. .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
  105. .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
  106. .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
  107. } };
  108. static const u32 golden_settings_tonga_a11[] =
  109. {
  110. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  111. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  112. mmFBC_MISC, 0x1f311fff, 0x12300000,
  113. mmHDMI_CONTROL, 0x31000111, 0x00000011,
  114. };
  115. static const u32 tonga_mgcg_cgcg_init[] =
  116. {
  117. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  118. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  119. };
  120. static const u32 golden_settings_fiji_a10[] =
  121. {
  122. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  123. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  124. mmFBC_MISC, 0x1f311fff, 0x12300000,
  125. mmHDMI_CONTROL, 0x31000111, 0x00000011,
  126. };
  127. static const u32 fiji_mgcg_cgcg_init[] =
  128. {
  129. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  130. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  131. };
  132. static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
  133. {
  134. switch (adev->asic_type) {
  135. case CHIP_FIJI:
  136. amdgpu_program_register_sequence(adev,
  137. fiji_mgcg_cgcg_init,
  138. (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
  139. amdgpu_program_register_sequence(adev,
  140. golden_settings_fiji_a10,
  141. (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
  142. break;
  143. case CHIP_TONGA:
  144. amdgpu_program_register_sequence(adev,
  145. tonga_mgcg_cgcg_init,
  146. (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
  147. amdgpu_program_register_sequence(adev,
  148. golden_settings_tonga_a11,
  149. (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
  150. break;
  151. default:
  152. break;
  153. }
  154. }
  155. static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
  156. u32 block_offset, u32 reg)
  157. {
  158. unsigned long flags;
  159. u32 r;
  160. spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
  161. WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  162. r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
  163. spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
  164. return r;
  165. }
  166. static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
  167. u32 block_offset, u32 reg, u32 v)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
  171. WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  172. WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
  173. spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
  174. }
  175. static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
  176. {
  177. if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) &
  178. CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK)
  179. return true;
  180. else
  181. return false;
  182. }
  183. static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
  184. {
  185. u32 pos1, pos2;
  186. pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
  187. pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
  188. if (pos1 != pos2)
  189. return true;
  190. else
  191. return false;
  192. }
  193. /**
  194. * dce_v10_0_vblank_wait - vblank wait asic callback.
  195. *
  196. * @adev: amdgpu_device pointer
  197. * @crtc: crtc to wait for vblank on
  198. *
  199. * Wait for vblank on the requested crtc (evergreen+).
  200. */
  201. static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc)
  202. {
  203. unsigned i = 100;
  204. if (crtc >= adev->mode_info.num_crtc)
  205. return;
  206. if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
  207. return;
  208. /* depending on when we hit vblank, we may be close to active; if so,
  209. * wait for another frame.
  210. */
  211. while (dce_v10_0_is_in_vblank(adev, crtc)) {
  212. if (i++ == 100) {
  213. i = 0;
  214. if (!dce_v10_0_is_counter_moving(adev, crtc))
  215. break;
  216. }
  217. }
  218. while (!dce_v10_0_is_in_vblank(adev, crtc)) {
  219. if (i++ == 100) {
  220. i = 0;
  221. if (!dce_v10_0_is_counter_moving(adev, crtc))
  222. break;
  223. }
  224. }
  225. }
  226. static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  227. {
  228. if (crtc >= adev->mode_info.num_crtc)
  229. return 0;
  230. else
  231. return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
  232. }
  233. static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
  234. {
  235. unsigned i;
  236. /* Enable pflip interrupts */
  237. for (i = 0; i < adev->mode_info.num_crtc; i++)
  238. amdgpu_irq_get(adev, &adev->pageflip_irq, i);
  239. }
  240. static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  241. {
  242. unsigned i;
  243. /* Disable pflip interrupts */
  244. for (i = 0; i < adev->mode_info.num_crtc; i++)
  245. amdgpu_irq_put(adev, &adev->pageflip_irq, i);
  246. }
  247. /**
  248. * dce_v10_0_page_flip - pageflip callback.
  249. *
  250. * @adev: amdgpu_device pointer
  251. * @crtc_id: crtc to cleanup pageflip on
  252. * @crtc_base: new address of the crtc (GPU MC address)
  253. *
  254. * Triggers the actual pageflip by updating the primary
  255. * surface base address.
  256. */
  257. static void dce_v10_0_page_flip(struct amdgpu_device *adev,
  258. int crtc_id, u64 crtc_base, bool async)
  259. {
  260. struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
  261. u32 tmp;
  262. /* flip at hsync for async, default is vsync */
  263. tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
  264. tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
  265. GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
  266. WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  267. /* update the primary scanout address */
  268. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  269. upper_32_bits(crtc_base));
  270. /* writing to the low address triggers the update */
  271. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  272. lower_32_bits(crtc_base));
  273. /* post the write */
  274. RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
  275. }
  276. static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  277. u32 *vbl, u32 *position)
  278. {
  279. if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
  280. return -EINVAL;
  281. *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
  282. *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
  283. return 0;
  284. }
  285. /**
  286. * dce_v10_0_hpd_sense - hpd sense callback.
  287. *
  288. * @adev: amdgpu_device pointer
  289. * @hpd: hpd (hotplug detect) pin
  290. *
  291. * Checks if a digital monitor is connected (evergreen+).
  292. * Returns true if connected, false if not connected.
  293. */
  294. static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
  295. enum amdgpu_hpd_id hpd)
  296. {
  297. bool connected = false;
  298. if (hpd >= adev->mode_info.num_hpd)
  299. return connected;
  300. if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
  301. DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
  302. connected = true;
  303. return connected;
  304. }
  305. /**
  306. * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
  307. *
  308. * @adev: amdgpu_device pointer
  309. * @hpd: hpd (hotplug detect) pin
  310. *
  311. * Set the polarity of the hpd pin (evergreen+).
  312. */
  313. static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
  314. enum amdgpu_hpd_id hpd)
  315. {
  316. u32 tmp;
  317. bool connected = dce_v10_0_hpd_sense(adev, hpd);
  318. if (hpd >= adev->mode_info.num_hpd)
  319. return;
  320. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  321. if (connected)
  322. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
  323. else
  324. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
  325. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  326. }
  327. /**
  328. * dce_v10_0_hpd_init - hpd setup callback.
  329. *
  330. * @adev: amdgpu_device pointer
  331. *
  332. * Setup the hpd pins used by the card (evergreen+).
  333. * Enable the pin, set the polarity, and enable the hpd interrupts.
  334. */
  335. static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
  336. {
  337. struct drm_device *dev = adev->ddev;
  338. struct drm_connector *connector;
  339. u32 tmp;
  340. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  341. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  342. if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
  343. continue;
  344. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
  345. connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
  346. /* don't try to enable hpd on eDP or LVDS avoid breaking the
  347. * aux dp channel on imac and help (but not completely fix)
  348. * https://bugzilla.redhat.com/show_bug.cgi?id=726143
  349. * also avoid interrupt storms during dpms.
  350. */
  351. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  352. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
  353. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  354. continue;
  355. }
  356. tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  357. tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
  358. WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  359. tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  360. tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
  361. DC_HPD_CONNECT_INT_DELAY,
  362. AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
  363. tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
  364. DC_HPD_DISCONNECT_INT_DELAY,
  365. AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
  366. WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  367. dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  368. amdgpu_irq_get(adev, &adev->hpd_irq,
  369. amdgpu_connector->hpd.hpd);
  370. }
  371. }
  372. /**
  373. * dce_v10_0_hpd_fini - hpd tear down callback.
  374. *
  375. * @adev: amdgpu_device pointer
  376. *
  377. * Tear down the hpd pins used by the card (evergreen+).
  378. * Disable the hpd interrupts.
  379. */
  380. static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
  381. {
  382. struct drm_device *dev = adev->ddev;
  383. struct drm_connector *connector;
  384. u32 tmp;
  385. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  386. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  387. if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
  388. continue;
  389. tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  390. tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
  391. WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  392. amdgpu_irq_put(adev, &adev->hpd_irq,
  393. amdgpu_connector->hpd.hpd);
  394. }
  395. }
  396. static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
  397. {
  398. return mmDC_GPIO_HPD_A;
  399. }
  400. static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
  401. {
  402. u32 crtc_hung = 0;
  403. u32 crtc_status[6];
  404. u32 i, j, tmp;
  405. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  406. tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
  407. if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
  408. crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
  409. crtc_hung |= (1 << i);
  410. }
  411. }
  412. for (j = 0; j < 10; j++) {
  413. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  414. if (crtc_hung & (1 << i)) {
  415. tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
  416. if (tmp != crtc_status[i])
  417. crtc_hung &= ~(1 << i);
  418. }
  419. }
  420. if (crtc_hung == 0)
  421. return false;
  422. udelay(100);
  423. }
  424. return true;
  425. }
  426. static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev,
  427. struct amdgpu_mode_mc_save *save)
  428. {
  429. u32 crtc_enabled, tmp;
  430. int i;
  431. save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
  432. save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
  433. /* disable VGA render */
  434. tmp = RREG32(mmVGA_RENDER_CONTROL);
  435. tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
  436. WREG32(mmVGA_RENDER_CONTROL, tmp);
  437. /* blank the display controllers */
  438. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  439. crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
  440. CRTC_CONTROL, CRTC_MASTER_EN);
  441. if (crtc_enabled) {
  442. #if 0
  443. u32 frame_count;
  444. int j;
  445. save->crtc_enabled[i] = true;
  446. tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
  447. if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) {
  448. amdgpu_display_vblank_wait(adev, i);
  449. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  450. tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1);
  451. WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
  452. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  453. }
  454. /* wait for the next frame */
  455. frame_count = amdgpu_display_vblank_get_counter(adev, i);
  456. for (j = 0; j < adev->usec_timeout; j++) {
  457. if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
  458. break;
  459. udelay(1);
  460. }
  461. tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
  462. if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) {
  463. tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
  464. WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
  465. }
  466. tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
  467. if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) {
  468. tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1);
  469. WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
  470. }
  471. #else
  472. /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
  473. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  474. tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
  475. tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
  476. WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
  477. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  478. save->crtc_enabled[i] = false;
  479. /* ***** */
  480. #endif
  481. } else {
  482. save->crtc_enabled[i] = false;
  483. }
  484. }
  485. }
  486. static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev,
  487. struct amdgpu_mode_mc_save *save)
  488. {
  489. u32 tmp, frame_count;
  490. int i, j;
  491. /* update crtc base addresses */
  492. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  493. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
  494. upper_32_bits(adev->mc.vram_start));
  495. WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
  496. upper_32_bits(adev->mc.vram_start));
  497. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
  498. (u32)adev->mc.vram_start);
  499. WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
  500. (u32)adev->mc.vram_start);
  501. if (save->crtc_enabled[i]) {
  502. tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
  503. if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) {
  504. tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0);
  505. WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
  506. }
  507. tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
  508. if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) {
  509. tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
  510. WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
  511. }
  512. tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
  513. if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) {
  514. tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0);
  515. WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
  516. }
  517. for (j = 0; j < adev->usec_timeout; j++) {
  518. tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
  519. if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0)
  520. break;
  521. udelay(1);
  522. }
  523. tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
  524. tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0);
  525. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  526. WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
  527. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  528. /* wait for the next frame */
  529. frame_count = amdgpu_display_vblank_get_counter(adev, i);
  530. for (j = 0; j < adev->usec_timeout; j++) {
  531. if (amdgpu_display_vblank_get_counter(adev, i) != frame_count)
  532. break;
  533. udelay(1);
  534. }
  535. }
  536. }
  537. WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
  538. WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start));
  539. /* Unlock vga access */
  540. WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
  541. mdelay(1);
  542. WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
  543. }
  544. static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
  545. bool render)
  546. {
  547. u32 tmp;
  548. /* Lockout access through VGA aperture*/
  549. tmp = RREG32(mmVGA_HDP_CONTROL);
  550. if (render)
  551. tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
  552. else
  553. tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
  554. WREG32(mmVGA_HDP_CONTROL, tmp);
  555. /* disable VGA render */
  556. tmp = RREG32(mmVGA_RENDER_CONTROL);
  557. if (render)
  558. tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
  559. else
  560. tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
  561. WREG32(mmVGA_RENDER_CONTROL, tmp);
  562. }
  563. static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
  564. {
  565. int num_crtc = 0;
  566. switch (adev->asic_type) {
  567. case CHIP_FIJI:
  568. case CHIP_TONGA:
  569. num_crtc = 6;
  570. break;
  571. default:
  572. num_crtc = 0;
  573. }
  574. return num_crtc;
  575. }
  576. void dce_v10_0_disable_dce(struct amdgpu_device *adev)
  577. {
  578. /*Disable VGA render and enabled crtc, if has DCE engine*/
  579. if (amdgpu_atombios_has_dce_engine_info(adev)) {
  580. u32 tmp;
  581. int crtc_enabled, i;
  582. dce_v10_0_set_vga_render_state(adev, false);
  583. /*Disable crtc*/
  584. for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
  585. crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
  586. CRTC_CONTROL, CRTC_MASTER_EN);
  587. if (crtc_enabled) {
  588. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  589. tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
  590. tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
  591. WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
  592. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  593. }
  594. }
  595. }
  596. }
  597. static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
  598. {
  599. struct drm_device *dev = encoder->dev;
  600. struct amdgpu_device *adev = dev->dev_private;
  601. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  602. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
  603. struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
  604. int bpc = 0;
  605. u32 tmp = 0;
  606. enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
  607. if (connector) {
  608. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  609. bpc = amdgpu_connector_get_monitor_bpc(connector);
  610. dither = amdgpu_connector->dither;
  611. }
  612. /* LVDS/eDP FMT is set up by atom */
  613. if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  614. return;
  615. /* not needed for analog */
  616. if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
  617. (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
  618. return;
  619. if (bpc == 0)
  620. return;
  621. switch (bpc) {
  622. case 6:
  623. if (dither == AMDGPU_FMT_DITHER_ENABLE) {
  624. /* XXX sort out optimal dither settings */
  625. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
  626. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
  627. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
  628. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
  629. } else {
  630. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
  631. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
  632. }
  633. break;
  634. case 8:
  635. if (dither == AMDGPU_FMT_DITHER_ENABLE) {
  636. /* XXX sort out optimal dither settings */
  637. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
  638. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
  639. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
  640. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
  641. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
  642. } else {
  643. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
  644. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
  645. }
  646. break;
  647. case 10:
  648. if (dither == AMDGPU_FMT_DITHER_ENABLE) {
  649. /* XXX sort out optimal dither settings */
  650. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
  651. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
  652. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
  653. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
  654. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
  655. } else {
  656. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
  657. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
  658. }
  659. break;
  660. default:
  661. /* not needed */
  662. break;
  663. }
  664. WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  665. }
  666. /* display watermark setup */
  667. /**
  668. * dce_v10_0_line_buffer_adjust - Set up the line buffer
  669. *
  670. * @adev: amdgpu_device pointer
  671. * @amdgpu_crtc: the selected display controller
  672. * @mode: the current display mode on the selected display
  673. * controller
  674. *
  675. * Setup up the line buffer allocation for
  676. * the selected display controller (CIK).
  677. * Returns the line buffer size in pixels.
  678. */
  679. static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
  680. struct amdgpu_crtc *amdgpu_crtc,
  681. struct drm_display_mode *mode)
  682. {
  683. u32 tmp, buffer_alloc, i, mem_cfg;
  684. u32 pipe_offset = amdgpu_crtc->crtc_id;
  685. /*
  686. * Line Buffer Setup
  687. * There are 6 line buffers, one for each display controllers.
  688. * There are 3 partitions per LB. Select the number of partitions
  689. * to enable based on the display width. For display widths larger
  690. * than 4096, you need use to use 2 display controllers and combine
  691. * them using the stereo blender.
  692. */
  693. if (amdgpu_crtc->base.enabled && mode) {
  694. if (mode->crtc_hdisplay < 1920) {
  695. mem_cfg = 1;
  696. buffer_alloc = 2;
  697. } else if (mode->crtc_hdisplay < 2560) {
  698. mem_cfg = 2;
  699. buffer_alloc = 2;
  700. } else if (mode->crtc_hdisplay < 4096) {
  701. mem_cfg = 0;
  702. buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
  703. } else {
  704. DRM_DEBUG_KMS("Mode too big for LB!\n");
  705. mem_cfg = 0;
  706. buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
  707. }
  708. } else {
  709. mem_cfg = 1;
  710. buffer_alloc = 0;
  711. }
  712. tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
  713. tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
  714. WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
  715. tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
  716. tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
  717. WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
  718. for (i = 0; i < adev->usec_timeout; i++) {
  719. tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
  720. if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
  721. break;
  722. udelay(1);
  723. }
  724. if (amdgpu_crtc->base.enabled && mode) {
  725. switch (mem_cfg) {
  726. case 0:
  727. default:
  728. return 4096 * 2;
  729. case 1:
  730. return 1920 * 2;
  731. case 2:
  732. return 2560 * 2;
  733. }
  734. }
  735. /* controller not enabled, so no lb used */
  736. return 0;
  737. }
  738. /**
  739. * cik_get_number_of_dram_channels - get the number of dram channels
  740. *
  741. * @adev: amdgpu_device pointer
  742. *
  743. * Look up the number of video ram channels (CIK).
  744. * Used for display watermark bandwidth calculations
  745. * Returns the number of dram channels
  746. */
  747. static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
  748. {
  749. u32 tmp = RREG32(mmMC_SHARED_CHMAP);
  750. switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
  751. case 0:
  752. default:
  753. return 1;
  754. case 1:
  755. return 2;
  756. case 2:
  757. return 4;
  758. case 3:
  759. return 8;
  760. case 4:
  761. return 3;
  762. case 5:
  763. return 6;
  764. case 6:
  765. return 10;
  766. case 7:
  767. return 12;
  768. case 8:
  769. return 16;
  770. }
  771. }
  772. struct dce10_wm_params {
  773. u32 dram_channels; /* number of dram channels */
  774. u32 yclk; /* bandwidth per dram data pin in kHz */
  775. u32 sclk; /* engine clock in kHz */
  776. u32 disp_clk; /* display clock in kHz */
  777. u32 src_width; /* viewport width */
  778. u32 active_time; /* active display time in ns */
  779. u32 blank_time; /* blank time in ns */
  780. bool interlaced; /* mode is interlaced */
  781. fixed20_12 vsc; /* vertical scale ratio */
  782. u32 num_heads; /* number of active crtcs */
  783. u32 bytes_per_pixel; /* bytes per pixel display + overlay */
  784. u32 lb_size; /* line buffer allocated to pipe */
  785. u32 vtaps; /* vertical scaler taps */
  786. };
  787. /**
  788. * dce_v10_0_dram_bandwidth - get the dram bandwidth
  789. *
  790. * @wm: watermark calculation data
  791. *
  792. * Calculate the raw dram bandwidth (CIK).
  793. * Used for display watermark bandwidth calculations
  794. * Returns the dram bandwidth in MBytes/s
  795. */
  796. static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
  797. {
  798. /* Calculate raw DRAM Bandwidth */
  799. fixed20_12 dram_efficiency; /* 0.7 */
  800. fixed20_12 yclk, dram_channels, bandwidth;
  801. fixed20_12 a;
  802. a.full = dfixed_const(1000);
  803. yclk.full = dfixed_const(wm->yclk);
  804. yclk.full = dfixed_div(yclk, a);
  805. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  806. a.full = dfixed_const(10);
  807. dram_efficiency.full = dfixed_const(7);
  808. dram_efficiency.full = dfixed_div(dram_efficiency, a);
  809. bandwidth.full = dfixed_mul(dram_channels, yclk);
  810. bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
  811. return dfixed_trunc(bandwidth);
  812. }
  813. /**
  814. * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
  815. *
  816. * @wm: watermark calculation data
  817. *
  818. * Calculate the dram bandwidth used for display (CIK).
  819. * Used for display watermark bandwidth calculations
  820. * Returns the dram bandwidth for display in MBytes/s
  821. */
  822. static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
  823. {
  824. /* Calculate DRAM Bandwidth and the part allocated to display. */
  825. fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
  826. fixed20_12 yclk, dram_channels, bandwidth;
  827. fixed20_12 a;
  828. a.full = dfixed_const(1000);
  829. yclk.full = dfixed_const(wm->yclk);
  830. yclk.full = dfixed_div(yclk, a);
  831. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  832. a.full = dfixed_const(10);
  833. disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
  834. disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
  835. bandwidth.full = dfixed_mul(dram_channels, yclk);
  836. bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
  837. return dfixed_trunc(bandwidth);
  838. }
  839. /**
  840. * dce_v10_0_data_return_bandwidth - get the data return bandwidth
  841. *
  842. * @wm: watermark calculation data
  843. *
  844. * Calculate the data return bandwidth used for display (CIK).
  845. * Used for display watermark bandwidth calculations
  846. * Returns the data return bandwidth in MBytes/s
  847. */
  848. static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
  849. {
  850. /* Calculate the display Data return Bandwidth */
  851. fixed20_12 return_efficiency; /* 0.8 */
  852. fixed20_12 sclk, bandwidth;
  853. fixed20_12 a;
  854. a.full = dfixed_const(1000);
  855. sclk.full = dfixed_const(wm->sclk);
  856. sclk.full = dfixed_div(sclk, a);
  857. a.full = dfixed_const(10);
  858. return_efficiency.full = dfixed_const(8);
  859. return_efficiency.full = dfixed_div(return_efficiency, a);
  860. a.full = dfixed_const(32);
  861. bandwidth.full = dfixed_mul(a, sclk);
  862. bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
  863. return dfixed_trunc(bandwidth);
  864. }
  865. /**
  866. * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
  867. *
  868. * @wm: watermark calculation data
  869. *
  870. * Calculate the dmif bandwidth used for display (CIK).
  871. * Used for display watermark bandwidth calculations
  872. * Returns the dmif bandwidth in MBytes/s
  873. */
  874. static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
  875. {
  876. /* Calculate the DMIF Request Bandwidth */
  877. fixed20_12 disp_clk_request_efficiency; /* 0.8 */
  878. fixed20_12 disp_clk, bandwidth;
  879. fixed20_12 a, b;
  880. a.full = dfixed_const(1000);
  881. disp_clk.full = dfixed_const(wm->disp_clk);
  882. disp_clk.full = dfixed_div(disp_clk, a);
  883. a.full = dfixed_const(32);
  884. b.full = dfixed_mul(a, disp_clk);
  885. a.full = dfixed_const(10);
  886. disp_clk_request_efficiency.full = dfixed_const(8);
  887. disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
  888. bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
  889. return dfixed_trunc(bandwidth);
  890. }
  891. /**
  892. * dce_v10_0_available_bandwidth - get the min available bandwidth
  893. *
  894. * @wm: watermark calculation data
  895. *
  896. * Calculate the min available bandwidth used for display (CIK).
  897. * Used for display watermark bandwidth calculations
  898. * Returns the min available bandwidth in MBytes/s
  899. */
  900. static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
  901. {
  902. /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
  903. u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
  904. u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
  905. u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
  906. return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
  907. }
  908. /**
  909. * dce_v10_0_average_bandwidth - get the average available bandwidth
  910. *
  911. * @wm: watermark calculation data
  912. *
  913. * Calculate the average available bandwidth used for display (CIK).
  914. * Used for display watermark bandwidth calculations
  915. * Returns the average available bandwidth in MBytes/s
  916. */
  917. static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
  918. {
  919. /* Calculate the display mode Average Bandwidth
  920. * DisplayMode should contain the source and destination dimensions,
  921. * timing, etc.
  922. */
  923. fixed20_12 bpp;
  924. fixed20_12 line_time;
  925. fixed20_12 src_width;
  926. fixed20_12 bandwidth;
  927. fixed20_12 a;
  928. a.full = dfixed_const(1000);
  929. line_time.full = dfixed_const(wm->active_time + wm->blank_time);
  930. line_time.full = dfixed_div(line_time, a);
  931. bpp.full = dfixed_const(wm->bytes_per_pixel);
  932. src_width.full = dfixed_const(wm->src_width);
  933. bandwidth.full = dfixed_mul(src_width, bpp);
  934. bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
  935. bandwidth.full = dfixed_div(bandwidth, line_time);
  936. return dfixed_trunc(bandwidth);
  937. }
  938. /**
  939. * dce_v10_0_latency_watermark - get the latency watermark
  940. *
  941. * @wm: watermark calculation data
  942. *
  943. * Calculate the latency watermark (CIK).
  944. * Used for display watermark bandwidth calculations
  945. * Returns the latency watermark in ns
  946. */
  947. static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
  948. {
  949. /* First calculate the latency in ns */
  950. u32 mc_latency = 2000; /* 2000 ns. */
  951. u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
  952. u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
  953. u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
  954. u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
  955. u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
  956. (wm->num_heads * cursor_line_pair_return_time);
  957. u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
  958. u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
  959. u32 tmp, dmif_size = 12288;
  960. fixed20_12 a, b, c;
  961. if (wm->num_heads == 0)
  962. return 0;
  963. a.full = dfixed_const(2);
  964. b.full = dfixed_const(1);
  965. if ((wm->vsc.full > a.full) ||
  966. ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
  967. (wm->vtaps >= 5) ||
  968. ((wm->vsc.full >= a.full) && wm->interlaced))
  969. max_src_lines_per_dst_line = 4;
  970. else
  971. max_src_lines_per_dst_line = 2;
  972. a.full = dfixed_const(available_bandwidth);
  973. b.full = dfixed_const(wm->num_heads);
  974. a.full = dfixed_div(a, b);
  975. tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
  976. tmp = min(dfixed_trunc(a), tmp);
  977. lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
  978. a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
  979. b.full = dfixed_const(1000);
  980. c.full = dfixed_const(lb_fill_bw);
  981. b.full = dfixed_div(c, b);
  982. a.full = dfixed_div(a, b);
  983. line_fill_time = dfixed_trunc(a);
  984. if (line_fill_time < wm->active_time)
  985. return latency;
  986. else
  987. return latency + (line_fill_time - wm->active_time);
  988. }
  989. /**
  990. * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
  991. * average and available dram bandwidth
  992. *
  993. * @wm: watermark calculation data
  994. *
  995. * Check if the display average bandwidth fits in the display
  996. * dram bandwidth (CIK).
  997. * Used for display watermark bandwidth calculations
  998. * Returns true if the display fits, false if not.
  999. */
  1000. static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
  1001. {
  1002. if (dce_v10_0_average_bandwidth(wm) <=
  1003. (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
  1004. return true;
  1005. else
  1006. return false;
  1007. }
  1008. /**
  1009. * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
  1010. * average and available bandwidth
  1011. *
  1012. * @wm: watermark calculation data
  1013. *
  1014. * Check if the display average bandwidth fits in the display
  1015. * available bandwidth (CIK).
  1016. * Used for display watermark bandwidth calculations
  1017. * Returns true if the display fits, false if not.
  1018. */
  1019. static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
  1020. {
  1021. if (dce_v10_0_average_bandwidth(wm) <=
  1022. (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
  1023. return true;
  1024. else
  1025. return false;
  1026. }
  1027. /**
  1028. * dce_v10_0_check_latency_hiding - check latency hiding
  1029. *
  1030. * @wm: watermark calculation data
  1031. *
  1032. * Check latency hiding (CIK).
  1033. * Used for display watermark bandwidth calculations
  1034. * Returns true if the display fits, false if not.
  1035. */
  1036. static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
  1037. {
  1038. u32 lb_partitions = wm->lb_size / wm->src_width;
  1039. u32 line_time = wm->active_time + wm->blank_time;
  1040. u32 latency_tolerant_lines;
  1041. u32 latency_hiding;
  1042. fixed20_12 a;
  1043. a.full = dfixed_const(1);
  1044. if (wm->vsc.full > a.full)
  1045. latency_tolerant_lines = 1;
  1046. else {
  1047. if (lb_partitions <= (wm->vtaps + 1))
  1048. latency_tolerant_lines = 1;
  1049. else
  1050. latency_tolerant_lines = 2;
  1051. }
  1052. latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
  1053. if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
  1054. return true;
  1055. else
  1056. return false;
  1057. }
  1058. /**
  1059. * dce_v10_0_program_watermarks - program display watermarks
  1060. *
  1061. * @adev: amdgpu_device pointer
  1062. * @amdgpu_crtc: the selected display controller
  1063. * @lb_size: line buffer size
  1064. * @num_heads: number of display controllers in use
  1065. *
  1066. * Calculate and program the display watermarks for the
  1067. * selected display controller (CIK).
  1068. */
  1069. static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
  1070. struct amdgpu_crtc *amdgpu_crtc,
  1071. u32 lb_size, u32 num_heads)
  1072. {
  1073. struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
  1074. struct dce10_wm_params wm_low, wm_high;
  1075. u32 active_time;
  1076. u32 line_time = 0;
  1077. u32 latency_watermark_a = 0, latency_watermark_b = 0;
  1078. u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
  1079. if (amdgpu_crtc->base.enabled && num_heads && mode) {
  1080. active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
  1081. (u32)mode->clock);
  1082. line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
  1083. (u32)mode->clock);
  1084. line_time = min(line_time, (u32)65535);
  1085. /* watermark for high clocks */
  1086. if (adev->pm.dpm_enabled) {
  1087. wm_high.yclk =
  1088. amdgpu_dpm_get_mclk(adev, false) * 10;
  1089. wm_high.sclk =
  1090. amdgpu_dpm_get_sclk(adev, false) * 10;
  1091. } else {
  1092. wm_high.yclk = adev->pm.current_mclk * 10;
  1093. wm_high.sclk = adev->pm.current_sclk * 10;
  1094. }
  1095. wm_high.disp_clk = mode->clock;
  1096. wm_high.src_width = mode->crtc_hdisplay;
  1097. wm_high.active_time = active_time;
  1098. wm_high.blank_time = line_time - wm_high.active_time;
  1099. wm_high.interlaced = false;
  1100. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1101. wm_high.interlaced = true;
  1102. wm_high.vsc = amdgpu_crtc->vsc;
  1103. wm_high.vtaps = 1;
  1104. if (amdgpu_crtc->rmx_type != RMX_OFF)
  1105. wm_high.vtaps = 2;
  1106. wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
  1107. wm_high.lb_size = lb_size;
  1108. wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
  1109. wm_high.num_heads = num_heads;
  1110. /* set for high clocks */
  1111. latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
  1112. /* possibly force display priority to high */
  1113. /* should really do this at mode validation time... */
  1114. if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
  1115. !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
  1116. !dce_v10_0_check_latency_hiding(&wm_high) ||
  1117. (adev->mode_info.disp_priority == 2)) {
  1118. DRM_DEBUG_KMS("force priority to high\n");
  1119. }
  1120. /* watermark for low clocks */
  1121. if (adev->pm.dpm_enabled) {
  1122. wm_low.yclk =
  1123. amdgpu_dpm_get_mclk(adev, true) * 10;
  1124. wm_low.sclk =
  1125. amdgpu_dpm_get_sclk(adev, true) * 10;
  1126. } else {
  1127. wm_low.yclk = adev->pm.current_mclk * 10;
  1128. wm_low.sclk = adev->pm.current_sclk * 10;
  1129. }
  1130. wm_low.disp_clk = mode->clock;
  1131. wm_low.src_width = mode->crtc_hdisplay;
  1132. wm_low.active_time = active_time;
  1133. wm_low.blank_time = line_time - wm_low.active_time;
  1134. wm_low.interlaced = false;
  1135. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1136. wm_low.interlaced = true;
  1137. wm_low.vsc = amdgpu_crtc->vsc;
  1138. wm_low.vtaps = 1;
  1139. if (amdgpu_crtc->rmx_type != RMX_OFF)
  1140. wm_low.vtaps = 2;
  1141. wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
  1142. wm_low.lb_size = lb_size;
  1143. wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
  1144. wm_low.num_heads = num_heads;
  1145. /* set for low clocks */
  1146. latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
  1147. /* possibly force display priority to high */
  1148. /* should really do this at mode validation time... */
  1149. if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
  1150. !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
  1151. !dce_v10_0_check_latency_hiding(&wm_low) ||
  1152. (adev->mode_info.disp_priority == 2)) {
  1153. DRM_DEBUG_KMS("force priority to high\n");
  1154. }
  1155. lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
  1156. }
  1157. /* select wm A */
  1158. wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
  1159. tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
  1160. WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1161. tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
  1162. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
  1163. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
  1164. WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1165. /* select wm B */
  1166. tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
  1167. WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1168. tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
  1169. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
  1170. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
  1171. WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1172. /* restore original selection */
  1173. WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
  1174. /* save values for DPM */
  1175. amdgpu_crtc->line_time = line_time;
  1176. amdgpu_crtc->wm_high = latency_watermark_a;
  1177. amdgpu_crtc->wm_low = latency_watermark_b;
  1178. /* Save number of lines the linebuffer leads before the scanout */
  1179. amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
  1180. }
  1181. /**
  1182. * dce_v10_0_bandwidth_update - program display watermarks
  1183. *
  1184. * @adev: amdgpu_device pointer
  1185. *
  1186. * Calculate and program the display watermarks and line
  1187. * buffer allocation (CIK).
  1188. */
  1189. static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
  1190. {
  1191. struct drm_display_mode *mode = NULL;
  1192. u32 num_heads = 0, lb_size;
  1193. int i;
  1194. amdgpu_update_display_priority(adev);
  1195. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  1196. if (adev->mode_info.crtcs[i]->base.enabled)
  1197. num_heads++;
  1198. }
  1199. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  1200. mode = &adev->mode_info.crtcs[i]->base.mode;
  1201. lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
  1202. dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
  1203. lb_size, num_heads);
  1204. }
  1205. }
  1206. static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
  1207. {
  1208. int i;
  1209. u32 offset, tmp;
  1210. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  1211. offset = adev->mode_info.audio.pin[i].offset;
  1212. tmp = RREG32_AUDIO_ENDPT(offset,
  1213. ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
  1214. if (((tmp &
  1215. AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
  1216. AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
  1217. adev->mode_info.audio.pin[i].connected = false;
  1218. else
  1219. adev->mode_info.audio.pin[i].connected = true;
  1220. }
  1221. }
  1222. static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
  1223. {
  1224. int i;
  1225. dce_v10_0_audio_get_connected_pins(adev);
  1226. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  1227. if (adev->mode_info.audio.pin[i].connected)
  1228. return &adev->mode_info.audio.pin[i];
  1229. }
  1230. DRM_ERROR("No connected audio pins found!\n");
  1231. return NULL;
  1232. }
  1233. static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
  1234. {
  1235. struct amdgpu_device *adev = encoder->dev->dev_private;
  1236. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1237. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1238. u32 tmp;
  1239. if (!dig || !dig->afmt || !dig->afmt->pin)
  1240. return;
  1241. tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
  1242. tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
  1243. WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
  1244. }
  1245. static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
  1246. struct drm_display_mode *mode)
  1247. {
  1248. struct amdgpu_device *adev = encoder->dev->dev_private;
  1249. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1250. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1251. struct drm_connector *connector;
  1252. struct amdgpu_connector *amdgpu_connector = NULL;
  1253. u32 tmp;
  1254. int interlace = 0;
  1255. if (!dig || !dig->afmt || !dig->afmt->pin)
  1256. return;
  1257. list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  1258. if (connector->encoder == encoder) {
  1259. amdgpu_connector = to_amdgpu_connector(connector);
  1260. break;
  1261. }
  1262. }
  1263. if (!amdgpu_connector) {
  1264. DRM_ERROR("Couldn't find encoder's connector\n");
  1265. return;
  1266. }
  1267. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1268. interlace = 1;
  1269. if (connector->latency_present[interlace]) {
  1270. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1271. VIDEO_LIPSYNC, connector->video_latency[interlace]);
  1272. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1273. AUDIO_LIPSYNC, connector->audio_latency[interlace]);
  1274. } else {
  1275. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1276. VIDEO_LIPSYNC, 0);
  1277. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1278. AUDIO_LIPSYNC, 0);
  1279. }
  1280. WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
  1281. ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
  1282. }
  1283. static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
  1284. {
  1285. struct amdgpu_device *adev = encoder->dev->dev_private;
  1286. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1287. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1288. struct drm_connector *connector;
  1289. struct amdgpu_connector *amdgpu_connector = NULL;
  1290. u32 tmp;
  1291. u8 *sadb = NULL;
  1292. int sad_count;
  1293. if (!dig || !dig->afmt || !dig->afmt->pin)
  1294. return;
  1295. list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  1296. if (connector->encoder == encoder) {
  1297. amdgpu_connector = to_amdgpu_connector(connector);
  1298. break;
  1299. }
  1300. }
  1301. if (!amdgpu_connector) {
  1302. DRM_ERROR("Couldn't find encoder's connector\n");
  1303. return;
  1304. }
  1305. sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
  1306. if (sad_count < 0) {
  1307. DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
  1308. sad_count = 0;
  1309. }
  1310. /* program the speaker allocation */
  1311. tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
  1312. ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
  1313. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1314. DP_CONNECTION, 0);
  1315. /* set HDMI mode */
  1316. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1317. HDMI_CONNECTION, 1);
  1318. if (sad_count)
  1319. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1320. SPEAKER_ALLOCATION, sadb[0]);
  1321. else
  1322. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1323. SPEAKER_ALLOCATION, 5); /* stereo */
  1324. WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
  1325. ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
  1326. kfree(sadb);
  1327. }
  1328. static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
  1329. {
  1330. struct amdgpu_device *adev = encoder->dev->dev_private;
  1331. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1332. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1333. struct drm_connector *connector;
  1334. struct amdgpu_connector *amdgpu_connector = NULL;
  1335. struct cea_sad *sads;
  1336. int i, sad_count;
  1337. static const u16 eld_reg_to_type[][2] = {
  1338. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
  1339. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
  1340. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
  1341. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
  1342. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
  1343. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
  1344. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
  1345. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
  1346. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
  1347. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
  1348. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
  1349. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
  1350. };
  1351. if (!dig || !dig->afmt || !dig->afmt->pin)
  1352. return;
  1353. list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  1354. if (connector->encoder == encoder) {
  1355. amdgpu_connector = to_amdgpu_connector(connector);
  1356. break;
  1357. }
  1358. }
  1359. if (!amdgpu_connector) {
  1360. DRM_ERROR("Couldn't find encoder's connector\n");
  1361. return;
  1362. }
  1363. sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
  1364. if (sad_count <= 0) {
  1365. DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
  1366. return;
  1367. }
  1368. BUG_ON(!sads);
  1369. for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
  1370. u32 tmp = 0;
  1371. u8 stereo_freqs = 0;
  1372. int max_channels = -1;
  1373. int j;
  1374. for (j = 0; j < sad_count; j++) {
  1375. struct cea_sad *sad = &sads[j];
  1376. if (sad->format == eld_reg_to_type[i][1]) {
  1377. if (sad->channels > max_channels) {
  1378. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1379. MAX_CHANNELS, sad->channels);
  1380. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1381. DESCRIPTOR_BYTE_2, sad->byte2);
  1382. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1383. SUPPORTED_FREQUENCIES, sad->freq);
  1384. max_channels = sad->channels;
  1385. }
  1386. if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
  1387. stereo_freqs |= sad->freq;
  1388. else
  1389. break;
  1390. }
  1391. }
  1392. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1393. SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
  1394. WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
  1395. }
  1396. kfree(sads);
  1397. }
  1398. static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
  1399. struct amdgpu_audio_pin *pin,
  1400. bool enable)
  1401. {
  1402. if (!pin)
  1403. return;
  1404. WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
  1405. enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
  1406. }
  1407. static const u32 pin_offsets[] =
  1408. {
  1409. AUD0_REGISTER_OFFSET,
  1410. AUD1_REGISTER_OFFSET,
  1411. AUD2_REGISTER_OFFSET,
  1412. AUD3_REGISTER_OFFSET,
  1413. AUD4_REGISTER_OFFSET,
  1414. AUD5_REGISTER_OFFSET,
  1415. AUD6_REGISTER_OFFSET,
  1416. };
  1417. static int dce_v10_0_audio_init(struct amdgpu_device *adev)
  1418. {
  1419. int i;
  1420. if (!amdgpu_audio)
  1421. return 0;
  1422. adev->mode_info.audio.enabled = true;
  1423. adev->mode_info.audio.num_pins = 7;
  1424. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  1425. adev->mode_info.audio.pin[i].channels = -1;
  1426. adev->mode_info.audio.pin[i].rate = -1;
  1427. adev->mode_info.audio.pin[i].bits_per_sample = -1;
  1428. adev->mode_info.audio.pin[i].status_bits = 0;
  1429. adev->mode_info.audio.pin[i].category_code = 0;
  1430. adev->mode_info.audio.pin[i].connected = false;
  1431. adev->mode_info.audio.pin[i].offset = pin_offsets[i];
  1432. adev->mode_info.audio.pin[i].id = i;
  1433. /* disable audio. it will be set up later */
  1434. /* XXX remove once we switch to ip funcs */
  1435. dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  1436. }
  1437. return 0;
  1438. }
  1439. static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
  1440. {
  1441. int i;
  1442. if (!amdgpu_audio)
  1443. return;
  1444. if (!adev->mode_info.audio.enabled)
  1445. return;
  1446. for (i = 0; i < adev->mode_info.audio.num_pins; i++)
  1447. dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  1448. adev->mode_info.audio.enabled = false;
  1449. }
  1450. /*
  1451. * update the N and CTS parameters for a given pixel clock rate
  1452. */
  1453. static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  1454. {
  1455. struct drm_device *dev = encoder->dev;
  1456. struct amdgpu_device *adev = dev->dev_private;
  1457. struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
  1458. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1459. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1460. u32 tmp;
  1461. tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
  1462. tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
  1463. WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
  1464. tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
  1465. tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
  1466. WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
  1467. tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
  1468. tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
  1469. WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
  1470. tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
  1471. tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
  1472. WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
  1473. tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
  1474. tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
  1475. WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
  1476. tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
  1477. tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
  1478. WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
  1479. }
  1480. /*
  1481. * build a HDMI Video Info Frame
  1482. */
  1483. static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
  1484. void *buffer, size_t size)
  1485. {
  1486. struct drm_device *dev = encoder->dev;
  1487. struct amdgpu_device *adev = dev->dev_private;
  1488. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1489. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1490. uint8_t *frame = buffer + 3;
  1491. uint8_t *header = buffer;
  1492. WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
  1493. frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  1494. WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
  1495. frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
  1496. WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
  1497. frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
  1498. WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
  1499. frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
  1500. }
  1501. static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  1502. {
  1503. struct drm_device *dev = encoder->dev;
  1504. struct amdgpu_device *adev = dev->dev_private;
  1505. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1506. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1507. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
  1508. u32 dto_phase = 24 * 1000;
  1509. u32 dto_modulo = clock;
  1510. u32 tmp;
  1511. if (!dig || !dig->afmt)
  1512. return;
  1513. /* XXX two dtos; generally use dto0 for hdmi */
  1514. /* Express [24MHz / target pixel clock] as an exact rational
  1515. * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
  1516. * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
  1517. */
  1518. tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
  1519. tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
  1520. amdgpu_crtc->crtc_id);
  1521. WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
  1522. WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
  1523. WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
  1524. }
  1525. /*
  1526. * update the info frames with the data from the current display mode
  1527. */
  1528. static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
  1529. struct drm_display_mode *mode)
  1530. {
  1531. struct drm_device *dev = encoder->dev;
  1532. struct amdgpu_device *adev = dev->dev_private;
  1533. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1534. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1535. struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
  1536. u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
  1537. struct hdmi_avi_infoframe frame;
  1538. ssize_t err;
  1539. u32 tmp;
  1540. int bpc = 8;
  1541. if (!dig || !dig->afmt)
  1542. return;
  1543. /* Silent, r600_hdmi_enable will raise WARN for us */
  1544. if (!dig->afmt->enabled)
  1545. return;
  1546. /* hdmi deep color mode general control packets setup, if bpc > 8 */
  1547. if (encoder->crtc) {
  1548. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
  1549. bpc = amdgpu_crtc->bpc;
  1550. }
  1551. /* disable audio prior to setting up hw */
  1552. dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
  1553. dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
  1554. dce_v10_0_audio_set_dto(encoder, mode->clock);
  1555. tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
  1556. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
  1557. WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
  1558. WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
  1559. tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
  1560. switch (bpc) {
  1561. case 0:
  1562. case 6:
  1563. case 8:
  1564. case 16:
  1565. default:
  1566. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
  1567. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
  1568. DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
  1569. connector->name, bpc);
  1570. break;
  1571. case 10:
  1572. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
  1573. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
  1574. DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
  1575. connector->name);
  1576. break;
  1577. case 12:
  1578. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
  1579. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
  1580. DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
  1581. connector->name);
  1582. break;
  1583. }
  1584. WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
  1585. tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
  1586. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
  1587. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
  1588. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
  1589. WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
  1590. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
  1591. /* enable audio info frames (frames won't be set until audio is enabled) */
  1592. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
  1593. /* required for audio info values to be updated */
  1594. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
  1595. WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
  1596. tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
  1597. /* required for audio info values to be updated */
  1598. tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
  1599. WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
  1600. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
  1601. /* anything other than 0 */
  1602. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
  1603. WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
  1604. WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
  1605. tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
  1606. /* set the default audio delay */
  1607. tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
  1608. /* should be suffient for all audio modes and small enough for all hblanks */
  1609. tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
  1610. WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
  1611. tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
  1612. /* allow 60958 channel status fields to be updated */
  1613. tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
  1614. WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
  1615. tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
  1616. if (bpc > 8)
  1617. /* clear SW CTS value */
  1618. tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
  1619. else
  1620. /* select SW CTS value */
  1621. tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
  1622. /* allow hw to sent ACR packets when required */
  1623. tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
  1624. WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
  1625. dce_v10_0_afmt_update_ACR(encoder, mode->clock);
  1626. tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
  1627. tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
  1628. WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
  1629. tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
  1630. tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
  1631. WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
  1632. tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
  1633. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
  1634. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
  1635. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
  1636. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
  1637. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
  1638. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
  1639. WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
  1640. dce_v10_0_audio_write_speaker_allocation(encoder);
  1641. WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
  1642. (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
  1643. dce_v10_0_afmt_audio_select_pin(encoder);
  1644. dce_v10_0_audio_write_sad_regs(encoder);
  1645. dce_v10_0_audio_write_latency_fields(encoder, mode);
  1646. err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
  1647. if (err < 0) {
  1648. DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
  1649. return;
  1650. }
  1651. err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  1652. if (err < 0) {
  1653. DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
  1654. return;
  1655. }
  1656. dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
  1657. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
  1658. /* enable AVI info frames */
  1659. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
  1660. /* required for audio info values to be updated */
  1661. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
  1662. WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
  1663. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
  1664. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
  1665. WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
  1666. tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
  1667. /* send audio packets */
  1668. tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
  1669. WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
  1670. WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
  1671. WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
  1672. WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
  1673. WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
  1674. /* enable audio after to setting up hw */
  1675. dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
  1676. }
  1677. static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
  1678. {
  1679. struct drm_device *dev = encoder->dev;
  1680. struct amdgpu_device *adev = dev->dev_private;
  1681. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1682. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1683. if (!dig || !dig->afmt)
  1684. return;
  1685. /* Silent, r600_hdmi_enable will raise WARN for us */
  1686. if (enable && dig->afmt->enabled)
  1687. return;
  1688. if (!enable && !dig->afmt->enabled)
  1689. return;
  1690. if (!enable && dig->afmt->pin) {
  1691. dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
  1692. dig->afmt->pin = NULL;
  1693. }
  1694. dig->afmt->enabled = enable;
  1695. DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
  1696. enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
  1697. }
  1698. static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
  1699. {
  1700. int i;
  1701. for (i = 0; i < adev->mode_info.num_dig; i++)
  1702. adev->mode_info.afmt[i] = NULL;
  1703. /* DCE10 has audio blocks tied to DIG encoders */
  1704. for (i = 0; i < adev->mode_info.num_dig; i++) {
  1705. adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
  1706. if (adev->mode_info.afmt[i]) {
  1707. adev->mode_info.afmt[i]->offset = dig_offsets[i];
  1708. adev->mode_info.afmt[i]->id = i;
  1709. } else {
  1710. int j;
  1711. for (j = 0; j < i; j++) {
  1712. kfree(adev->mode_info.afmt[j]);
  1713. adev->mode_info.afmt[j] = NULL;
  1714. }
  1715. return -ENOMEM;
  1716. }
  1717. }
  1718. return 0;
  1719. }
  1720. static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
  1721. {
  1722. int i;
  1723. for (i = 0; i < adev->mode_info.num_dig; i++) {
  1724. kfree(adev->mode_info.afmt[i]);
  1725. adev->mode_info.afmt[i] = NULL;
  1726. }
  1727. }
  1728. static const u32 vga_control_regs[6] =
  1729. {
  1730. mmD1VGA_CONTROL,
  1731. mmD2VGA_CONTROL,
  1732. mmD3VGA_CONTROL,
  1733. mmD4VGA_CONTROL,
  1734. mmD5VGA_CONTROL,
  1735. mmD6VGA_CONTROL,
  1736. };
  1737. static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
  1738. {
  1739. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1740. struct drm_device *dev = crtc->dev;
  1741. struct amdgpu_device *adev = dev->dev_private;
  1742. u32 vga_control;
  1743. vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
  1744. if (enable)
  1745. WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
  1746. else
  1747. WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
  1748. }
  1749. static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
  1750. {
  1751. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1752. struct drm_device *dev = crtc->dev;
  1753. struct amdgpu_device *adev = dev->dev_private;
  1754. if (enable)
  1755. WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
  1756. else
  1757. WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
  1758. }
  1759. static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
  1760. struct drm_framebuffer *fb,
  1761. int x, int y, int atomic)
  1762. {
  1763. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1764. struct drm_device *dev = crtc->dev;
  1765. struct amdgpu_device *adev = dev->dev_private;
  1766. struct amdgpu_framebuffer *amdgpu_fb;
  1767. struct drm_framebuffer *target_fb;
  1768. struct drm_gem_object *obj;
  1769. struct amdgpu_bo *abo;
  1770. uint64_t fb_location, tiling_flags;
  1771. uint32_t fb_format, fb_pitch_pixels;
  1772. u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
  1773. u32 pipe_config;
  1774. u32 tmp, viewport_w, viewport_h;
  1775. int r;
  1776. bool bypass_lut = false;
  1777. struct drm_format_name_buf format_name;
  1778. /* no fb bound */
  1779. if (!atomic && !crtc->primary->fb) {
  1780. DRM_DEBUG_KMS("No FB bound\n");
  1781. return 0;
  1782. }
  1783. if (atomic) {
  1784. amdgpu_fb = to_amdgpu_framebuffer(fb);
  1785. target_fb = fb;
  1786. } else {
  1787. amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
  1788. target_fb = crtc->primary->fb;
  1789. }
  1790. /* If atomic, assume fb object is pinned & idle & fenced and
  1791. * just update base pointers
  1792. */
  1793. obj = amdgpu_fb->obj;
  1794. abo = gem_to_amdgpu_bo(obj);
  1795. r = amdgpu_bo_reserve(abo, false);
  1796. if (unlikely(r != 0))
  1797. return r;
  1798. if (atomic) {
  1799. fb_location = amdgpu_bo_gpu_offset(abo);
  1800. } else {
  1801. r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
  1802. if (unlikely(r != 0)) {
  1803. amdgpu_bo_unreserve(abo);
  1804. return -EINVAL;
  1805. }
  1806. }
  1807. amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
  1808. amdgpu_bo_unreserve(abo);
  1809. pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
  1810. switch (target_fb->format->format) {
  1811. case DRM_FORMAT_C8:
  1812. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
  1813. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
  1814. break;
  1815. case DRM_FORMAT_XRGB4444:
  1816. case DRM_FORMAT_ARGB4444:
  1817. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1818. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
  1819. #ifdef __BIG_ENDIAN
  1820. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1821. ENDIAN_8IN16);
  1822. #endif
  1823. break;
  1824. case DRM_FORMAT_XRGB1555:
  1825. case DRM_FORMAT_ARGB1555:
  1826. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1827. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
  1828. #ifdef __BIG_ENDIAN
  1829. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1830. ENDIAN_8IN16);
  1831. #endif
  1832. break;
  1833. case DRM_FORMAT_BGRX5551:
  1834. case DRM_FORMAT_BGRA5551:
  1835. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1836. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
  1837. #ifdef __BIG_ENDIAN
  1838. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1839. ENDIAN_8IN16);
  1840. #endif
  1841. break;
  1842. case DRM_FORMAT_RGB565:
  1843. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1844. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
  1845. #ifdef __BIG_ENDIAN
  1846. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1847. ENDIAN_8IN16);
  1848. #endif
  1849. break;
  1850. case DRM_FORMAT_XRGB8888:
  1851. case DRM_FORMAT_ARGB8888:
  1852. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
  1853. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
  1854. #ifdef __BIG_ENDIAN
  1855. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1856. ENDIAN_8IN32);
  1857. #endif
  1858. break;
  1859. case DRM_FORMAT_XRGB2101010:
  1860. case DRM_FORMAT_ARGB2101010:
  1861. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
  1862. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
  1863. #ifdef __BIG_ENDIAN
  1864. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1865. ENDIAN_8IN32);
  1866. #endif
  1867. /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
  1868. bypass_lut = true;
  1869. break;
  1870. case DRM_FORMAT_BGRX1010102:
  1871. case DRM_FORMAT_BGRA1010102:
  1872. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
  1873. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
  1874. #ifdef __BIG_ENDIAN
  1875. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1876. ENDIAN_8IN32);
  1877. #endif
  1878. /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
  1879. bypass_lut = true;
  1880. break;
  1881. default:
  1882. DRM_ERROR("Unsupported screen format %s\n",
  1883. drm_get_format_name(target_fb->format->format, &format_name));
  1884. return -EINVAL;
  1885. }
  1886. if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
  1887. unsigned bankw, bankh, mtaspect, tile_split, num_banks;
  1888. bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
  1889. bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
  1890. mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
  1891. tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
  1892. num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
  1893. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
  1894. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
  1895. ARRAY_2D_TILED_THIN1);
  1896. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
  1897. tile_split);
  1898. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
  1899. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
  1900. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
  1901. mtaspect);
  1902. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
  1903. ADDR_SURF_MICRO_TILING_DISPLAY);
  1904. } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
  1905. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
  1906. ARRAY_1D_TILED_THIN1);
  1907. }
  1908. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
  1909. pipe_config);
  1910. dce_v10_0_vga_enable(crtc, false);
  1911. /* Make sure surface address is updated at vertical blank rather than
  1912. * horizontal blank
  1913. */
  1914. tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
  1915. tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
  1916. GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
  1917. WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1918. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  1919. upper_32_bits(fb_location));
  1920. WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  1921. upper_32_bits(fb_location));
  1922. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  1923. (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
  1924. WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  1925. (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
  1926. WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
  1927. WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
  1928. /*
  1929. * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
  1930. * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
  1931. * retain the full precision throughout the pipeline.
  1932. */
  1933. tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
  1934. if (bypass_lut)
  1935. tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
  1936. else
  1937. tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
  1938. WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
  1939. if (bypass_lut)
  1940. DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
  1941. WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
  1942. WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
  1943. WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
  1944. WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
  1945. WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
  1946. WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
  1947. fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
  1948. WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
  1949. dce_v10_0_grph_enable(crtc, true);
  1950. WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
  1951. target_fb->height);
  1952. x &= ~3;
  1953. y &= ~1;
  1954. WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
  1955. (x << 16) | y);
  1956. viewport_w = crtc->mode.hdisplay;
  1957. viewport_h = (crtc->mode.vdisplay + 1) & ~1;
  1958. WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
  1959. (viewport_w << 16) | viewport_h);
  1960. /* set pageflip to happen anywhere in vblank interval */
  1961. WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
  1962. if (!atomic && fb && fb != crtc->primary->fb) {
  1963. amdgpu_fb = to_amdgpu_framebuffer(fb);
  1964. abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
  1965. r = amdgpu_bo_reserve(abo, true);
  1966. if (unlikely(r != 0))
  1967. return r;
  1968. amdgpu_bo_unpin(abo);
  1969. amdgpu_bo_unreserve(abo);
  1970. }
  1971. /* Bytes per pixel may have changed */
  1972. dce_v10_0_bandwidth_update(adev);
  1973. return 0;
  1974. }
  1975. static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
  1976. struct drm_display_mode *mode)
  1977. {
  1978. struct drm_device *dev = crtc->dev;
  1979. struct amdgpu_device *adev = dev->dev_private;
  1980. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1981. u32 tmp;
  1982. tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
  1983. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1984. tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
  1985. else
  1986. tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
  1987. WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
  1988. }
  1989. static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
  1990. {
  1991. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1992. struct drm_device *dev = crtc->dev;
  1993. struct amdgpu_device *adev = dev->dev_private;
  1994. int i;
  1995. u32 tmp;
  1996. DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
  1997. tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
  1998. tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
  1999. tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
  2000. WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2001. tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
  2002. tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
  2003. WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2004. tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
  2005. tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
  2006. WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2007. tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
  2008. tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
  2009. tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
  2010. WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2011. WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
  2012. WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
  2013. WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
  2014. WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
  2015. WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
  2016. WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
  2017. WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
  2018. WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
  2019. WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
  2020. WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
  2021. for (i = 0; i < 256; i++) {
  2022. WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
  2023. (amdgpu_crtc->lut_r[i] << 20) |
  2024. (amdgpu_crtc->lut_g[i] << 10) |
  2025. (amdgpu_crtc->lut_b[i] << 0));
  2026. }
  2027. tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
  2028. tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
  2029. tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
  2030. tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
  2031. WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2032. tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
  2033. tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
  2034. tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
  2035. WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2036. tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
  2037. tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
  2038. tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
  2039. WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2040. tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
  2041. tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
  2042. tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
  2043. WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2044. /* XXX match this to the depth of the crtc fmt block, move to modeset? */
  2045. WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
  2046. /* XXX this only needs to be programmed once per crtc at startup,
  2047. * not sure where the best place for it is
  2048. */
  2049. tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
  2050. tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
  2051. WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2052. }
  2053. static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
  2054. {
  2055. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  2056. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  2057. switch (amdgpu_encoder->encoder_id) {
  2058. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  2059. if (dig->linkb)
  2060. return 1;
  2061. else
  2062. return 0;
  2063. break;
  2064. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  2065. if (dig->linkb)
  2066. return 3;
  2067. else
  2068. return 2;
  2069. break;
  2070. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  2071. if (dig->linkb)
  2072. return 5;
  2073. else
  2074. return 4;
  2075. break;
  2076. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  2077. return 6;
  2078. break;
  2079. default:
  2080. DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
  2081. return 0;
  2082. }
  2083. }
  2084. /**
  2085. * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
  2086. *
  2087. * @crtc: drm crtc
  2088. *
  2089. * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
  2090. * a single PPLL can be used for all DP crtcs/encoders. For non-DP
  2091. * monitors a dedicated PPLL must be used. If a particular board has
  2092. * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
  2093. * as there is no need to program the PLL itself. If we are not able to
  2094. * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
  2095. * avoid messing up an existing monitor.
  2096. *
  2097. * Asic specific PLL information
  2098. *
  2099. * DCE 10.x
  2100. * Tonga
  2101. * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
  2102. * CI
  2103. * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
  2104. *
  2105. */
  2106. static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
  2107. {
  2108. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2109. struct drm_device *dev = crtc->dev;
  2110. struct amdgpu_device *adev = dev->dev_private;
  2111. u32 pll_in_use;
  2112. int pll;
  2113. if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
  2114. if (adev->clock.dp_extclk)
  2115. /* skip PPLL programming if using ext clock */
  2116. return ATOM_PPLL_INVALID;
  2117. else {
  2118. /* use the same PPLL for all DP monitors */
  2119. pll = amdgpu_pll_get_shared_dp_ppll(crtc);
  2120. if (pll != ATOM_PPLL_INVALID)
  2121. return pll;
  2122. }
  2123. } else {
  2124. /* use the same PPLL for all monitors with the same clock */
  2125. pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
  2126. if (pll != ATOM_PPLL_INVALID)
  2127. return pll;
  2128. }
  2129. /* DCE10 has PPLL0, PPLL1, and PPLL2 */
  2130. pll_in_use = amdgpu_pll_get_use_mask(crtc);
  2131. if (!(pll_in_use & (1 << ATOM_PPLL2)))
  2132. return ATOM_PPLL2;
  2133. if (!(pll_in_use & (1 << ATOM_PPLL1)))
  2134. return ATOM_PPLL1;
  2135. if (!(pll_in_use & (1 << ATOM_PPLL0)))
  2136. return ATOM_PPLL0;
  2137. DRM_ERROR("unable to allocate a PPLL\n");
  2138. return ATOM_PPLL_INVALID;
  2139. }
  2140. static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
  2141. {
  2142. struct amdgpu_device *adev = crtc->dev->dev_private;
  2143. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2144. uint32_t cur_lock;
  2145. cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
  2146. if (lock)
  2147. cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
  2148. else
  2149. cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
  2150. WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
  2151. }
  2152. static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
  2153. {
  2154. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2155. struct amdgpu_device *adev = crtc->dev->dev_private;
  2156. u32 tmp;
  2157. tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
  2158. tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
  2159. WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2160. }
  2161. static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
  2162. {
  2163. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2164. struct amdgpu_device *adev = crtc->dev->dev_private;
  2165. u32 tmp;
  2166. WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  2167. upper_32_bits(amdgpu_crtc->cursor_addr));
  2168. WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  2169. lower_32_bits(amdgpu_crtc->cursor_addr));
  2170. tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
  2171. tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
  2172. tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
  2173. WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2174. }
  2175. static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
  2176. int x, int y)
  2177. {
  2178. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2179. struct amdgpu_device *adev = crtc->dev->dev_private;
  2180. int xorigin = 0, yorigin = 0;
  2181. amdgpu_crtc->cursor_x = x;
  2182. amdgpu_crtc->cursor_y = y;
  2183. /* avivo cursor are offset into the total surface */
  2184. x += crtc->x;
  2185. y += crtc->y;
  2186. DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
  2187. if (x < 0) {
  2188. xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
  2189. x = 0;
  2190. }
  2191. if (y < 0) {
  2192. yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
  2193. y = 0;
  2194. }
  2195. WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
  2196. WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
  2197. WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
  2198. ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
  2199. return 0;
  2200. }
  2201. static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
  2202. int x, int y)
  2203. {
  2204. int ret;
  2205. dce_v10_0_lock_cursor(crtc, true);
  2206. ret = dce_v10_0_cursor_move_locked(crtc, x, y);
  2207. dce_v10_0_lock_cursor(crtc, false);
  2208. return ret;
  2209. }
  2210. static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
  2211. struct drm_file *file_priv,
  2212. uint32_t handle,
  2213. uint32_t width,
  2214. uint32_t height,
  2215. int32_t hot_x,
  2216. int32_t hot_y)
  2217. {
  2218. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2219. struct drm_gem_object *obj;
  2220. struct amdgpu_bo *aobj;
  2221. int ret;
  2222. if (!handle) {
  2223. /* turn off cursor */
  2224. dce_v10_0_hide_cursor(crtc);
  2225. obj = NULL;
  2226. goto unpin;
  2227. }
  2228. if ((width > amdgpu_crtc->max_cursor_width) ||
  2229. (height > amdgpu_crtc->max_cursor_height)) {
  2230. DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
  2231. return -EINVAL;
  2232. }
  2233. obj = drm_gem_object_lookup(file_priv, handle);
  2234. if (!obj) {
  2235. DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
  2236. return -ENOENT;
  2237. }
  2238. aobj = gem_to_amdgpu_bo(obj);
  2239. ret = amdgpu_bo_reserve(aobj, false);
  2240. if (ret != 0) {
  2241. drm_gem_object_unreference_unlocked(obj);
  2242. return ret;
  2243. }
  2244. ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
  2245. amdgpu_bo_unreserve(aobj);
  2246. if (ret) {
  2247. DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
  2248. drm_gem_object_unreference_unlocked(obj);
  2249. return ret;
  2250. }
  2251. dce_v10_0_lock_cursor(crtc, true);
  2252. if (width != amdgpu_crtc->cursor_width ||
  2253. height != amdgpu_crtc->cursor_height ||
  2254. hot_x != amdgpu_crtc->cursor_hot_x ||
  2255. hot_y != amdgpu_crtc->cursor_hot_y) {
  2256. int x, y;
  2257. x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
  2258. y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
  2259. dce_v10_0_cursor_move_locked(crtc, x, y);
  2260. amdgpu_crtc->cursor_width = width;
  2261. amdgpu_crtc->cursor_height = height;
  2262. amdgpu_crtc->cursor_hot_x = hot_x;
  2263. amdgpu_crtc->cursor_hot_y = hot_y;
  2264. }
  2265. dce_v10_0_show_cursor(crtc);
  2266. dce_v10_0_lock_cursor(crtc, false);
  2267. unpin:
  2268. if (amdgpu_crtc->cursor_bo) {
  2269. struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
  2270. ret = amdgpu_bo_reserve(aobj, true);
  2271. if (likely(ret == 0)) {
  2272. amdgpu_bo_unpin(aobj);
  2273. amdgpu_bo_unreserve(aobj);
  2274. }
  2275. drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
  2276. }
  2277. amdgpu_crtc->cursor_bo = obj;
  2278. return 0;
  2279. }
  2280. static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
  2281. {
  2282. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2283. if (amdgpu_crtc->cursor_bo) {
  2284. dce_v10_0_lock_cursor(crtc, true);
  2285. dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
  2286. amdgpu_crtc->cursor_y);
  2287. dce_v10_0_show_cursor(crtc);
  2288. dce_v10_0_lock_cursor(crtc, false);
  2289. }
  2290. }
  2291. static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  2292. u16 *blue, uint32_t size,
  2293. struct drm_modeset_acquire_ctx *ctx)
  2294. {
  2295. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2296. int i;
  2297. /* userspace palettes are always correct as is */
  2298. for (i = 0; i < size; i++) {
  2299. amdgpu_crtc->lut_r[i] = red[i] >> 6;
  2300. amdgpu_crtc->lut_g[i] = green[i] >> 6;
  2301. amdgpu_crtc->lut_b[i] = blue[i] >> 6;
  2302. }
  2303. dce_v10_0_crtc_load_lut(crtc);
  2304. return 0;
  2305. }
  2306. static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
  2307. {
  2308. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2309. drm_crtc_cleanup(crtc);
  2310. kfree(amdgpu_crtc);
  2311. }
  2312. static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
  2313. .cursor_set2 = dce_v10_0_crtc_cursor_set2,
  2314. .cursor_move = dce_v10_0_crtc_cursor_move,
  2315. .gamma_set = dce_v10_0_crtc_gamma_set,
  2316. .set_config = amdgpu_crtc_set_config,
  2317. .destroy = dce_v10_0_crtc_destroy,
  2318. .page_flip_target = amdgpu_crtc_page_flip_target,
  2319. };
  2320. static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
  2321. {
  2322. struct drm_device *dev = crtc->dev;
  2323. struct amdgpu_device *adev = dev->dev_private;
  2324. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2325. unsigned type;
  2326. switch (mode) {
  2327. case DRM_MODE_DPMS_ON:
  2328. amdgpu_crtc->enabled = true;
  2329. amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
  2330. dce_v10_0_vga_enable(crtc, true);
  2331. amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
  2332. dce_v10_0_vga_enable(crtc, false);
  2333. /* Make sure VBLANK and PFLIP interrupts are still enabled */
  2334. type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
  2335. amdgpu_irq_update(adev, &adev->crtc_irq, type);
  2336. amdgpu_irq_update(adev, &adev->pageflip_irq, type);
  2337. drm_crtc_vblank_on(crtc);
  2338. dce_v10_0_crtc_load_lut(crtc);
  2339. break;
  2340. case DRM_MODE_DPMS_STANDBY:
  2341. case DRM_MODE_DPMS_SUSPEND:
  2342. case DRM_MODE_DPMS_OFF:
  2343. drm_crtc_vblank_off(crtc);
  2344. if (amdgpu_crtc->enabled) {
  2345. dce_v10_0_vga_enable(crtc, true);
  2346. amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
  2347. dce_v10_0_vga_enable(crtc, false);
  2348. }
  2349. amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
  2350. amdgpu_crtc->enabled = false;
  2351. break;
  2352. }
  2353. /* adjust pm to dpms */
  2354. amdgpu_pm_compute_clocks(adev);
  2355. }
  2356. static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
  2357. {
  2358. /* disable crtc pair power gating before programming */
  2359. amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
  2360. amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
  2361. dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  2362. }
  2363. static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
  2364. {
  2365. dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  2366. amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
  2367. }
  2368. static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
  2369. {
  2370. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2371. struct drm_device *dev = crtc->dev;
  2372. struct amdgpu_device *adev = dev->dev_private;
  2373. struct amdgpu_atom_ss ss;
  2374. int i;
  2375. dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  2376. if (crtc->primary->fb) {
  2377. int r;
  2378. struct amdgpu_framebuffer *amdgpu_fb;
  2379. struct amdgpu_bo *abo;
  2380. amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
  2381. abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
  2382. r = amdgpu_bo_reserve(abo, true);
  2383. if (unlikely(r))
  2384. DRM_ERROR("failed to reserve abo before unpin\n");
  2385. else {
  2386. amdgpu_bo_unpin(abo);
  2387. amdgpu_bo_unreserve(abo);
  2388. }
  2389. }
  2390. /* disable the GRPH */
  2391. dce_v10_0_grph_enable(crtc, false);
  2392. amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
  2393. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  2394. if (adev->mode_info.crtcs[i] &&
  2395. adev->mode_info.crtcs[i]->enabled &&
  2396. i != amdgpu_crtc->crtc_id &&
  2397. amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
  2398. /* one other crtc is using this pll don't turn
  2399. * off the pll
  2400. */
  2401. goto done;
  2402. }
  2403. }
  2404. switch (amdgpu_crtc->pll_id) {
  2405. case ATOM_PPLL0:
  2406. case ATOM_PPLL1:
  2407. case ATOM_PPLL2:
  2408. /* disable the ppll */
  2409. amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
  2410. 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
  2411. break;
  2412. default:
  2413. break;
  2414. }
  2415. done:
  2416. amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  2417. amdgpu_crtc->adjusted_clock = 0;
  2418. amdgpu_crtc->encoder = NULL;
  2419. amdgpu_crtc->connector = NULL;
  2420. }
  2421. static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
  2422. struct drm_display_mode *mode,
  2423. struct drm_display_mode *adjusted_mode,
  2424. int x, int y, struct drm_framebuffer *old_fb)
  2425. {
  2426. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2427. if (!amdgpu_crtc->adjusted_clock)
  2428. return -EINVAL;
  2429. amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
  2430. amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
  2431. dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
  2432. amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
  2433. amdgpu_atombios_crtc_scaler_setup(crtc);
  2434. dce_v10_0_cursor_reset(crtc);
  2435. /* update the hw version fpr dpm */
  2436. amdgpu_crtc->hw_mode = *adjusted_mode;
  2437. return 0;
  2438. }
  2439. static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
  2440. const struct drm_display_mode *mode,
  2441. struct drm_display_mode *adjusted_mode)
  2442. {
  2443. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2444. struct drm_device *dev = crtc->dev;
  2445. struct drm_encoder *encoder;
  2446. /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
  2447. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2448. if (encoder->crtc == crtc) {
  2449. amdgpu_crtc->encoder = encoder;
  2450. amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
  2451. break;
  2452. }
  2453. }
  2454. if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
  2455. amdgpu_crtc->encoder = NULL;
  2456. amdgpu_crtc->connector = NULL;
  2457. return false;
  2458. }
  2459. if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
  2460. return false;
  2461. if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
  2462. return false;
  2463. /* pick pll */
  2464. amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
  2465. /* if we can't get a PPLL for a non-DP encoder, fail */
  2466. if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
  2467. !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
  2468. return false;
  2469. return true;
  2470. }
  2471. static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  2472. struct drm_framebuffer *old_fb)
  2473. {
  2474. return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
  2475. }
  2476. static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
  2477. struct drm_framebuffer *fb,
  2478. int x, int y, enum mode_set_atomic state)
  2479. {
  2480. return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
  2481. }
  2482. static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
  2483. .dpms = dce_v10_0_crtc_dpms,
  2484. .mode_fixup = dce_v10_0_crtc_mode_fixup,
  2485. .mode_set = dce_v10_0_crtc_mode_set,
  2486. .mode_set_base = dce_v10_0_crtc_set_base,
  2487. .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
  2488. .prepare = dce_v10_0_crtc_prepare,
  2489. .commit = dce_v10_0_crtc_commit,
  2490. .load_lut = dce_v10_0_crtc_load_lut,
  2491. .disable = dce_v10_0_crtc_disable,
  2492. };
  2493. static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
  2494. {
  2495. struct amdgpu_crtc *amdgpu_crtc;
  2496. int i;
  2497. amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
  2498. (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  2499. if (amdgpu_crtc == NULL)
  2500. return -ENOMEM;
  2501. drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
  2502. drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
  2503. amdgpu_crtc->crtc_id = index;
  2504. adev->mode_info.crtcs[index] = amdgpu_crtc;
  2505. amdgpu_crtc->max_cursor_width = 128;
  2506. amdgpu_crtc->max_cursor_height = 128;
  2507. adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
  2508. adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
  2509. for (i = 0; i < 256; i++) {
  2510. amdgpu_crtc->lut_r[i] = i << 2;
  2511. amdgpu_crtc->lut_g[i] = i << 2;
  2512. amdgpu_crtc->lut_b[i] = i << 2;
  2513. }
  2514. switch (amdgpu_crtc->crtc_id) {
  2515. case 0:
  2516. default:
  2517. amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
  2518. break;
  2519. case 1:
  2520. amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
  2521. break;
  2522. case 2:
  2523. amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
  2524. break;
  2525. case 3:
  2526. amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
  2527. break;
  2528. case 4:
  2529. amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
  2530. break;
  2531. case 5:
  2532. amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
  2533. break;
  2534. }
  2535. amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  2536. amdgpu_crtc->adjusted_clock = 0;
  2537. amdgpu_crtc->encoder = NULL;
  2538. amdgpu_crtc->connector = NULL;
  2539. drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
  2540. return 0;
  2541. }
  2542. static int dce_v10_0_early_init(void *handle)
  2543. {
  2544. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2545. adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
  2546. adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
  2547. dce_v10_0_set_display_funcs(adev);
  2548. dce_v10_0_set_irq_funcs(adev);
  2549. adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
  2550. switch (adev->asic_type) {
  2551. case CHIP_FIJI:
  2552. case CHIP_TONGA:
  2553. adev->mode_info.num_hpd = 6;
  2554. adev->mode_info.num_dig = 7;
  2555. break;
  2556. default:
  2557. /* FIXME: not supported yet */
  2558. return -EINVAL;
  2559. }
  2560. return 0;
  2561. }
  2562. static int dce_v10_0_sw_init(void *handle)
  2563. {
  2564. int r, i;
  2565. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2566. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  2567. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
  2568. if (r)
  2569. return r;
  2570. }
  2571. for (i = 8; i < 20; i += 2) {
  2572. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
  2573. if (r)
  2574. return r;
  2575. }
  2576. /* HPD hotplug */
  2577. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
  2578. if (r)
  2579. return r;
  2580. adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
  2581. adev->ddev->mode_config.async_page_flip = true;
  2582. adev->ddev->mode_config.max_width = 16384;
  2583. adev->ddev->mode_config.max_height = 16384;
  2584. adev->ddev->mode_config.preferred_depth = 24;
  2585. adev->ddev->mode_config.prefer_shadow = 1;
  2586. adev->ddev->mode_config.fb_base = adev->mc.aper_base;
  2587. r = amdgpu_modeset_create_props(adev);
  2588. if (r)
  2589. return r;
  2590. adev->ddev->mode_config.max_width = 16384;
  2591. adev->ddev->mode_config.max_height = 16384;
  2592. /* allocate crtcs */
  2593. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  2594. r = dce_v10_0_crtc_init(adev, i);
  2595. if (r)
  2596. return r;
  2597. }
  2598. if (amdgpu_atombios_get_connector_info_from_object_table(adev))
  2599. amdgpu_print_display_setup(adev->ddev);
  2600. else
  2601. return -EINVAL;
  2602. /* setup afmt */
  2603. r = dce_v10_0_afmt_init(adev);
  2604. if (r)
  2605. return r;
  2606. r = dce_v10_0_audio_init(adev);
  2607. if (r)
  2608. return r;
  2609. drm_kms_helper_poll_init(adev->ddev);
  2610. adev->mode_info.mode_config_initialized = true;
  2611. return 0;
  2612. }
  2613. static int dce_v10_0_sw_fini(void *handle)
  2614. {
  2615. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2616. kfree(adev->mode_info.bios_hardcoded_edid);
  2617. drm_kms_helper_poll_fini(adev->ddev);
  2618. dce_v10_0_audio_fini(adev);
  2619. dce_v10_0_afmt_fini(adev);
  2620. drm_mode_config_cleanup(adev->ddev);
  2621. adev->mode_info.mode_config_initialized = false;
  2622. return 0;
  2623. }
  2624. static int dce_v10_0_hw_init(void *handle)
  2625. {
  2626. int i;
  2627. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2628. dce_v10_0_init_golden_registers(adev);
  2629. /* init dig PHYs, disp eng pll */
  2630. amdgpu_atombios_encoder_init_dig(adev);
  2631. amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
  2632. /* initialize hpd */
  2633. dce_v10_0_hpd_init(adev);
  2634. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  2635. dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  2636. }
  2637. dce_v10_0_pageflip_interrupt_init(adev);
  2638. return 0;
  2639. }
  2640. static int dce_v10_0_hw_fini(void *handle)
  2641. {
  2642. int i;
  2643. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2644. dce_v10_0_hpd_fini(adev);
  2645. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  2646. dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  2647. }
  2648. dce_v10_0_pageflip_interrupt_fini(adev);
  2649. return 0;
  2650. }
  2651. static int dce_v10_0_suspend(void *handle)
  2652. {
  2653. return dce_v10_0_hw_fini(handle);
  2654. }
  2655. static int dce_v10_0_resume(void *handle)
  2656. {
  2657. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2658. int ret;
  2659. ret = dce_v10_0_hw_init(handle);
  2660. /* turn on the BL */
  2661. if (adev->mode_info.bl_encoder) {
  2662. u8 bl_level = amdgpu_display_backlight_get_level(adev,
  2663. adev->mode_info.bl_encoder);
  2664. amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
  2665. bl_level);
  2666. }
  2667. return ret;
  2668. }
  2669. static bool dce_v10_0_is_idle(void *handle)
  2670. {
  2671. return true;
  2672. }
  2673. static int dce_v10_0_wait_for_idle(void *handle)
  2674. {
  2675. return 0;
  2676. }
  2677. static bool dce_v10_0_check_soft_reset(void *handle)
  2678. {
  2679. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2680. return dce_v10_0_is_display_hung(adev);
  2681. }
  2682. static int dce_v10_0_soft_reset(void *handle)
  2683. {
  2684. u32 srbm_soft_reset = 0, tmp;
  2685. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2686. if (dce_v10_0_is_display_hung(adev))
  2687. srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
  2688. if (srbm_soft_reset) {
  2689. tmp = RREG32(mmSRBM_SOFT_RESET);
  2690. tmp |= srbm_soft_reset;
  2691. dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  2692. WREG32(mmSRBM_SOFT_RESET, tmp);
  2693. tmp = RREG32(mmSRBM_SOFT_RESET);
  2694. udelay(50);
  2695. tmp &= ~srbm_soft_reset;
  2696. WREG32(mmSRBM_SOFT_RESET, tmp);
  2697. tmp = RREG32(mmSRBM_SOFT_RESET);
  2698. /* Wait a little for things to settle down */
  2699. udelay(50);
  2700. }
  2701. return 0;
  2702. }
  2703. static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  2704. int crtc,
  2705. enum amdgpu_interrupt_state state)
  2706. {
  2707. u32 lb_interrupt_mask;
  2708. if (crtc >= adev->mode_info.num_crtc) {
  2709. DRM_DEBUG("invalid crtc %d\n", crtc);
  2710. return;
  2711. }
  2712. switch (state) {
  2713. case AMDGPU_IRQ_STATE_DISABLE:
  2714. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2715. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2716. VBLANK_INTERRUPT_MASK, 0);
  2717. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2718. break;
  2719. case AMDGPU_IRQ_STATE_ENABLE:
  2720. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2721. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2722. VBLANK_INTERRUPT_MASK, 1);
  2723. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2724. break;
  2725. default:
  2726. break;
  2727. }
  2728. }
  2729. static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
  2730. int crtc,
  2731. enum amdgpu_interrupt_state state)
  2732. {
  2733. u32 lb_interrupt_mask;
  2734. if (crtc >= adev->mode_info.num_crtc) {
  2735. DRM_DEBUG("invalid crtc %d\n", crtc);
  2736. return;
  2737. }
  2738. switch (state) {
  2739. case AMDGPU_IRQ_STATE_DISABLE:
  2740. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2741. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2742. VLINE_INTERRUPT_MASK, 0);
  2743. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2744. break;
  2745. case AMDGPU_IRQ_STATE_ENABLE:
  2746. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2747. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2748. VLINE_INTERRUPT_MASK, 1);
  2749. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2750. break;
  2751. default:
  2752. break;
  2753. }
  2754. }
  2755. static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
  2756. struct amdgpu_irq_src *source,
  2757. unsigned hpd,
  2758. enum amdgpu_interrupt_state state)
  2759. {
  2760. u32 tmp;
  2761. if (hpd >= adev->mode_info.num_hpd) {
  2762. DRM_DEBUG("invalid hdp %d\n", hpd);
  2763. return 0;
  2764. }
  2765. switch (state) {
  2766. case AMDGPU_IRQ_STATE_DISABLE:
  2767. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  2768. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
  2769. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  2770. break;
  2771. case AMDGPU_IRQ_STATE_ENABLE:
  2772. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  2773. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
  2774. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  2775. break;
  2776. default:
  2777. break;
  2778. }
  2779. return 0;
  2780. }
  2781. static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
  2782. struct amdgpu_irq_src *source,
  2783. unsigned type,
  2784. enum amdgpu_interrupt_state state)
  2785. {
  2786. switch (type) {
  2787. case AMDGPU_CRTC_IRQ_VBLANK1:
  2788. dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
  2789. break;
  2790. case AMDGPU_CRTC_IRQ_VBLANK2:
  2791. dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
  2792. break;
  2793. case AMDGPU_CRTC_IRQ_VBLANK3:
  2794. dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
  2795. break;
  2796. case AMDGPU_CRTC_IRQ_VBLANK4:
  2797. dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
  2798. break;
  2799. case AMDGPU_CRTC_IRQ_VBLANK5:
  2800. dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
  2801. break;
  2802. case AMDGPU_CRTC_IRQ_VBLANK6:
  2803. dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
  2804. break;
  2805. case AMDGPU_CRTC_IRQ_VLINE1:
  2806. dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
  2807. break;
  2808. case AMDGPU_CRTC_IRQ_VLINE2:
  2809. dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
  2810. break;
  2811. case AMDGPU_CRTC_IRQ_VLINE3:
  2812. dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
  2813. break;
  2814. case AMDGPU_CRTC_IRQ_VLINE4:
  2815. dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
  2816. break;
  2817. case AMDGPU_CRTC_IRQ_VLINE5:
  2818. dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
  2819. break;
  2820. case AMDGPU_CRTC_IRQ_VLINE6:
  2821. dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
  2822. break;
  2823. default:
  2824. break;
  2825. }
  2826. return 0;
  2827. }
  2828. static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
  2829. struct amdgpu_irq_src *src,
  2830. unsigned type,
  2831. enum amdgpu_interrupt_state state)
  2832. {
  2833. u32 reg;
  2834. if (type >= adev->mode_info.num_crtc) {
  2835. DRM_ERROR("invalid pageflip crtc %d\n", type);
  2836. return -EINVAL;
  2837. }
  2838. reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
  2839. if (state == AMDGPU_IRQ_STATE_DISABLE)
  2840. WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
  2841. reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
  2842. else
  2843. WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
  2844. reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
  2845. return 0;
  2846. }
  2847. static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
  2848. struct amdgpu_irq_src *source,
  2849. struct amdgpu_iv_entry *entry)
  2850. {
  2851. unsigned long flags;
  2852. unsigned crtc_id;
  2853. struct amdgpu_crtc *amdgpu_crtc;
  2854. struct amdgpu_flip_work *works;
  2855. crtc_id = (entry->src_id - 8) >> 1;
  2856. amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
  2857. if (crtc_id >= adev->mode_info.num_crtc) {
  2858. DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
  2859. return -EINVAL;
  2860. }
  2861. if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
  2862. GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
  2863. WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
  2864. GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
  2865. /* IRQ could occur when in initial stage */
  2866. if (amdgpu_crtc == NULL)
  2867. return 0;
  2868. spin_lock_irqsave(&adev->ddev->event_lock, flags);
  2869. works = amdgpu_crtc->pflip_works;
  2870. if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
  2871. DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
  2872. "AMDGPU_FLIP_SUBMITTED(%d)\n",
  2873. amdgpu_crtc->pflip_status,
  2874. AMDGPU_FLIP_SUBMITTED);
  2875. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  2876. return 0;
  2877. }
  2878. /* page flip completed. clean up */
  2879. amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
  2880. amdgpu_crtc->pflip_works = NULL;
  2881. /* wakeup usersapce */
  2882. if (works->event)
  2883. drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
  2884. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  2885. drm_crtc_vblank_put(&amdgpu_crtc->base);
  2886. schedule_work(&works->unpin_work);
  2887. return 0;
  2888. }
  2889. static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
  2890. int hpd)
  2891. {
  2892. u32 tmp;
  2893. if (hpd >= adev->mode_info.num_hpd) {
  2894. DRM_DEBUG("invalid hdp %d\n", hpd);
  2895. return;
  2896. }
  2897. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  2898. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
  2899. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  2900. }
  2901. static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
  2902. int crtc)
  2903. {
  2904. u32 tmp;
  2905. if (crtc >= adev->mode_info.num_crtc) {
  2906. DRM_DEBUG("invalid crtc %d\n", crtc);
  2907. return;
  2908. }
  2909. tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
  2910. tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
  2911. WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
  2912. }
  2913. static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
  2914. int crtc)
  2915. {
  2916. u32 tmp;
  2917. if (crtc >= adev->mode_info.num_crtc) {
  2918. DRM_DEBUG("invalid crtc %d\n", crtc);
  2919. return;
  2920. }
  2921. tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
  2922. tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
  2923. WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
  2924. }
  2925. static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
  2926. struct amdgpu_irq_src *source,
  2927. struct amdgpu_iv_entry *entry)
  2928. {
  2929. unsigned crtc = entry->src_id - 1;
  2930. uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
  2931. unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
  2932. switch (entry->src_data[0]) {
  2933. case 0: /* vblank */
  2934. if (disp_int & interrupt_status_offsets[crtc].vblank)
  2935. dce_v10_0_crtc_vblank_int_ack(adev, crtc);
  2936. else
  2937. DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
  2938. if (amdgpu_irq_enabled(adev, source, irq_type)) {
  2939. drm_handle_vblank(adev->ddev, crtc);
  2940. }
  2941. DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
  2942. break;
  2943. case 1: /* vline */
  2944. if (disp_int & interrupt_status_offsets[crtc].vline)
  2945. dce_v10_0_crtc_vline_int_ack(adev, crtc);
  2946. else
  2947. DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
  2948. DRM_DEBUG("IH: D%d vline\n", crtc + 1);
  2949. break;
  2950. default:
  2951. DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
  2952. break;
  2953. }
  2954. return 0;
  2955. }
  2956. static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
  2957. struct amdgpu_irq_src *source,
  2958. struct amdgpu_iv_entry *entry)
  2959. {
  2960. uint32_t disp_int, mask;
  2961. unsigned hpd;
  2962. if (entry->src_data[0] >= adev->mode_info.num_hpd) {
  2963. DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
  2964. return 0;
  2965. }
  2966. hpd = entry->src_data[0];
  2967. disp_int = RREG32(interrupt_status_offsets[hpd].reg);
  2968. mask = interrupt_status_offsets[hpd].hpd;
  2969. if (disp_int & mask) {
  2970. dce_v10_0_hpd_int_ack(adev, hpd);
  2971. schedule_work(&adev->hotplug_work);
  2972. DRM_DEBUG("IH: HPD%d\n", hpd + 1);
  2973. }
  2974. return 0;
  2975. }
  2976. static int dce_v10_0_set_clockgating_state(void *handle,
  2977. enum amd_clockgating_state state)
  2978. {
  2979. return 0;
  2980. }
  2981. static int dce_v10_0_set_powergating_state(void *handle,
  2982. enum amd_powergating_state state)
  2983. {
  2984. return 0;
  2985. }
  2986. static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
  2987. .name = "dce_v10_0",
  2988. .early_init = dce_v10_0_early_init,
  2989. .late_init = NULL,
  2990. .sw_init = dce_v10_0_sw_init,
  2991. .sw_fini = dce_v10_0_sw_fini,
  2992. .hw_init = dce_v10_0_hw_init,
  2993. .hw_fini = dce_v10_0_hw_fini,
  2994. .suspend = dce_v10_0_suspend,
  2995. .resume = dce_v10_0_resume,
  2996. .is_idle = dce_v10_0_is_idle,
  2997. .wait_for_idle = dce_v10_0_wait_for_idle,
  2998. .check_soft_reset = dce_v10_0_check_soft_reset,
  2999. .soft_reset = dce_v10_0_soft_reset,
  3000. .set_clockgating_state = dce_v10_0_set_clockgating_state,
  3001. .set_powergating_state = dce_v10_0_set_powergating_state,
  3002. };
  3003. static void
  3004. dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
  3005. struct drm_display_mode *mode,
  3006. struct drm_display_mode *adjusted_mode)
  3007. {
  3008. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  3009. amdgpu_encoder->pixel_clock = adjusted_mode->clock;
  3010. /* need to call this here rather than in prepare() since we need some crtc info */
  3011. amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  3012. /* set scaler clears this on some chips */
  3013. dce_v10_0_set_interleave(encoder->crtc, mode);
  3014. if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
  3015. dce_v10_0_afmt_enable(encoder, true);
  3016. dce_v10_0_afmt_setmode(encoder, adjusted_mode);
  3017. }
  3018. }
  3019. static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
  3020. {
  3021. struct amdgpu_device *adev = encoder->dev->dev_private;
  3022. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  3023. struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
  3024. if ((amdgpu_encoder->active_device &
  3025. (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
  3026. (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
  3027. ENCODER_OBJECT_ID_NONE)) {
  3028. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  3029. if (dig) {
  3030. dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
  3031. if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
  3032. dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
  3033. }
  3034. }
  3035. amdgpu_atombios_scratch_regs_lock(adev, true);
  3036. if (connector) {
  3037. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  3038. /* select the clock/data port if it uses a router */
  3039. if (amdgpu_connector->router.cd_valid)
  3040. amdgpu_i2c_router_select_cd_port(amdgpu_connector);
  3041. /* turn eDP panel on for mode set */
  3042. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  3043. amdgpu_atombios_encoder_set_edp_panel_power(connector,
  3044. ATOM_TRANSMITTER_ACTION_POWER_ON);
  3045. }
  3046. /* this is needed for the pll/ss setup to work correctly in some cases */
  3047. amdgpu_atombios_encoder_set_crtc_source(encoder);
  3048. /* set up the FMT blocks */
  3049. dce_v10_0_program_fmt(encoder);
  3050. }
  3051. static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
  3052. {
  3053. struct drm_device *dev = encoder->dev;
  3054. struct amdgpu_device *adev = dev->dev_private;
  3055. /* need to call this here as we need the crtc set up */
  3056. amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
  3057. amdgpu_atombios_scratch_regs_lock(adev, false);
  3058. }
  3059. static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
  3060. {
  3061. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  3062. struct amdgpu_encoder_atom_dig *dig;
  3063. amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  3064. if (amdgpu_atombios_encoder_is_digital(encoder)) {
  3065. if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
  3066. dce_v10_0_afmt_enable(encoder, false);
  3067. dig = amdgpu_encoder->enc_priv;
  3068. dig->dig_encoder = -1;
  3069. }
  3070. amdgpu_encoder->active_device = 0;
  3071. }
  3072. /* these are handled by the primary encoders */
  3073. static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
  3074. {
  3075. }
  3076. static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
  3077. {
  3078. }
  3079. static void
  3080. dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
  3081. struct drm_display_mode *mode,
  3082. struct drm_display_mode *adjusted_mode)
  3083. {
  3084. }
  3085. static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
  3086. {
  3087. }
  3088. static void
  3089. dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
  3090. {
  3091. }
  3092. static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
  3093. .dpms = dce_v10_0_ext_dpms,
  3094. .prepare = dce_v10_0_ext_prepare,
  3095. .mode_set = dce_v10_0_ext_mode_set,
  3096. .commit = dce_v10_0_ext_commit,
  3097. .disable = dce_v10_0_ext_disable,
  3098. /* no detect for TMDS/LVDS yet */
  3099. };
  3100. static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
  3101. .dpms = amdgpu_atombios_encoder_dpms,
  3102. .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
  3103. .prepare = dce_v10_0_encoder_prepare,
  3104. .mode_set = dce_v10_0_encoder_mode_set,
  3105. .commit = dce_v10_0_encoder_commit,
  3106. .disable = dce_v10_0_encoder_disable,
  3107. .detect = amdgpu_atombios_encoder_dig_detect,
  3108. };
  3109. static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
  3110. .dpms = amdgpu_atombios_encoder_dpms,
  3111. .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
  3112. .prepare = dce_v10_0_encoder_prepare,
  3113. .mode_set = dce_v10_0_encoder_mode_set,
  3114. .commit = dce_v10_0_encoder_commit,
  3115. .detect = amdgpu_atombios_encoder_dac_detect,
  3116. };
  3117. static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
  3118. {
  3119. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  3120. if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  3121. amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
  3122. kfree(amdgpu_encoder->enc_priv);
  3123. drm_encoder_cleanup(encoder);
  3124. kfree(amdgpu_encoder);
  3125. }
  3126. static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
  3127. .destroy = dce_v10_0_encoder_destroy,
  3128. };
  3129. static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
  3130. uint32_t encoder_enum,
  3131. uint32_t supported_device,
  3132. u16 caps)
  3133. {
  3134. struct drm_device *dev = adev->ddev;
  3135. struct drm_encoder *encoder;
  3136. struct amdgpu_encoder *amdgpu_encoder;
  3137. /* see if we already added it */
  3138. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3139. amdgpu_encoder = to_amdgpu_encoder(encoder);
  3140. if (amdgpu_encoder->encoder_enum == encoder_enum) {
  3141. amdgpu_encoder->devices |= supported_device;
  3142. return;
  3143. }
  3144. }
  3145. /* add a new one */
  3146. amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
  3147. if (!amdgpu_encoder)
  3148. return;
  3149. encoder = &amdgpu_encoder->base;
  3150. switch (adev->mode_info.num_crtc) {
  3151. case 1:
  3152. encoder->possible_crtcs = 0x1;
  3153. break;
  3154. case 2:
  3155. default:
  3156. encoder->possible_crtcs = 0x3;
  3157. break;
  3158. case 4:
  3159. encoder->possible_crtcs = 0xf;
  3160. break;
  3161. case 6:
  3162. encoder->possible_crtcs = 0x3f;
  3163. break;
  3164. }
  3165. amdgpu_encoder->enc_priv = NULL;
  3166. amdgpu_encoder->encoder_enum = encoder_enum;
  3167. amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  3168. amdgpu_encoder->devices = supported_device;
  3169. amdgpu_encoder->rmx_type = RMX_OFF;
  3170. amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
  3171. amdgpu_encoder->is_ext_encoder = false;
  3172. amdgpu_encoder->caps = caps;
  3173. switch (amdgpu_encoder->encoder_id) {
  3174. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  3175. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  3176. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3177. DRM_MODE_ENCODER_DAC, NULL);
  3178. drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
  3179. break;
  3180. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  3181. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  3182. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  3183. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  3184. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  3185. if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  3186. amdgpu_encoder->rmx_type = RMX_FULL;
  3187. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3188. DRM_MODE_ENCODER_LVDS, NULL);
  3189. amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
  3190. } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
  3191. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3192. DRM_MODE_ENCODER_DAC, NULL);
  3193. amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
  3194. } else {
  3195. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3196. DRM_MODE_ENCODER_TMDS, NULL);
  3197. amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
  3198. }
  3199. drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
  3200. break;
  3201. case ENCODER_OBJECT_ID_SI170B:
  3202. case ENCODER_OBJECT_ID_CH7303:
  3203. case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
  3204. case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
  3205. case ENCODER_OBJECT_ID_TITFP513:
  3206. case ENCODER_OBJECT_ID_VT1623:
  3207. case ENCODER_OBJECT_ID_HDMI_SI1930:
  3208. case ENCODER_OBJECT_ID_TRAVIS:
  3209. case ENCODER_OBJECT_ID_NUTMEG:
  3210. /* these are handled by the primary encoders */
  3211. amdgpu_encoder->is_ext_encoder = true;
  3212. if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  3213. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3214. DRM_MODE_ENCODER_LVDS, NULL);
  3215. else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
  3216. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3217. DRM_MODE_ENCODER_DAC, NULL);
  3218. else
  3219. drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
  3220. DRM_MODE_ENCODER_TMDS, NULL);
  3221. drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
  3222. break;
  3223. }
  3224. }
  3225. static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
  3226. .set_vga_render_state = &dce_v10_0_set_vga_render_state,
  3227. .bandwidth_update = &dce_v10_0_bandwidth_update,
  3228. .vblank_get_counter = &dce_v10_0_vblank_get_counter,
  3229. .vblank_wait = &dce_v10_0_vblank_wait,
  3230. .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
  3231. .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
  3232. .hpd_sense = &dce_v10_0_hpd_sense,
  3233. .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
  3234. .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
  3235. .page_flip = &dce_v10_0_page_flip,
  3236. .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
  3237. .add_encoder = &dce_v10_0_encoder_add,
  3238. .add_connector = &amdgpu_connector_add,
  3239. .stop_mc_access = &dce_v10_0_stop_mc_access,
  3240. .resume_mc_access = &dce_v10_0_resume_mc_access,
  3241. };
  3242. static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
  3243. {
  3244. if (adev->mode_info.funcs == NULL)
  3245. adev->mode_info.funcs = &dce_v10_0_display_funcs;
  3246. }
  3247. static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
  3248. .set = dce_v10_0_set_crtc_irq_state,
  3249. .process = dce_v10_0_crtc_irq,
  3250. };
  3251. static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
  3252. .set = dce_v10_0_set_pageflip_irq_state,
  3253. .process = dce_v10_0_pageflip_irq,
  3254. };
  3255. static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
  3256. .set = dce_v10_0_set_hpd_irq_state,
  3257. .process = dce_v10_0_hpd_irq,
  3258. };
  3259. static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
  3260. {
  3261. adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
  3262. adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
  3263. adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
  3264. adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
  3265. adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
  3266. adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
  3267. }
  3268. const struct amdgpu_ip_block_version dce_v10_0_ip_block =
  3269. {
  3270. .type = AMD_IP_BLOCK_TYPE_DCE,
  3271. .major = 10,
  3272. .minor = 0,
  3273. .rev = 0,
  3274. .funcs = &dce_v10_0_ip_funcs,
  3275. };
  3276. const struct amdgpu_ip_block_version dce_v10_1_ip_block =
  3277. {
  3278. .type = AMD_IP_BLOCK_TYPE_DCE,
  3279. .major = 10,
  3280. .minor = 1,
  3281. .rev = 0,
  3282. .funcs = &dce_v10_0_ip_funcs,
  3283. };