ci_dpm.c 206 KB

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  1. /*
  2. * Copyright 2013 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/firmware.h>
  24. #include <drm/drmP.h>
  25. #include "amdgpu.h"
  26. #include "amdgpu_pm.h"
  27. #include "amdgpu_ucode.h"
  28. #include "cikd.h"
  29. #include "amdgpu_dpm.h"
  30. #include "ci_dpm.h"
  31. #include "gfx_v7_0.h"
  32. #include "atom.h"
  33. #include "amd_pcie.h"
  34. #include <linux/seq_file.h>
  35. #include "smu/smu_7_0_1_d.h"
  36. #include "smu/smu_7_0_1_sh_mask.h"
  37. #include "dce/dce_8_0_d.h"
  38. #include "dce/dce_8_0_sh_mask.h"
  39. #include "bif/bif_4_1_d.h"
  40. #include "bif/bif_4_1_sh_mask.h"
  41. #include "gca/gfx_7_2_d.h"
  42. #include "gca/gfx_7_2_sh_mask.h"
  43. #include "gmc/gmc_7_1_d.h"
  44. #include "gmc/gmc_7_1_sh_mask.h"
  45. MODULE_FIRMWARE("radeon/bonaire_smc.bin");
  46. MODULE_FIRMWARE("radeon/bonaire_k_smc.bin");
  47. MODULE_FIRMWARE("radeon/hawaii_smc.bin");
  48. MODULE_FIRMWARE("radeon/hawaii_k_smc.bin");
  49. #define MC_CG_ARB_FREQ_F0 0x0a
  50. #define MC_CG_ARB_FREQ_F1 0x0b
  51. #define MC_CG_ARB_FREQ_F2 0x0c
  52. #define MC_CG_ARB_FREQ_F3 0x0d
  53. #define SMC_RAM_END 0x40000
  54. #define VOLTAGE_SCALE 4
  55. #define VOLTAGE_VID_OFFSET_SCALE1 625
  56. #define VOLTAGE_VID_OFFSET_SCALE2 100
  57. static const struct ci_pt_defaults defaults_hawaii_xt =
  58. {
  59. 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  60. { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
  61. { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  62. };
  63. static const struct ci_pt_defaults defaults_hawaii_pro =
  64. {
  65. 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  66. { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
  67. { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
  68. };
  69. static const struct ci_pt_defaults defaults_bonaire_xt =
  70. {
  71. 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  72. { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
  73. { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  74. };
  75. #if 0
  76. static const struct ci_pt_defaults defaults_bonaire_pro =
  77. {
  78. 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  79. { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
  80. { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  81. };
  82. #endif
  83. static const struct ci_pt_defaults defaults_saturn_xt =
  84. {
  85. 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  86. { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
  87. { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  88. };
  89. #if 0
  90. static const struct ci_pt_defaults defaults_saturn_pro =
  91. {
  92. 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  93. { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
  94. { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  95. };
  96. #endif
  97. static const struct ci_pt_config_reg didt_config_ci[] =
  98. {
  99. { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  100. { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  101. { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  102. { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  103. { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  104. { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  105. { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  106. { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  107. { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  108. { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  109. { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  110. { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  111. { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
  112. { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
  113. { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
  114. { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  115. { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  116. { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  117. { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  118. { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  119. { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  120. { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  121. { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  122. { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  123. { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  124. { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  125. { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  126. { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  127. { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  128. { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  129. { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
  130. { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
  131. { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
  132. { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  133. { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  134. { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  135. { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  136. { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  137. { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  138. { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  139. { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  140. { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  141. { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  142. { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  143. { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  144. { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  145. { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  146. { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  147. { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
  148. { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
  149. { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
  150. { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  151. { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  152. { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  153. { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  154. { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  155. { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  156. { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  157. { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  158. { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  159. { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  160. { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  161. { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  162. { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  163. { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  164. { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  165. { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
  166. { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
  167. { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
  168. { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  169. { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
  170. { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  171. { 0xFFFFFFFF }
  172. };
  173. static u8 ci_get_memory_module_index(struct amdgpu_device *adev)
  174. {
  175. return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
  176. }
  177. #define MC_CG_ARB_FREQ_F0 0x0a
  178. #define MC_CG_ARB_FREQ_F1 0x0b
  179. #define MC_CG_ARB_FREQ_F2 0x0c
  180. #define MC_CG_ARB_FREQ_F3 0x0d
  181. static int ci_copy_and_switch_arb_sets(struct amdgpu_device *adev,
  182. u32 arb_freq_src, u32 arb_freq_dest)
  183. {
  184. u32 mc_arb_dram_timing;
  185. u32 mc_arb_dram_timing2;
  186. u32 burst_time;
  187. u32 mc_cg_config;
  188. switch (arb_freq_src) {
  189. case MC_CG_ARB_FREQ_F0:
  190. mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
  191. mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
  192. burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
  193. MC_ARB_BURST_TIME__STATE0__SHIFT;
  194. break;
  195. case MC_CG_ARB_FREQ_F1:
  196. mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
  197. mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
  198. burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
  199. MC_ARB_BURST_TIME__STATE1__SHIFT;
  200. break;
  201. default:
  202. return -EINVAL;
  203. }
  204. switch (arb_freq_dest) {
  205. case MC_CG_ARB_FREQ_F0:
  206. WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
  207. WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
  208. WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT),
  209. ~MC_ARB_BURST_TIME__STATE0_MASK);
  210. break;
  211. case MC_CG_ARB_FREQ_F1:
  212. WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
  213. WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
  214. WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT),
  215. ~MC_ARB_BURST_TIME__STATE1_MASK);
  216. break;
  217. default:
  218. return -EINVAL;
  219. }
  220. mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
  221. WREG32(mmMC_CG_CONFIG, mc_cg_config);
  222. WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT,
  223. ~MC_ARB_CG__CG_ARB_REQ_MASK);
  224. return 0;
  225. }
  226. static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
  227. {
  228. u8 mc_para_index;
  229. if (memory_clock < 10000)
  230. mc_para_index = 0;
  231. else if (memory_clock >= 80000)
  232. mc_para_index = 0x0f;
  233. else
  234. mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
  235. return mc_para_index;
  236. }
  237. static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
  238. {
  239. u8 mc_para_index;
  240. if (strobe_mode) {
  241. if (memory_clock < 12500)
  242. mc_para_index = 0x00;
  243. else if (memory_clock > 47500)
  244. mc_para_index = 0x0f;
  245. else
  246. mc_para_index = (u8)((memory_clock - 10000) / 2500);
  247. } else {
  248. if (memory_clock < 65000)
  249. mc_para_index = 0x00;
  250. else if (memory_clock > 135000)
  251. mc_para_index = 0x0f;
  252. else
  253. mc_para_index = (u8)((memory_clock - 60000) / 5000);
  254. }
  255. return mc_para_index;
  256. }
  257. static void ci_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
  258. u32 max_voltage_steps,
  259. struct atom_voltage_table *voltage_table)
  260. {
  261. unsigned int i, diff;
  262. if (voltage_table->count <= max_voltage_steps)
  263. return;
  264. diff = voltage_table->count - max_voltage_steps;
  265. for (i = 0; i < max_voltage_steps; i++)
  266. voltage_table->entries[i] = voltage_table->entries[i + diff];
  267. voltage_table->count = max_voltage_steps;
  268. }
  269. static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
  270. struct atom_voltage_table_entry *voltage_table,
  271. u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
  272. static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
  273. static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
  274. u32 target_tdp);
  275. static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
  276. static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
  277. static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
  278. static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
  279. PPSMC_Msg msg, u32 parameter);
  280. static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev);
  281. static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
  282. static struct ci_power_info *ci_get_pi(struct amdgpu_device *adev)
  283. {
  284. struct ci_power_info *pi = adev->pm.dpm.priv;
  285. return pi;
  286. }
  287. static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps)
  288. {
  289. struct ci_ps *ps = rps->ps_priv;
  290. return ps;
  291. }
  292. static void ci_initialize_powertune_defaults(struct amdgpu_device *adev)
  293. {
  294. struct ci_power_info *pi = ci_get_pi(adev);
  295. switch (adev->pdev->device) {
  296. case 0x6649:
  297. case 0x6650:
  298. case 0x6651:
  299. case 0x6658:
  300. case 0x665C:
  301. case 0x665D:
  302. default:
  303. pi->powertune_defaults = &defaults_bonaire_xt;
  304. break;
  305. case 0x6640:
  306. case 0x6641:
  307. case 0x6646:
  308. case 0x6647:
  309. pi->powertune_defaults = &defaults_saturn_xt;
  310. break;
  311. case 0x67B8:
  312. case 0x67B0:
  313. pi->powertune_defaults = &defaults_hawaii_xt;
  314. break;
  315. case 0x67BA:
  316. case 0x67B1:
  317. pi->powertune_defaults = &defaults_hawaii_pro;
  318. break;
  319. case 0x67A0:
  320. case 0x67A1:
  321. case 0x67A2:
  322. case 0x67A8:
  323. case 0x67A9:
  324. case 0x67AA:
  325. case 0x67B9:
  326. case 0x67BE:
  327. pi->powertune_defaults = &defaults_bonaire_xt;
  328. break;
  329. }
  330. pi->dte_tj_offset = 0;
  331. pi->caps_power_containment = true;
  332. pi->caps_cac = false;
  333. pi->caps_sq_ramping = false;
  334. pi->caps_db_ramping = false;
  335. pi->caps_td_ramping = false;
  336. pi->caps_tcp_ramping = false;
  337. if (pi->caps_power_containment) {
  338. pi->caps_cac = true;
  339. if (adev->asic_type == CHIP_HAWAII)
  340. pi->enable_bapm_feature = false;
  341. else
  342. pi->enable_bapm_feature = true;
  343. pi->enable_tdc_limit_feature = true;
  344. pi->enable_pkg_pwr_tracking_feature = true;
  345. }
  346. }
  347. static u8 ci_convert_to_vid(u16 vddc)
  348. {
  349. return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
  350. }
  351. static int ci_populate_bapm_vddc_vid_sidd(struct amdgpu_device *adev)
  352. {
  353. struct ci_power_info *pi = ci_get_pi(adev);
  354. u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
  355. u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
  356. u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
  357. u32 i;
  358. if (adev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
  359. return -EINVAL;
  360. if (adev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
  361. return -EINVAL;
  362. if (adev->pm.dpm.dyn_state.cac_leakage_table.count !=
  363. adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
  364. return -EINVAL;
  365. for (i = 0; i < adev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
  366. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
  367. lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
  368. hi_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
  369. hi2_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
  370. } else {
  371. lo_vid[i] = ci_convert_to_vid(adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
  372. hi_vid[i] = ci_convert_to_vid((u16)adev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
  373. }
  374. }
  375. return 0;
  376. }
  377. static int ci_populate_vddc_vid(struct amdgpu_device *adev)
  378. {
  379. struct ci_power_info *pi = ci_get_pi(adev);
  380. u8 *vid = pi->smc_powertune_table.VddCVid;
  381. u32 i;
  382. if (pi->vddc_voltage_table.count > 8)
  383. return -EINVAL;
  384. for (i = 0; i < pi->vddc_voltage_table.count; i++)
  385. vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
  386. return 0;
  387. }
  388. static int ci_populate_svi_load_line(struct amdgpu_device *adev)
  389. {
  390. struct ci_power_info *pi = ci_get_pi(adev);
  391. const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
  392. pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
  393. pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
  394. pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
  395. pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
  396. return 0;
  397. }
  398. static int ci_populate_tdc_limit(struct amdgpu_device *adev)
  399. {
  400. struct ci_power_info *pi = ci_get_pi(adev);
  401. const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
  402. u16 tdc_limit;
  403. tdc_limit = adev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
  404. pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
  405. pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
  406. pt_defaults->tdc_vddc_throttle_release_limit_perc;
  407. pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
  408. return 0;
  409. }
  410. static int ci_populate_dw8(struct amdgpu_device *adev)
  411. {
  412. struct ci_power_info *pi = ci_get_pi(adev);
  413. const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
  414. int ret;
  415. ret = amdgpu_ci_read_smc_sram_dword(adev,
  416. SMU7_FIRMWARE_HEADER_LOCATION +
  417. offsetof(SMU7_Firmware_Header, PmFuseTable) +
  418. offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
  419. (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
  420. pi->sram_end);
  421. if (ret)
  422. return -EINVAL;
  423. else
  424. pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
  425. return 0;
  426. }
  427. static int ci_populate_fuzzy_fan(struct amdgpu_device *adev)
  428. {
  429. struct ci_power_info *pi = ci_get_pi(adev);
  430. if ((adev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
  431. (adev->pm.dpm.fan.fan_output_sensitivity == 0))
  432. adev->pm.dpm.fan.fan_output_sensitivity =
  433. adev->pm.dpm.fan.default_fan_output_sensitivity;
  434. pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
  435. cpu_to_be16(adev->pm.dpm.fan.fan_output_sensitivity);
  436. return 0;
  437. }
  438. static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct amdgpu_device *adev)
  439. {
  440. struct ci_power_info *pi = ci_get_pi(adev);
  441. u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
  442. u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
  443. int i, min, max;
  444. min = max = hi_vid[0];
  445. for (i = 0; i < 8; i++) {
  446. if (0 != hi_vid[i]) {
  447. if (min > hi_vid[i])
  448. min = hi_vid[i];
  449. if (max < hi_vid[i])
  450. max = hi_vid[i];
  451. }
  452. if (0 != lo_vid[i]) {
  453. if (min > lo_vid[i])
  454. min = lo_vid[i];
  455. if (max < lo_vid[i])
  456. max = lo_vid[i];
  457. }
  458. }
  459. if ((min == 0) || (max == 0))
  460. return -EINVAL;
  461. pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
  462. pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
  463. return 0;
  464. }
  465. static int ci_populate_bapm_vddc_base_leakage_sidd(struct amdgpu_device *adev)
  466. {
  467. struct ci_power_info *pi = ci_get_pi(adev);
  468. u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
  469. u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
  470. struct amdgpu_cac_tdp_table *cac_tdp_table =
  471. adev->pm.dpm.dyn_state.cac_tdp_table;
  472. hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
  473. lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
  474. pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
  475. pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
  476. return 0;
  477. }
  478. static int ci_populate_bapm_parameters_in_dpm_table(struct amdgpu_device *adev)
  479. {
  480. struct ci_power_info *pi = ci_get_pi(adev);
  481. const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
  482. SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
  483. struct amdgpu_cac_tdp_table *cac_tdp_table =
  484. adev->pm.dpm.dyn_state.cac_tdp_table;
  485. struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
  486. int i, j, k;
  487. const u16 *def1;
  488. const u16 *def2;
  489. dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
  490. dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
  491. dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
  492. dpm_table->GpuTjMax =
  493. (u8)(pi->thermal_temp_setting.temperature_high / 1000);
  494. dpm_table->GpuTjHyst = 8;
  495. dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
  496. if (ppm) {
  497. dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
  498. dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
  499. } else {
  500. dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
  501. dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
  502. }
  503. dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
  504. def1 = pt_defaults->bapmti_r;
  505. def2 = pt_defaults->bapmti_rc;
  506. for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
  507. for (j = 0; j < SMU7_DTE_SOURCES; j++) {
  508. for (k = 0; k < SMU7_DTE_SINKS; k++) {
  509. dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
  510. dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
  511. def1++;
  512. def2++;
  513. }
  514. }
  515. }
  516. return 0;
  517. }
  518. static int ci_populate_pm_base(struct amdgpu_device *adev)
  519. {
  520. struct ci_power_info *pi = ci_get_pi(adev);
  521. u32 pm_fuse_table_offset;
  522. int ret;
  523. if (pi->caps_power_containment) {
  524. ret = amdgpu_ci_read_smc_sram_dword(adev,
  525. SMU7_FIRMWARE_HEADER_LOCATION +
  526. offsetof(SMU7_Firmware_Header, PmFuseTable),
  527. &pm_fuse_table_offset, pi->sram_end);
  528. if (ret)
  529. return ret;
  530. ret = ci_populate_bapm_vddc_vid_sidd(adev);
  531. if (ret)
  532. return ret;
  533. ret = ci_populate_vddc_vid(adev);
  534. if (ret)
  535. return ret;
  536. ret = ci_populate_svi_load_line(adev);
  537. if (ret)
  538. return ret;
  539. ret = ci_populate_tdc_limit(adev);
  540. if (ret)
  541. return ret;
  542. ret = ci_populate_dw8(adev);
  543. if (ret)
  544. return ret;
  545. ret = ci_populate_fuzzy_fan(adev);
  546. if (ret)
  547. return ret;
  548. ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(adev);
  549. if (ret)
  550. return ret;
  551. ret = ci_populate_bapm_vddc_base_leakage_sidd(adev);
  552. if (ret)
  553. return ret;
  554. ret = amdgpu_ci_copy_bytes_to_smc(adev, pm_fuse_table_offset,
  555. (u8 *)&pi->smc_powertune_table,
  556. sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
  557. if (ret)
  558. return ret;
  559. }
  560. return 0;
  561. }
  562. static void ci_do_enable_didt(struct amdgpu_device *adev, const bool enable)
  563. {
  564. struct ci_power_info *pi = ci_get_pi(adev);
  565. u32 data;
  566. if (pi->caps_sq_ramping) {
  567. data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
  568. if (enable)
  569. data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
  570. else
  571. data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
  572. WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
  573. }
  574. if (pi->caps_db_ramping) {
  575. data = RREG32_DIDT(ixDIDT_DB_CTRL0);
  576. if (enable)
  577. data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
  578. else
  579. data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
  580. WREG32_DIDT(ixDIDT_DB_CTRL0, data);
  581. }
  582. if (pi->caps_td_ramping) {
  583. data = RREG32_DIDT(ixDIDT_TD_CTRL0);
  584. if (enable)
  585. data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
  586. else
  587. data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
  588. WREG32_DIDT(ixDIDT_TD_CTRL0, data);
  589. }
  590. if (pi->caps_tcp_ramping) {
  591. data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
  592. if (enable)
  593. data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
  594. else
  595. data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
  596. WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
  597. }
  598. }
  599. static int ci_program_pt_config_registers(struct amdgpu_device *adev,
  600. const struct ci_pt_config_reg *cac_config_regs)
  601. {
  602. const struct ci_pt_config_reg *config_regs = cac_config_regs;
  603. u32 data;
  604. u32 cache = 0;
  605. if (config_regs == NULL)
  606. return -EINVAL;
  607. while (config_regs->offset != 0xFFFFFFFF) {
  608. if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
  609. cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
  610. } else {
  611. switch (config_regs->type) {
  612. case CISLANDS_CONFIGREG_SMC_IND:
  613. data = RREG32_SMC(config_regs->offset);
  614. break;
  615. case CISLANDS_CONFIGREG_DIDT_IND:
  616. data = RREG32_DIDT(config_regs->offset);
  617. break;
  618. default:
  619. data = RREG32(config_regs->offset);
  620. break;
  621. }
  622. data &= ~config_regs->mask;
  623. data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
  624. data |= cache;
  625. switch (config_regs->type) {
  626. case CISLANDS_CONFIGREG_SMC_IND:
  627. WREG32_SMC(config_regs->offset, data);
  628. break;
  629. case CISLANDS_CONFIGREG_DIDT_IND:
  630. WREG32_DIDT(config_regs->offset, data);
  631. break;
  632. default:
  633. WREG32(config_regs->offset, data);
  634. break;
  635. }
  636. cache = 0;
  637. }
  638. config_regs++;
  639. }
  640. return 0;
  641. }
  642. static int ci_enable_didt(struct amdgpu_device *adev, bool enable)
  643. {
  644. struct ci_power_info *pi = ci_get_pi(adev);
  645. int ret;
  646. if (pi->caps_sq_ramping || pi->caps_db_ramping ||
  647. pi->caps_td_ramping || pi->caps_tcp_ramping) {
  648. adev->gfx.rlc.funcs->enter_safe_mode(adev);
  649. if (enable) {
  650. ret = ci_program_pt_config_registers(adev, didt_config_ci);
  651. if (ret) {
  652. adev->gfx.rlc.funcs->exit_safe_mode(adev);
  653. return ret;
  654. }
  655. }
  656. ci_do_enable_didt(adev, enable);
  657. adev->gfx.rlc.funcs->exit_safe_mode(adev);
  658. }
  659. return 0;
  660. }
  661. static int ci_enable_power_containment(struct amdgpu_device *adev, bool enable)
  662. {
  663. struct ci_power_info *pi = ci_get_pi(adev);
  664. PPSMC_Result smc_result;
  665. int ret = 0;
  666. if (enable) {
  667. pi->power_containment_features = 0;
  668. if (pi->caps_power_containment) {
  669. if (pi->enable_bapm_feature) {
  670. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
  671. if (smc_result != PPSMC_Result_OK)
  672. ret = -EINVAL;
  673. else
  674. pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
  675. }
  676. if (pi->enable_tdc_limit_feature) {
  677. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitEnable);
  678. if (smc_result != PPSMC_Result_OK)
  679. ret = -EINVAL;
  680. else
  681. pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
  682. }
  683. if (pi->enable_pkg_pwr_tracking_feature) {
  684. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitEnable);
  685. if (smc_result != PPSMC_Result_OK) {
  686. ret = -EINVAL;
  687. } else {
  688. struct amdgpu_cac_tdp_table *cac_tdp_table =
  689. adev->pm.dpm.dyn_state.cac_tdp_table;
  690. u32 default_pwr_limit =
  691. (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
  692. pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
  693. ci_set_power_limit(adev, default_pwr_limit);
  694. }
  695. }
  696. }
  697. } else {
  698. if (pi->caps_power_containment && pi->power_containment_features) {
  699. if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
  700. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_TDCLimitDisable);
  701. if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
  702. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
  703. if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
  704. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PkgPwrLimitDisable);
  705. pi->power_containment_features = 0;
  706. }
  707. }
  708. return ret;
  709. }
  710. static int ci_enable_smc_cac(struct amdgpu_device *adev, bool enable)
  711. {
  712. struct ci_power_info *pi = ci_get_pi(adev);
  713. PPSMC_Result smc_result;
  714. int ret = 0;
  715. if (pi->caps_cac) {
  716. if (enable) {
  717. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
  718. if (smc_result != PPSMC_Result_OK) {
  719. ret = -EINVAL;
  720. pi->cac_enabled = false;
  721. } else {
  722. pi->cac_enabled = true;
  723. }
  724. } else if (pi->cac_enabled) {
  725. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
  726. pi->cac_enabled = false;
  727. }
  728. }
  729. return ret;
  730. }
  731. static int ci_enable_thermal_based_sclk_dpm(struct amdgpu_device *adev,
  732. bool enable)
  733. {
  734. struct ci_power_info *pi = ci_get_pi(adev);
  735. PPSMC_Result smc_result = PPSMC_Result_OK;
  736. if (pi->thermal_sclk_dpm_enabled) {
  737. if (enable)
  738. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ENABLE_THERMAL_DPM);
  739. else
  740. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DISABLE_THERMAL_DPM);
  741. }
  742. if (smc_result == PPSMC_Result_OK)
  743. return 0;
  744. else
  745. return -EINVAL;
  746. }
  747. static int ci_power_control_set_level(struct amdgpu_device *adev)
  748. {
  749. struct ci_power_info *pi = ci_get_pi(adev);
  750. struct amdgpu_cac_tdp_table *cac_tdp_table =
  751. adev->pm.dpm.dyn_state.cac_tdp_table;
  752. s32 adjust_percent;
  753. s32 target_tdp;
  754. int ret = 0;
  755. bool adjust_polarity = false; /* ??? */
  756. if (pi->caps_power_containment) {
  757. adjust_percent = adjust_polarity ?
  758. adev->pm.dpm.tdp_adjustment : (-1 * adev->pm.dpm.tdp_adjustment);
  759. target_tdp = ((100 + adjust_percent) *
  760. (s32)cac_tdp_table->configurable_tdp) / 100;
  761. ret = ci_set_overdrive_target_tdp(adev, (u32)target_tdp);
  762. }
  763. return ret;
  764. }
  765. static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate)
  766. {
  767. struct ci_power_info *pi = ci_get_pi(adev);
  768. pi->uvd_power_gated = gate;
  769. if (gate) {
  770. /* stop the UVD block */
  771. amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
  772. AMD_PG_STATE_GATE);
  773. ci_update_uvd_dpm(adev, gate);
  774. } else {
  775. amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
  776. AMD_PG_STATE_UNGATE);
  777. ci_update_uvd_dpm(adev, gate);
  778. }
  779. }
  780. static bool ci_dpm_vblank_too_short(struct amdgpu_device *adev)
  781. {
  782. u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
  783. u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300;
  784. /* disable mclk switching if the refresh is >120Hz, even if the
  785. * blanking period would allow it
  786. */
  787. if (amdgpu_dpm_get_vrefresh(adev) > 120)
  788. return true;
  789. if (vblank_time < switch_limit)
  790. return true;
  791. else
  792. return false;
  793. }
  794. static void ci_apply_state_adjust_rules(struct amdgpu_device *adev,
  795. struct amdgpu_ps *rps)
  796. {
  797. struct ci_ps *ps = ci_get_ps(rps);
  798. struct ci_power_info *pi = ci_get_pi(adev);
  799. struct amdgpu_clock_and_voltage_limits *max_limits;
  800. bool disable_mclk_switching;
  801. u32 sclk, mclk;
  802. int i;
  803. if (rps->vce_active) {
  804. rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
  805. rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
  806. } else {
  807. rps->evclk = 0;
  808. rps->ecclk = 0;
  809. }
  810. if ((adev->pm.dpm.new_active_crtc_count > 1) ||
  811. ci_dpm_vblank_too_short(adev))
  812. disable_mclk_switching = true;
  813. else
  814. disable_mclk_switching = false;
  815. if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
  816. pi->battery_state = true;
  817. else
  818. pi->battery_state = false;
  819. if (adev->pm.dpm.ac_power)
  820. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  821. else
  822. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
  823. if (adev->pm.dpm.ac_power == false) {
  824. for (i = 0; i < ps->performance_level_count; i++) {
  825. if (ps->performance_levels[i].mclk > max_limits->mclk)
  826. ps->performance_levels[i].mclk = max_limits->mclk;
  827. if (ps->performance_levels[i].sclk > max_limits->sclk)
  828. ps->performance_levels[i].sclk = max_limits->sclk;
  829. }
  830. }
  831. /* XXX validate the min clocks required for display */
  832. if (disable_mclk_switching) {
  833. mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
  834. sclk = ps->performance_levels[0].sclk;
  835. } else {
  836. mclk = ps->performance_levels[0].mclk;
  837. sclk = ps->performance_levels[0].sclk;
  838. }
  839. if (adev->pm.pm_display_cfg.min_core_set_clock > sclk)
  840. sclk = adev->pm.pm_display_cfg.min_core_set_clock;
  841. if (adev->pm.pm_display_cfg.min_mem_set_clock > mclk)
  842. mclk = adev->pm.pm_display_cfg.min_mem_set_clock;
  843. if (rps->vce_active) {
  844. if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
  845. sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
  846. if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
  847. mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
  848. }
  849. ps->performance_levels[0].sclk = sclk;
  850. ps->performance_levels[0].mclk = mclk;
  851. if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
  852. ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
  853. if (disable_mclk_switching) {
  854. if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
  855. ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
  856. } else {
  857. if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
  858. ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
  859. }
  860. }
  861. static int ci_thermal_set_temperature_range(struct amdgpu_device *adev,
  862. int min_temp, int max_temp)
  863. {
  864. int low_temp = 0 * 1000;
  865. int high_temp = 255 * 1000;
  866. u32 tmp;
  867. if (low_temp < min_temp)
  868. low_temp = min_temp;
  869. if (high_temp > max_temp)
  870. high_temp = max_temp;
  871. if (high_temp < low_temp) {
  872. DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
  873. return -EINVAL;
  874. }
  875. tmp = RREG32_SMC(ixCG_THERMAL_INT);
  876. tmp &= ~(CG_THERMAL_INT__DIG_THERM_INTH_MASK | CG_THERMAL_INT__DIG_THERM_INTL_MASK);
  877. tmp |= ((high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT) |
  878. ((low_temp / 1000)) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT;
  879. WREG32_SMC(ixCG_THERMAL_INT, tmp);
  880. #if 0
  881. /* XXX: need to figure out how to handle this properly */
  882. tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
  883. tmp &= DIG_THERM_DPM_MASK;
  884. tmp |= DIG_THERM_DPM(high_temp / 1000);
  885. WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
  886. #endif
  887. adev->pm.dpm.thermal.min_temp = low_temp;
  888. adev->pm.dpm.thermal.max_temp = high_temp;
  889. return 0;
  890. }
  891. static int ci_thermal_enable_alert(struct amdgpu_device *adev,
  892. bool enable)
  893. {
  894. u32 thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
  895. PPSMC_Result result;
  896. if (enable) {
  897. thermal_int &= ~(CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
  898. CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
  899. WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
  900. result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Enable);
  901. if (result != PPSMC_Result_OK) {
  902. DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
  903. return -EINVAL;
  904. }
  905. } else {
  906. thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK |
  907. CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
  908. WREG32_SMC(ixCG_THERMAL_INT, thermal_int);
  909. result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Thermal_Cntl_Disable);
  910. if (result != PPSMC_Result_OK) {
  911. DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
  912. return -EINVAL;
  913. }
  914. }
  915. return 0;
  916. }
  917. static void ci_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
  918. {
  919. struct ci_power_info *pi = ci_get_pi(adev);
  920. u32 tmp;
  921. if (pi->fan_ctrl_is_in_default_mode) {
  922. tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK)
  923. >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
  924. pi->fan_ctrl_default_mode = tmp;
  925. tmp = (RREG32_SMC(ixCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK)
  926. >> CG_FDO_CTRL2__TMIN__SHIFT;
  927. pi->t_min = tmp;
  928. pi->fan_ctrl_is_in_default_mode = false;
  929. }
  930. tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
  931. tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT;
  932. WREG32_SMC(ixCG_FDO_CTRL2, tmp);
  933. tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
  934. tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
  935. WREG32_SMC(ixCG_FDO_CTRL2, tmp);
  936. }
  937. static int ci_thermal_setup_fan_table(struct amdgpu_device *adev)
  938. {
  939. struct ci_power_info *pi = ci_get_pi(adev);
  940. SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
  941. u32 duty100;
  942. u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
  943. u16 fdo_min, slope1, slope2;
  944. u32 reference_clock, tmp;
  945. int ret;
  946. u64 tmp64;
  947. if (!pi->fan_table_start) {
  948. adev->pm.dpm.fan.ucode_fan_control = false;
  949. return 0;
  950. }
  951. duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
  952. >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
  953. if (duty100 == 0) {
  954. adev->pm.dpm.fan.ucode_fan_control = false;
  955. return 0;
  956. }
  957. tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
  958. do_div(tmp64, 10000);
  959. fdo_min = (u16)tmp64;
  960. t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
  961. t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
  962. pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
  963. pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
  964. slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
  965. slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
  966. fan_table.TempMin = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
  967. fan_table.TempMed = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
  968. fan_table.TempMax = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
  969. fan_table.Slope1 = cpu_to_be16(slope1);
  970. fan_table.Slope2 = cpu_to_be16(slope2);
  971. fan_table.FdoMin = cpu_to_be16(fdo_min);
  972. fan_table.HystDown = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
  973. fan_table.HystUp = cpu_to_be16(1);
  974. fan_table.HystSlope = cpu_to_be16(1);
  975. fan_table.TempRespLim = cpu_to_be16(5);
  976. reference_clock = amdgpu_asic_get_xclk(adev);
  977. fan_table.RefreshPeriod = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
  978. reference_clock) / 1600);
  979. fan_table.FdoMax = cpu_to_be16((u16)duty100);
  980. tmp = (RREG32_SMC(ixCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK)
  981. >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT;
  982. fan_table.TempSrc = (uint8_t)tmp;
  983. ret = amdgpu_ci_copy_bytes_to_smc(adev,
  984. pi->fan_table_start,
  985. (u8 *)(&fan_table),
  986. sizeof(fan_table),
  987. pi->sram_end);
  988. if (ret) {
  989. DRM_ERROR("Failed to load fan table to the SMC.");
  990. adev->pm.dpm.fan.ucode_fan_control = false;
  991. }
  992. return 0;
  993. }
  994. static int ci_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
  995. {
  996. struct ci_power_info *pi = ci_get_pi(adev);
  997. PPSMC_Result ret;
  998. if (pi->caps_od_fuzzy_fan_control_support) {
  999. ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  1000. PPSMC_StartFanControl,
  1001. FAN_CONTROL_FUZZY);
  1002. if (ret != PPSMC_Result_OK)
  1003. return -EINVAL;
  1004. ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  1005. PPSMC_MSG_SetFanPwmMax,
  1006. adev->pm.dpm.fan.default_max_fan_pwm);
  1007. if (ret != PPSMC_Result_OK)
  1008. return -EINVAL;
  1009. } else {
  1010. ret = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  1011. PPSMC_StartFanControl,
  1012. FAN_CONTROL_TABLE);
  1013. if (ret != PPSMC_Result_OK)
  1014. return -EINVAL;
  1015. }
  1016. pi->fan_is_controlled_by_smc = true;
  1017. return 0;
  1018. }
  1019. static int ci_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
  1020. {
  1021. PPSMC_Result ret;
  1022. struct ci_power_info *pi = ci_get_pi(adev);
  1023. ret = amdgpu_ci_send_msg_to_smc(adev, PPSMC_StopFanControl);
  1024. if (ret == PPSMC_Result_OK) {
  1025. pi->fan_is_controlled_by_smc = false;
  1026. return 0;
  1027. } else {
  1028. return -EINVAL;
  1029. }
  1030. }
  1031. static int ci_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
  1032. u32 *speed)
  1033. {
  1034. u32 duty, duty100;
  1035. u64 tmp64;
  1036. if (adev->pm.no_fan)
  1037. return -ENOENT;
  1038. duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
  1039. >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
  1040. duty = (RREG32_SMC(ixCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK)
  1041. >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT;
  1042. if (duty100 == 0)
  1043. return -EINVAL;
  1044. tmp64 = (u64)duty * 100;
  1045. do_div(tmp64, duty100);
  1046. *speed = (u32)tmp64;
  1047. if (*speed > 100)
  1048. *speed = 100;
  1049. return 0;
  1050. }
  1051. static int ci_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
  1052. u32 speed)
  1053. {
  1054. u32 tmp;
  1055. u32 duty, duty100;
  1056. u64 tmp64;
  1057. struct ci_power_info *pi = ci_get_pi(adev);
  1058. if (adev->pm.no_fan)
  1059. return -ENOENT;
  1060. if (pi->fan_is_controlled_by_smc)
  1061. return -EINVAL;
  1062. if (speed > 100)
  1063. return -EINVAL;
  1064. duty100 = (RREG32_SMC(ixCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK)
  1065. >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
  1066. if (duty100 == 0)
  1067. return -EINVAL;
  1068. tmp64 = (u64)speed * duty100;
  1069. do_div(tmp64, 100);
  1070. duty = (u32)tmp64;
  1071. tmp = RREG32_SMC(ixCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK;
  1072. tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT;
  1073. WREG32_SMC(ixCG_FDO_CTRL0, tmp);
  1074. return 0;
  1075. }
  1076. static void ci_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
  1077. {
  1078. switch (mode) {
  1079. case AMD_FAN_CTRL_NONE:
  1080. if (adev->pm.dpm.fan.ucode_fan_control)
  1081. ci_fan_ctrl_stop_smc_fan_control(adev);
  1082. ci_dpm_set_fan_speed_percent(adev, 100);
  1083. break;
  1084. case AMD_FAN_CTRL_MANUAL:
  1085. if (adev->pm.dpm.fan.ucode_fan_control)
  1086. ci_fan_ctrl_stop_smc_fan_control(adev);
  1087. break;
  1088. case AMD_FAN_CTRL_AUTO:
  1089. if (adev->pm.dpm.fan.ucode_fan_control)
  1090. ci_thermal_start_smc_fan_control(adev);
  1091. break;
  1092. default:
  1093. break;
  1094. }
  1095. }
  1096. static u32 ci_dpm_get_fan_control_mode(struct amdgpu_device *adev)
  1097. {
  1098. struct ci_power_info *pi = ci_get_pi(adev);
  1099. if (pi->fan_is_controlled_by_smc)
  1100. return AMD_FAN_CTRL_AUTO;
  1101. else
  1102. return AMD_FAN_CTRL_MANUAL;
  1103. }
  1104. #if 0
  1105. static int ci_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
  1106. u32 *speed)
  1107. {
  1108. u32 tach_period;
  1109. u32 xclk = amdgpu_asic_get_xclk(adev);
  1110. if (adev->pm.no_fan)
  1111. return -ENOENT;
  1112. if (adev->pm.fan_pulses_per_revolution == 0)
  1113. return -ENOENT;
  1114. tach_period = (RREG32_SMC(ixCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK)
  1115. >> CG_TACH_STATUS__TACH_PERIOD__SHIFT;
  1116. if (tach_period == 0)
  1117. return -ENOENT;
  1118. *speed = 60 * xclk * 10000 / tach_period;
  1119. return 0;
  1120. }
  1121. static int ci_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
  1122. u32 speed)
  1123. {
  1124. u32 tach_period, tmp;
  1125. u32 xclk = amdgpu_asic_get_xclk(adev);
  1126. if (adev->pm.no_fan)
  1127. return -ENOENT;
  1128. if (adev->pm.fan_pulses_per_revolution == 0)
  1129. return -ENOENT;
  1130. if ((speed < adev->pm.fan_min_rpm) ||
  1131. (speed > adev->pm.fan_max_rpm))
  1132. return -EINVAL;
  1133. if (adev->pm.dpm.fan.ucode_fan_control)
  1134. ci_fan_ctrl_stop_smc_fan_control(adev);
  1135. tach_period = 60 * xclk * 10000 / (8 * speed);
  1136. tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK;
  1137. tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT;
  1138. WREG32_SMC(CG_TACH_CTRL, tmp);
  1139. ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
  1140. return 0;
  1141. }
  1142. #endif
  1143. static void ci_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
  1144. {
  1145. struct ci_power_info *pi = ci_get_pi(adev);
  1146. u32 tmp;
  1147. if (!pi->fan_ctrl_is_in_default_mode) {
  1148. tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK;
  1149. tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;
  1150. WREG32_SMC(ixCG_FDO_CTRL2, tmp);
  1151. tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK;
  1152. tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;
  1153. WREG32_SMC(ixCG_FDO_CTRL2, tmp);
  1154. pi->fan_ctrl_is_in_default_mode = true;
  1155. }
  1156. }
  1157. static void ci_thermal_start_smc_fan_control(struct amdgpu_device *adev)
  1158. {
  1159. if (adev->pm.dpm.fan.ucode_fan_control) {
  1160. ci_fan_ctrl_start_smc_fan_control(adev);
  1161. ci_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
  1162. }
  1163. }
  1164. static void ci_thermal_initialize(struct amdgpu_device *adev)
  1165. {
  1166. u32 tmp;
  1167. if (adev->pm.fan_pulses_per_revolution) {
  1168. tmp = RREG32_SMC(ixCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK;
  1169. tmp |= (adev->pm.fan_pulses_per_revolution - 1)
  1170. << CG_TACH_CTRL__EDGE_PER_REV__SHIFT;
  1171. WREG32_SMC(ixCG_TACH_CTRL, tmp);
  1172. }
  1173. tmp = RREG32_SMC(ixCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK;
  1174. tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT;
  1175. WREG32_SMC(ixCG_FDO_CTRL2, tmp);
  1176. }
  1177. static int ci_thermal_start_thermal_controller(struct amdgpu_device *adev)
  1178. {
  1179. int ret;
  1180. ci_thermal_initialize(adev);
  1181. ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN, CISLANDS_TEMP_RANGE_MAX);
  1182. if (ret)
  1183. return ret;
  1184. ret = ci_thermal_enable_alert(adev, true);
  1185. if (ret)
  1186. return ret;
  1187. if (adev->pm.dpm.fan.ucode_fan_control) {
  1188. ret = ci_thermal_setup_fan_table(adev);
  1189. if (ret)
  1190. return ret;
  1191. ci_thermal_start_smc_fan_control(adev);
  1192. }
  1193. return 0;
  1194. }
  1195. static void ci_thermal_stop_thermal_controller(struct amdgpu_device *adev)
  1196. {
  1197. if (!adev->pm.no_fan)
  1198. ci_fan_ctrl_set_default_mode(adev);
  1199. }
  1200. static int ci_read_smc_soft_register(struct amdgpu_device *adev,
  1201. u16 reg_offset, u32 *value)
  1202. {
  1203. struct ci_power_info *pi = ci_get_pi(adev);
  1204. return amdgpu_ci_read_smc_sram_dword(adev,
  1205. pi->soft_regs_start + reg_offset,
  1206. value, pi->sram_end);
  1207. }
  1208. static int ci_write_smc_soft_register(struct amdgpu_device *adev,
  1209. u16 reg_offset, u32 value)
  1210. {
  1211. struct ci_power_info *pi = ci_get_pi(adev);
  1212. return amdgpu_ci_write_smc_sram_dword(adev,
  1213. pi->soft_regs_start + reg_offset,
  1214. value, pi->sram_end);
  1215. }
  1216. static void ci_init_fps_limits(struct amdgpu_device *adev)
  1217. {
  1218. struct ci_power_info *pi = ci_get_pi(adev);
  1219. SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
  1220. if (pi->caps_fps) {
  1221. u16 tmp;
  1222. tmp = 45;
  1223. table->FpsHighT = cpu_to_be16(tmp);
  1224. tmp = 30;
  1225. table->FpsLowT = cpu_to_be16(tmp);
  1226. }
  1227. }
  1228. static int ci_update_sclk_t(struct amdgpu_device *adev)
  1229. {
  1230. struct ci_power_info *pi = ci_get_pi(adev);
  1231. int ret = 0;
  1232. u32 low_sclk_interrupt_t = 0;
  1233. if (pi->caps_sclk_throttle_low_notification) {
  1234. low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
  1235. ret = amdgpu_ci_copy_bytes_to_smc(adev,
  1236. pi->dpm_table_start +
  1237. offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
  1238. (u8 *)&low_sclk_interrupt_t,
  1239. sizeof(u32), pi->sram_end);
  1240. }
  1241. return ret;
  1242. }
  1243. static void ci_get_leakage_voltages(struct amdgpu_device *adev)
  1244. {
  1245. struct ci_power_info *pi = ci_get_pi(adev);
  1246. u16 leakage_id, virtual_voltage_id;
  1247. u16 vddc, vddci;
  1248. int i;
  1249. pi->vddc_leakage.count = 0;
  1250. pi->vddci_leakage.count = 0;
  1251. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
  1252. for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
  1253. virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
  1254. if (amdgpu_atombios_get_voltage_evv(adev, virtual_voltage_id, &vddc) != 0)
  1255. continue;
  1256. if (vddc != 0 && vddc != virtual_voltage_id) {
  1257. pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
  1258. pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
  1259. pi->vddc_leakage.count++;
  1260. }
  1261. }
  1262. } else if (amdgpu_atombios_get_leakage_id_from_vbios(adev, &leakage_id) == 0) {
  1263. for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
  1264. virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
  1265. if (amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(adev, &vddc, &vddci,
  1266. virtual_voltage_id,
  1267. leakage_id) == 0) {
  1268. if (vddc != 0 && vddc != virtual_voltage_id) {
  1269. pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
  1270. pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
  1271. pi->vddc_leakage.count++;
  1272. }
  1273. if (vddci != 0 && vddci != virtual_voltage_id) {
  1274. pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
  1275. pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
  1276. pi->vddci_leakage.count++;
  1277. }
  1278. }
  1279. }
  1280. }
  1281. }
  1282. static void ci_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
  1283. {
  1284. struct ci_power_info *pi = ci_get_pi(adev);
  1285. bool want_thermal_protection;
  1286. enum amdgpu_dpm_event_src dpm_event_src;
  1287. u32 tmp;
  1288. switch (sources) {
  1289. case 0:
  1290. default:
  1291. want_thermal_protection = false;
  1292. break;
  1293. case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
  1294. want_thermal_protection = true;
  1295. dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
  1296. break;
  1297. case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
  1298. want_thermal_protection = true;
  1299. dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
  1300. break;
  1301. case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
  1302. (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
  1303. want_thermal_protection = true;
  1304. dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
  1305. break;
  1306. }
  1307. if (want_thermal_protection) {
  1308. #if 0
  1309. /* XXX: need to figure out how to handle this properly */
  1310. tmp = RREG32_SMC(ixCG_THERMAL_CTRL);
  1311. tmp &= DPM_EVENT_SRC_MASK;
  1312. tmp |= DPM_EVENT_SRC(dpm_event_src);
  1313. WREG32_SMC(ixCG_THERMAL_CTRL, tmp);
  1314. #endif
  1315. tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1316. if (pi->thermal_protection)
  1317. tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
  1318. else
  1319. tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
  1320. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1321. } else {
  1322. tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1323. tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
  1324. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1325. }
  1326. }
  1327. static void ci_enable_auto_throttle_source(struct amdgpu_device *adev,
  1328. enum amdgpu_dpm_auto_throttle_src source,
  1329. bool enable)
  1330. {
  1331. struct ci_power_info *pi = ci_get_pi(adev);
  1332. if (enable) {
  1333. if (!(pi->active_auto_throttle_sources & (1 << source))) {
  1334. pi->active_auto_throttle_sources |= 1 << source;
  1335. ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
  1336. }
  1337. } else {
  1338. if (pi->active_auto_throttle_sources & (1 << source)) {
  1339. pi->active_auto_throttle_sources &= ~(1 << source);
  1340. ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
  1341. }
  1342. }
  1343. }
  1344. static void ci_enable_vr_hot_gpio_interrupt(struct amdgpu_device *adev)
  1345. {
  1346. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
  1347. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
  1348. }
  1349. static int ci_unfreeze_sclk_mclk_dpm(struct amdgpu_device *adev)
  1350. {
  1351. struct ci_power_info *pi = ci_get_pi(adev);
  1352. PPSMC_Result smc_result;
  1353. if (!pi->need_update_smu7_dpm_table)
  1354. return 0;
  1355. if ((!pi->sclk_dpm_key_disabled) &&
  1356. (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
  1357. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
  1358. if (smc_result != PPSMC_Result_OK)
  1359. return -EINVAL;
  1360. }
  1361. if ((!pi->mclk_dpm_key_disabled) &&
  1362. (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
  1363. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
  1364. if (smc_result != PPSMC_Result_OK)
  1365. return -EINVAL;
  1366. }
  1367. pi->need_update_smu7_dpm_table = 0;
  1368. return 0;
  1369. }
  1370. static int ci_enable_sclk_mclk_dpm(struct amdgpu_device *adev, bool enable)
  1371. {
  1372. struct ci_power_info *pi = ci_get_pi(adev);
  1373. PPSMC_Result smc_result;
  1374. if (enable) {
  1375. if (!pi->sclk_dpm_key_disabled) {
  1376. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Enable);
  1377. if (smc_result != PPSMC_Result_OK)
  1378. return -EINVAL;
  1379. }
  1380. if (!pi->mclk_dpm_key_disabled) {
  1381. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Enable);
  1382. if (smc_result != PPSMC_Result_OK)
  1383. return -EINVAL;
  1384. WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK,
  1385. ~MC_SEQ_CNTL_3__CAC_EN_MASK);
  1386. WREG32_SMC(ixLCAC_MC0_CNTL, 0x05);
  1387. WREG32_SMC(ixLCAC_MC1_CNTL, 0x05);
  1388. WREG32_SMC(ixLCAC_CPL_CNTL, 0x100005);
  1389. udelay(10);
  1390. WREG32_SMC(ixLCAC_MC0_CNTL, 0x400005);
  1391. WREG32_SMC(ixLCAC_MC1_CNTL, 0x400005);
  1392. WREG32_SMC(ixLCAC_CPL_CNTL, 0x500005);
  1393. }
  1394. } else {
  1395. if (!pi->sclk_dpm_key_disabled) {
  1396. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DPM_Disable);
  1397. if (smc_result != PPSMC_Result_OK)
  1398. return -EINVAL;
  1399. }
  1400. if (!pi->mclk_dpm_key_disabled) {
  1401. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_Disable);
  1402. if (smc_result != PPSMC_Result_OK)
  1403. return -EINVAL;
  1404. }
  1405. }
  1406. return 0;
  1407. }
  1408. static int ci_start_dpm(struct amdgpu_device *adev)
  1409. {
  1410. struct ci_power_info *pi = ci_get_pi(adev);
  1411. PPSMC_Result smc_result;
  1412. int ret;
  1413. u32 tmp;
  1414. tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1415. tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
  1416. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1417. tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  1418. tmp |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
  1419. WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
  1420. ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
  1421. WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK);
  1422. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Enable);
  1423. if (smc_result != PPSMC_Result_OK)
  1424. return -EINVAL;
  1425. ret = ci_enable_sclk_mclk_dpm(adev, true);
  1426. if (ret)
  1427. return ret;
  1428. if (!pi->pcie_dpm_key_disabled) {
  1429. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Enable);
  1430. if (smc_result != PPSMC_Result_OK)
  1431. return -EINVAL;
  1432. }
  1433. return 0;
  1434. }
  1435. static int ci_freeze_sclk_mclk_dpm(struct amdgpu_device *adev)
  1436. {
  1437. struct ci_power_info *pi = ci_get_pi(adev);
  1438. PPSMC_Result smc_result;
  1439. if (!pi->need_update_smu7_dpm_table)
  1440. return 0;
  1441. if ((!pi->sclk_dpm_key_disabled) &&
  1442. (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
  1443. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_SCLKDPM_FreezeLevel);
  1444. if (smc_result != PPSMC_Result_OK)
  1445. return -EINVAL;
  1446. }
  1447. if ((!pi->mclk_dpm_key_disabled) &&
  1448. (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
  1449. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MCLKDPM_FreezeLevel);
  1450. if (smc_result != PPSMC_Result_OK)
  1451. return -EINVAL;
  1452. }
  1453. return 0;
  1454. }
  1455. static int ci_stop_dpm(struct amdgpu_device *adev)
  1456. {
  1457. struct ci_power_info *pi = ci_get_pi(adev);
  1458. PPSMC_Result smc_result;
  1459. int ret;
  1460. u32 tmp;
  1461. tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1462. tmp &= ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
  1463. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1464. tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  1465. tmp &= ~SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
  1466. WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
  1467. if (!pi->pcie_dpm_key_disabled) {
  1468. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_Disable);
  1469. if (smc_result != PPSMC_Result_OK)
  1470. return -EINVAL;
  1471. }
  1472. ret = ci_enable_sclk_mclk_dpm(adev, false);
  1473. if (ret)
  1474. return ret;
  1475. smc_result = amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Voltage_Cntl_Disable);
  1476. if (smc_result != PPSMC_Result_OK)
  1477. return -EINVAL;
  1478. return 0;
  1479. }
  1480. static void ci_enable_sclk_control(struct amdgpu_device *adev, bool enable)
  1481. {
  1482. u32 tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  1483. if (enable)
  1484. tmp &= ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
  1485. else
  1486. tmp |= SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK;
  1487. WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
  1488. }
  1489. #if 0
  1490. static int ci_notify_hw_of_power_source(struct amdgpu_device *adev,
  1491. bool ac_power)
  1492. {
  1493. struct ci_power_info *pi = ci_get_pi(adev);
  1494. struct amdgpu_cac_tdp_table *cac_tdp_table =
  1495. adev->pm.dpm.dyn_state.cac_tdp_table;
  1496. u32 power_limit;
  1497. if (ac_power)
  1498. power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
  1499. else
  1500. power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
  1501. ci_set_power_limit(adev, power_limit);
  1502. if (pi->caps_automatic_dc_transition) {
  1503. if (ac_power)
  1504. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC);
  1505. else
  1506. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_Remove_DC_Clamp);
  1507. }
  1508. return 0;
  1509. }
  1510. #endif
  1511. static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
  1512. PPSMC_Msg msg, u32 parameter)
  1513. {
  1514. WREG32(mmSMC_MSG_ARG_0, parameter);
  1515. return amdgpu_ci_send_msg_to_smc(adev, msg);
  1516. }
  1517. static PPSMC_Result amdgpu_ci_send_msg_to_smc_return_parameter(struct amdgpu_device *adev,
  1518. PPSMC_Msg msg, u32 *parameter)
  1519. {
  1520. PPSMC_Result smc_result;
  1521. smc_result = amdgpu_ci_send_msg_to_smc(adev, msg);
  1522. if ((smc_result == PPSMC_Result_OK) && parameter)
  1523. *parameter = RREG32(mmSMC_MSG_ARG_0);
  1524. return smc_result;
  1525. }
  1526. static int ci_dpm_force_state_sclk(struct amdgpu_device *adev, u32 n)
  1527. {
  1528. struct ci_power_info *pi = ci_get_pi(adev);
  1529. if (!pi->sclk_dpm_key_disabled) {
  1530. PPSMC_Result smc_result =
  1531. amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
  1532. if (smc_result != PPSMC_Result_OK)
  1533. return -EINVAL;
  1534. }
  1535. return 0;
  1536. }
  1537. static int ci_dpm_force_state_mclk(struct amdgpu_device *adev, u32 n)
  1538. {
  1539. struct ci_power_info *pi = ci_get_pi(adev);
  1540. if (!pi->mclk_dpm_key_disabled) {
  1541. PPSMC_Result smc_result =
  1542. amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
  1543. if (smc_result != PPSMC_Result_OK)
  1544. return -EINVAL;
  1545. }
  1546. return 0;
  1547. }
  1548. static int ci_dpm_force_state_pcie(struct amdgpu_device *adev, u32 n)
  1549. {
  1550. struct ci_power_info *pi = ci_get_pi(adev);
  1551. if (!pi->pcie_dpm_key_disabled) {
  1552. PPSMC_Result smc_result =
  1553. amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
  1554. if (smc_result != PPSMC_Result_OK)
  1555. return -EINVAL;
  1556. }
  1557. return 0;
  1558. }
  1559. static int ci_set_power_limit(struct amdgpu_device *adev, u32 n)
  1560. {
  1561. struct ci_power_info *pi = ci_get_pi(adev);
  1562. if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
  1563. PPSMC_Result smc_result =
  1564. amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_PkgPwrSetLimit, n);
  1565. if (smc_result != PPSMC_Result_OK)
  1566. return -EINVAL;
  1567. }
  1568. return 0;
  1569. }
  1570. static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
  1571. u32 target_tdp)
  1572. {
  1573. PPSMC_Result smc_result =
  1574. amdgpu_ci_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
  1575. if (smc_result != PPSMC_Result_OK)
  1576. return -EINVAL;
  1577. return 0;
  1578. }
  1579. #if 0
  1580. static int ci_set_boot_state(struct amdgpu_device *adev)
  1581. {
  1582. return ci_enable_sclk_mclk_dpm(adev, false);
  1583. }
  1584. #endif
  1585. static u32 ci_get_average_sclk_freq(struct amdgpu_device *adev)
  1586. {
  1587. u32 sclk_freq;
  1588. PPSMC_Result smc_result =
  1589. amdgpu_ci_send_msg_to_smc_return_parameter(adev,
  1590. PPSMC_MSG_API_GetSclkFrequency,
  1591. &sclk_freq);
  1592. if (smc_result != PPSMC_Result_OK)
  1593. sclk_freq = 0;
  1594. return sclk_freq;
  1595. }
  1596. static u32 ci_get_average_mclk_freq(struct amdgpu_device *adev)
  1597. {
  1598. u32 mclk_freq;
  1599. PPSMC_Result smc_result =
  1600. amdgpu_ci_send_msg_to_smc_return_parameter(adev,
  1601. PPSMC_MSG_API_GetMclkFrequency,
  1602. &mclk_freq);
  1603. if (smc_result != PPSMC_Result_OK)
  1604. mclk_freq = 0;
  1605. return mclk_freq;
  1606. }
  1607. static void ci_dpm_start_smc(struct amdgpu_device *adev)
  1608. {
  1609. int i;
  1610. amdgpu_ci_program_jump_on_start(adev);
  1611. amdgpu_ci_start_smc_clock(adev);
  1612. amdgpu_ci_start_smc(adev);
  1613. for (i = 0; i < adev->usec_timeout; i++) {
  1614. if (RREG32_SMC(ixFIRMWARE_FLAGS) & FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
  1615. break;
  1616. }
  1617. }
  1618. static void ci_dpm_stop_smc(struct amdgpu_device *adev)
  1619. {
  1620. amdgpu_ci_reset_smc(adev);
  1621. amdgpu_ci_stop_smc_clock(adev);
  1622. }
  1623. static int ci_process_firmware_header(struct amdgpu_device *adev)
  1624. {
  1625. struct ci_power_info *pi = ci_get_pi(adev);
  1626. u32 tmp;
  1627. int ret;
  1628. ret = amdgpu_ci_read_smc_sram_dword(adev,
  1629. SMU7_FIRMWARE_HEADER_LOCATION +
  1630. offsetof(SMU7_Firmware_Header, DpmTable),
  1631. &tmp, pi->sram_end);
  1632. if (ret)
  1633. return ret;
  1634. pi->dpm_table_start = tmp;
  1635. ret = amdgpu_ci_read_smc_sram_dword(adev,
  1636. SMU7_FIRMWARE_HEADER_LOCATION +
  1637. offsetof(SMU7_Firmware_Header, SoftRegisters),
  1638. &tmp, pi->sram_end);
  1639. if (ret)
  1640. return ret;
  1641. pi->soft_regs_start = tmp;
  1642. ret = amdgpu_ci_read_smc_sram_dword(adev,
  1643. SMU7_FIRMWARE_HEADER_LOCATION +
  1644. offsetof(SMU7_Firmware_Header, mcRegisterTable),
  1645. &tmp, pi->sram_end);
  1646. if (ret)
  1647. return ret;
  1648. pi->mc_reg_table_start = tmp;
  1649. ret = amdgpu_ci_read_smc_sram_dword(adev,
  1650. SMU7_FIRMWARE_HEADER_LOCATION +
  1651. offsetof(SMU7_Firmware_Header, FanTable),
  1652. &tmp, pi->sram_end);
  1653. if (ret)
  1654. return ret;
  1655. pi->fan_table_start = tmp;
  1656. ret = amdgpu_ci_read_smc_sram_dword(adev,
  1657. SMU7_FIRMWARE_HEADER_LOCATION +
  1658. offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
  1659. &tmp, pi->sram_end);
  1660. if (ret)
  1661. return ret;
  1662. pi->arb_table_start = tmp;
  1663. return 0;
  1664. }
  1665. static void ci_read_clock_registers(struct amdgpu_device *adev)
  1666. {
  1667. struct ci_power_info *pi = ci_get_pi(adev);
  1668. pi->clock_registers.cg_spll_func_cntl =
  1669. RREG32_SMC(ixCG_SPLL_FUNC_CNTL);
  1670. pi->clock_registers.cg_spll_func_cntl_2 =
  1671. RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2);
  1672. pi->clock_registers.cg_spll_func_cntl_3 =
  1673. RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3);
  1674. pi->clock_registers.cg_spll_func_cntl_4 =
  1675. RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4);
  1676. pi->clock_registers.cg_spll_spread_spectrum =
  1677. RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
  1678. pi->clock_registers.cg_spll_spread_spectrum_2 =
  1679. RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2);
  1680. pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
  1681. pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
  1682. pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
  1683. pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
  1684. pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
  1685. pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
  1686. pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
  1687. pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
  1688. pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
  1689. }
  1690. static void ci_init_sclk_t(struct amdgpu_device *adev)
  1691. {
  1692. struct ci_power_info *pi = ci_get_pi(adev);
  1693. pi->low_sclk_interrupt_t = 0;
  1694. }
  1695. static void ci_enable_thermal_protection(struct amdgpu_device *adev,
  1696. bool enable)
  1697. {
  1698. u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1699. if (enable)
  1700. tmp &= ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
  1701. else
  1702. tmp |= GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK;
  1703. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1704. }
  1705. static void ci_enable_acpi_power_management(struct amdgpu_device *adev)
  1706. {
  1707. u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1708. tmp |= GENERAL_PWRMGT__STATIC_PM_EN_MASK;
  1709. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1710. }
  1711. #if 0
  1712. static int ci_enter_ulp_state(struct amdgpu_device *adev)
  1713. {
  1714. WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
  1715. udelay(25000);
  1716. return 0;
  1717. }
  1718. static int ci_exit_ulp_state(struct amdgpu_device *adev)
  1719. {
  1720. int i;
  1721. WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
  1722. udelay(7000);
  1723. for (i = 0; i < adev->usec_timeout; i++) {
  1724. if (RREG32(mmSMC_RESP_0) == 1)
  1725. break;
  1726. udelay(1000);
  1727. }
  1728. return 0;
  1729. }
  1730. #endif
  1731. static int ci_notify_smc_display_change(struct amdgpu_device *adev,
  1732. bool has_display)
  1733. {
  1734. PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
  1735. return (amdgpu_ci_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
  1736. }
  1737. static int ci_enable_ds_master_switch(struct amdgpu_device *adev,
  1738. bool enable)
  1739. {
  1740. struct ci_power_info *pi = ci_get_pi(adev);
  1741. if (enable) {
  1742. if (pi->caps_sclk_ds) {
  1743. if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
  1744. return -EINVAL;
  1745. } else {
  1746. if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
  1747. return -EINVAL;
  1748. }
  1749. } else {
  1750. if (pi->caps_sclk_ds) {
  1751. if (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
  1752. return -EINVAL;
  1753. }
  1754. }
  1755. return 0;
  1756. }
  1757. static void ci_program_display_gap(struct amdgpu_device *adev)
  1758. {
  1759. u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
  1760. u32 pre_vbi_time_in_us;
  1761. u32 frame_time_in_us;
  1762. u32 ref_clock = adev->clock.spll.reference_freq;
  1763. u32 refresh_rate = amdgpu_dpm_get_vrefresh(adev);
  1764. u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
  1765. tmp &= ~CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK;
  1766. if (adev->pm.dpm.new_active_crtc_count > 0)
  1767. tmp |= (AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
  1768. else
  1769. tmp |= (AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT);
  1770. WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
  1771. if (refresh_rate == 0)
  1772. refresh_rate = 60;
  1773. if (vblank_time == 0xffffffff)
  1774. vblank_time = 500;
  1775. frame_time_in_us = 1000000 / refresh_rate;
  1776. pre_vbi_time_in_us =
  1777. frame_time_in_us - 200 - vblank_time;
  1778. tmp = pre_vbi_time_in_us * (ref_clock / 100);
  1779. WREG32_SMC(ixCG_DISPLAY_GAP_CNTL2, tmp);
  1780. ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
  1781. ci_write_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
  1782. ci_notify_smc_display_change(adev, (adev->pm.dpm.new_active_crtc_count == 1));
  1783. }
  1784. static void ci_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
  1785. {
  1786. struct ci_power_info *pi = ci_get_pi(adev);
  1787. u32 tmp;
  1788. if (enable) {
  1789. if (pi->caps_sclk_ss_support) {
  1790. tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1791. tmp |= GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
  1792. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1793. }
  1794. } else {
  1795. tmp = RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM);
  1796. tmp &= ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK;
  1797. WREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM, tmp);
  1798. tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  1799. tmp &= ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK;
  1800. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  1801. }
  1802. }
  1803. static void ci_program_sstp(struct amdgpu_device *adev)
  1804. {
  1805. WREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER,
  1806. ((CISLANDS_SSTU_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT) |
  1807. (CISLANDS_SST_DFLT << CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT)));
  1808. }
  1809. static void ci_enable_display_gap(struct amdgpu_device *adev)
  1810. {
  1811. u32 tmp = RREG32_SMC(ixCG_DISPLAY_GAP_CNTL);
  1812. tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK |
  1813. CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK);
  1814. tmp |= ((AMDGPU_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT) |
  1815. (AMDGPU_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT));
  1816. WREG32_SMC(ixCG_DISPLAY_GAP_CNTL, tmp);
  1817. }
  1818. static void ci_program_vc(struct amdgpu_device *adev)
  1819. {
  1820. u32 tmp;
  1821. tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  1822. tmp &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
  1823. WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
  1824. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, CISLANDS_VRC_DFLT0);
  1825. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, CISLANDS_VRC_DFLT1);
  1826. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, CISLANDS_VRC_DFLT2);
  1827. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, CISLANDS_VRC_DFLT3);
  1828. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, CISLANDS_VRC_DFLT4);
  1829. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, CISLANDS_VRC_DFLT5);
  1830. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, CISLANDS_VRC_DFLT6);
  1831. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, CISLANDS_VRC_DFLT7);
  1832. }
  1833. static void ci_clear_vc(struct amdgpu_device *adev)
  1834. {
  1835. u32 tmp;
  1836. tmp = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
  1837. tmp |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK | SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
  1838. WREG32_SMC(ixSCLK_PWRMGT_CNTL, tmp);
  1839. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
  1840. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_1, 0);
  1841. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_2, 0);
  1842. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_3, 0);
  1843. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_4, 0);
  1844. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_5, 0);
  1845. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_6, 0);
  1846. WREG32_SMC(ixCG_FREQ_TRAN_VOTING_7, 0);
  1847. }
  1848. static int ci_upload_firmware(struct amdgpu_device *adev)
  1849. {
  1850. int i, ret;
  1851. if (amdgpu_ci_is_smc_running(adev)) {
  1852. DRM_INFO("smc is running, no need to load smc firmware\n");
  1853. return 0;
  1854. }
  1855. for (i = 0; i < adev->usec_timeout; i++) {
  1856. if (RREG32_SMC(ixRCU_UC_EVENTS) & RCU_UC_EVENTS__boot_seq_done_MASK)
  1857. break;
  1858. }
  1859. WREG32_SMC(ixSMC_SYSCON_MISC_CNTL, 1);
  1860. amdgpu_ci_stop_smc_clock(adev);
  1861. amdgpu_ci_reset_smc(adev);
  1862. ret = amdgpu_ci_load_smc_ucode(adev, SMC_RAM_END);
  1863. return ret;
  1864. }
  1865. static int ci_get_svi2_voltage_table(struct amdgpu_device *adev,
  1866. struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
  1867. struct atom_voltage_table *voltage_table)
  1868. {
  1869. u32 i;
  1870. if (voltage_dependency_table == NULL)
  1871. return -EINVAL;
  1872. voltage_table->mask_low = 0;
  1873. voltage_table->phase_delay = 0;
  1874. voltage_table->count = voltage_dependency_table->count;
  1875. for (i = 0; i < voltage_table->count; i++) {
  1876. voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
  1877. voltage_table->entries[i].smio_low = 0;
  1878. }
  1879. return 0;
  1880. }
  1881. static int ci_construct_voltage_tables(struct amdgpu_device *adev)
  1882. {
  1883. struct ci_power_info *pi = ci_get_pi(adev);
  1884. int ret;
  1885. if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
  1886. ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
  1887. VOLTAGE_OBJ_GPIO_LUT,
  1888. &pi->vddc_voltage_table);
  1889. if (ret)
  1890. return ret;
  1891. } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
  1892. ret = ci_get_svi2_voltage_table(adev,
  1893. &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
  1894. &pi->vddc_voltage_table);
  1895. if (ret)
  1896. return ret;
  1897. }
  1898. if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
  1899. ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDC,
  1900. &pi->vddc_voltage_table);
  1901. if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
  1902. ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
  1903. VOLTAGE_OBJ_GPIO_LUT,
  1904. &pi->vddci_voltage_table);
  1905. if (ret)
  1906. return ret;
  1907. } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
  1908. ret = ci_get_svi2_voltage_table(adev,
  1909. &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
  1910. &pi->vddci_voltage_table);
  1911. if (ret)
  1912. return ret;
  1913. }
  1914. if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
  1915. ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_VDDCI,
  1916. &pi->vddci_voltage_table);
  1917. if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
  1918. ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
  1919. VOLTAGE_OBJ_GPIO_LUT,
  1920. &pi->mvdd_voltage_table);
  1921. if (ret)
  1922. return ret;
  1923. } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
  1924. ret = ci_get_svi2_voltage_table(adev,
  1925. &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
  1926. &pi->mvdd_voltage_table);
  1927. if (ret)
  1928. return ret;
  1929. }
  1930. if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
  1931. ci_trim_voltage_table_to_fit_state_table(adev, SMU7_MAX_LEVELS_MVDD,
  1932. &pi->mvdd_voltage_table);
  1933. return 0;
  1934. }
  1935. static void ci_populate_smc_voltage_table(struct amdgpu_device *adev,
  1936. struct atom_voltage_table_entry *voltage_table,
  1937. SMU7_Discrete_VoltageLevel *smc_voltage_table)
  1938. {
  1939. int ret;
  1940. ret = ci_get_std_voltage_value_sidd(adev, voltage_table,
  1941. &smc_voltage_table->StdVoltageHiSidd,
  1942. &smc_voltage_table->StdVoltageLoSidd);
  1943. if (ret) {
  1944. smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
  1945. smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
  1946. }
  1947. smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
  1948. smc_voltage_table->StdVoltageHiSidd =
  1949. cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
  1950. smc_voltage_table->StdVoltageLoSidd =
  1951. cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
  1952. }
  1953. static int ci_populate_smc_vddc_table(struct amdgpu_device *adev,
  1954. SMU7_Discrete_DpmTable *table)
  1955. {
  1956. struct ci_power_info *pi = ci_get_pi(adev);
  1957. unsigned int count;
  1958. table->VddcLevelCount = pi->vddc_voltage_table.count;
  1959. for (count = 0; count < table->VddcLevelCount; count++) {
  1960. ci_populate_smc_voltage_table(adev,
  1961. &pi->vddc_voltage_table.entries[count],
  1962. &table->VddcLevel[count]);
  1963. if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
  1964. table->VddcLevel[count].Smio |=
  1965. pi->vddc_voltage_table.entries[count].smio_low;
  1966. else
  1967. table->VddcLevel[count].Smio = 0;
  1968. }
  1969. table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
  1970. return 0;
  1971. }
  1972. static int ci_populate_smc_vddci_table(struct amdgpu_device *adev,
  1973. SMU7_Discrete_DpmTable *table)
  1974. {
  1975. unsigned int count;
  1976. struct ci_power_info *pi = ci_get_pi(adev);
  1977. table->VddciLevelCount = pi->vddci_voltage_table.count;
  1978. for (count = 0; count < table->VddciLevelCount; count++) {
  1979. ci_populate_smc_voltage_table(adev,
  1980. &pi->vddci_voltage_table.entries[count],
  1981. &table->VddciLevel[count]);
  1982. if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
  1983. table->VddciLevel[count].Smio |=
  1984. pi->vddci_voltage_table.entries[count].smio_low;
  1985. else
  1986. table->VddciLevel[count].Smio = 0;
  1987. }
  1988. table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
  1989. return 0;
  1990. }
  1991. static int ci_populate_smc_mvdd_table(struct amdgpu_device *adev,
  1992. SMU7_Discrete_DpmTable *table)
  1993. {
  1994. struct ci_power_info *pi = ci_get_pi(adev);
  1995. unsigned int count;
  1996. table->MvddLevelCount = pi->mvdd_voltage_table.count;
  1997. for (count = 0; count < table->MvddLevelCount; count++) {
  1998. ci_populate_smc_voltage_table(adev,
  1999. &pi->mvdd_voltage_table.entries[count],
  2000. &table->MvddLevel[count]);
  2001. if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
  2002. table->MvddLevel[count].Smio |=
  2003. pi->mvdd_voltage_table.entries[count].smio_low;
  2004. else
  2005. table->MvddLevel[count].Smio = 0;
  2006. }
  2007. table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
  2008. return 0;
  2009. }
  2010. static int ci_populate_smc_voltage_tables(struct amdgpu_device *adev,
  2011. SMU7_Discrete_DpmTable *table)
  2012. {
  2013. int ret;
  2014. ret = ci_populate_smc_vddc_table(adev, table);
  2015. if (ret)
  2016. return ret;
  2017. ret = ci_populate_smc_vddci_table(adev, table);
  2018. if (ret)
  2019. return ret;
  2020. ret = ci_populate_smc_mvdd_table(adev, table);
  2021. if (ret)
  2022. return ret;
  2023. return 0;
  2024. }
  2025. static int ci_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
  2026. SMU7_Discrete_VoltageLevel *voltage)
  2027. {
  2028. struct ci_power_info *pi = ci_get_pi(adev);
  2029. u32 i = 0;
  2030. if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
  2031. for (i = 0; i < adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
  2032. if (mclk <= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
  2033. voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
  2034. break;
  2035. }
  2036. }
  2037. if (i >= adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
  2038. return -EINVAL;
  2039. }
  2040. return -EINVAL;
  2041. }
  2042. static int ci_get_std_voltage_value_sidd(struct amdgpu_device *adev,
  2043. struct atom_voltage_table_entry *voltage_table,
  2044. u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
  2045. {
  2046. u16 v_index, idx;
  2047. bool voltage_found = false;
  2048. *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
  2049. *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
  2050. if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
  2051. return -EINVAL;
  2052. if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
  2053. for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
  2054. if (voltage_table->value ==
  2055. adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
  2056. voltage_found = true;
  2057. if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
  2058. idx = v_index;
  2059. else
  2060. idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
  2061. *std_voltage_lo_sidd =
  2062. adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
  2063. *std_voltage_hi_sidd =
  2064. adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
  2065. break;
  2066. }
  2067. }
  2068. if (!voltage_found) {
  2069. for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
  2070. if (voltage_table->value <=
  2071. adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
  2072. voltage_found = true;
  2073. if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
  2074. idx = v_index;
  2075. else
  2076. idx = adev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
  2077. *std_voltage_lo_sidd =
  2078. adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
  2079. *std_voltage_hi_sidd =
  2080. adev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
  2081. break;
  2082. }
  2083. }
  2084. }
  2085. }
  2086. return 0;
  2087. }
  2088. static void ci_populate_phase_value_based_on_sclk(struct amdgpu_device *adev,
  2089. const struct amdgpu_phase_shedding_limits_table *limits,
  2090. u32 sclk,
  2091. u32 *phase_shedding)
  2092. {
  2093. unsigned int i;
  2094. *phase_shedding = 1;
  2095. for (i = 0; i < limits->count; i++) {
  2096. if (sclk < limits->entries[i].sclk) {
  2097. *phase_shedding = i;
  2098. break;
  2099. }
  2100. }
  2101. }
  2102. static void ci_populate_phase_value_based_on_mclk(struct amdgpu_device *adev,
  2103. const struct amdgpu_phase_shedding_limits_table *limits,
  2104. u32 mclk,
  2105. u32 *phase_shedding)
  2106. {
  2107. unsigned int i;
  2108. *phase_shedding = 1;
  2109. for (i = 0; i < limits->count; i++) {
  2110. if (mclk < limits->entries[i].mclk) {
  2111. *phase_shedding = i;
  2112. break;
  2113. }
  2114. }
  2115. }
  2116. static int ci_init_arb_table_index(struct amdgpu_device *adev)
  2117. {
  2118. struct ci_power_info *pi = ci_get_pi(adev);
  2119. u32 tmp;
  2120. int ret;
  2121. ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,
  2122. &tmp, pi->sram_end);
  2123. if (ret)
  2124. return ret;
  2125. tmp &= 0x00FFFFFF;
  2126. tmp |= MC_CG_ARB_FREQ_F1 << 24;
  2127. return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,
  2128. tmp, pi->sram_end);
  2129. }
  2130. static int ci_get_dependency_volt_by_clk(struct amdgpu_device *adev,
  2131. struct amdgpu_clock_voltage_dependency_table *allowed_clock_voltage_table,
  2132. u32 clock, u32 *voltage)
  2133. {
  2134. u32 i = 0;
  2135. if (allowed_clock_voltage_table->count == 0)
  2136. return -EINVAL;
  2137. for (i = 0; i < allowed_clock_voltage_table->count; i++) {
  2138. if (allowed_clock_voltage_table->entries[i].clk >= clock) {
  2139. *voltage = allowed_clock_voltage_table->entries[i].v;
  2140. return 0;
  2141. }
  2142. }
  2143. *voltage = allowed_clock_voltage_table->entries[i-1].v;
  2144. return 0;
  2145. }
  2146. static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)
  2147. {
  2148. u32 i;
  2149. u32 tmp;
  2150. u32 min = max(min_sclk_in_sr, (u32)CISLAND_MINIMUM_ENGINE_CLOCK);
  2151. if (sclk < min)
  2152. return 0;
  2153. for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
  2154. tmp = sclk >> i;
  2155. if (tmp >= min || i == 0)
  2156. break;
  2157. }
  2158. return (u8)i;
  2159. }
  2160. static int ci_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
  2161. {
  2162. return ci_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
  2163. }
  2164. static int ci_reset_to_default(struct amdgpu_device *adev)
  2165. {
  2166. return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
  2167. 0 : -EINVAL;
  2168. }
  2169. static int ci_force_switch_to_arb_f0(struct amdgpu_device *adev)
  2170. {
  2171. u32 tmp;
  2172. tmp = (RREG32_SMC(ixSMC_SCRATCH9) & 0x0000ff00) >> 8;
  2173. if (tmp == MC_CG_ARB_FREQ_F0)
  2174. return 0;
  2175. return ci_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
  2176. }
  2177. static void ci_register_patching_mc_arb(struct amdgpu_device *adev,
  2178. const u32 engine_clock,
  2179. const u32 memory_clock,
  2180. u32 *dram_timimg2)
  2181. {
  2182. bool patch;
  2183. u32 tmp, tmp2;
  2184. tmp = RREG32(mmMC_SEQ_MISC0);
  2185. patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
  2186. if (patch &&
  2187. ((adev->pdev->device == 0x67B0) ||
  2188. (adev->pdev->device == 0x67B1))) {
  2189. if ((memory_clock > 100000) && (memory_clock <= 125000)) {
  2190. tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
  2191. *dram_timimg2 &= ~0x00ff0000;
  2192. *dram_timimg2 |= tmp2 << 16;
  2193. } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
  2194. tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
  2195. *dram_timimg2 &= ~0x00ff0000;
  2196. *dram_timimg2 |= tmp2 << 16;
  2197. }
  2198. }
  2199. }
  2200. static int ci_populate_memory_timing_parameters(struct amdgpu_device *adev,
  2201. u32 sclk,
  2202. u32 mclk,
  2203. SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
  2204. {
  2205. u32 dram_timing;
  2206. u32 dram_timing2;
  2207. u32 burst_time;
  2208. amdgpu_atombios_set_engine_dram_timings(adev, sclk, mclk);
  2209. dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
  2210. dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
  2211. burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
  2212. ci_register_patching_mc_arb(adev, sclk, mclk, &dram_timing2);
  2213. arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
  2214. arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
  2215. arb_regs->McArbBurstTime = (u8)burst_time;
  2216. return 0;
  2217. }
  2218. static int ci_do_program_memory_timing_parameters(struct amdgpu_device *adev)
  2219. {
  2220. struct ci_power_info *pi = ci_get_pi(adev);
  2221. SMU7_Discrete_MCArbDramTimingTable arb_regs;
  2222. u32 i, j;
  2223. int ret = 0;
  2224. memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
  2225. for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
  2226. for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
  2227. ret = ci_populate_memory_timing_parameters(adev,
  2228. pi->dpm_table.sclk_table.dpm_levels[i].value,
  2229. pi->dpm_table.mclk_table.dpm_levels[j].value,
  2230. &arb_regs.entries[i][j]);
  2231. if (ret)
  2232. break;
  2233. }
  2234. }
  2235. if (ret == 0)
  2236. ret = amdgpu_ci_copy_bytes_to_smc(adev,
  2237. pi->arb_table_start,
  2238. (u8 *)&arb_regs,
  2239. sizeof(SMU7_Discrete_MCArbDramTimingTable),
  2240. pi->sram_end);
  2241. return ret;
  2242. }
  2243. static int ci_program_memory_timing_parameters(struct amdgpu_device *adev)
  2244. {
  2245. struct ci_power_info *pi = ci_get_pi(adev);
  2246. if (pi->need_update_smu7_dpm_table == 0)
  2247. return 0;
  2248. return ci_do_program_memory_timing_parameters(adev);
  2249. }
  2250. static void ci_populate_smc_initial_state(struct amdgpu_device *adev,
  2251. struct amdgpu_ps *amdgpu_boot_state)
  2252. {
  2253. struct ci_ps *boot_state = ci_get_ps(amdgpu_boot_state);
  2254. struct ci_power_info *pi = ci_get_pi(adev);
  2255. u32 level = 0;
  2256. for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
  2257. if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
  2258. boot_state->performance_levels[0].sclk) {
  2259. pi->smc_state_table.GraphicsBootLevel = level;
  2260. break;
  2261. }
  2262. }
  2263. for (level = 0; level < adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
  2264. if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
  2265. boot_state->performance_levels[0].mclk) {
  2266. pi->smc_state_table.MemoryBootLevel = level;
  2267. break;
  2268. }
  2269. }
  2270. }
  2271. static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
  2272. {
  2273. u32 i;
  2274. u32 mask_value = 0;
  2275. for (i = dpm_table->count; i > 0; i--) {
  2276. mask_value = mask_value << 1;
  2277. if (dpm_table->dpm_levels[i-1].enabled)
  2278. mask_value |= 0x1;
  2279. else
  2280. mask_value &= 0xFFFFFFFE;
  2281. }
  2282. return mask_value;
  2283. }
  2284. static void ci_populate_smc_link_level(struct amdgpu_device *adev,
  2285. SMU7_Discrete_DpmTable *table)
  2286. {
  2287. struct ci_power_info *pi = ci_get_pi(adev);
  2288. struct ci_dpm_table *dpm_table = &pi->dpm_table;
  2289. u32 i;
  2290. for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
  2291. table->LinkLevel[i].PcieGenSpeed =
  2292. (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
  2293. table->LinkLevel[i].PcieLaneCount =
  2294. amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
  2295. table->LinkLevel[i].EnabledForActivity = 1;
  2296. table->LinkLevel[i].DownT = cpu_to_be32(5);
  2297. table->LinkLevel[i].UpT = cpu_to_be32(30);
  2298. }
  2299. pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
  2300. pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
  2301. ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
  2302. }
  2303. static int ci_populate_smc_uvd_level(struct amdgpu_device *adev,
  2304. SMU7_Discrete_DpmTable *table)
  2305. {
  2306. u32 count;
  2307. struct atom_clock_dividers dividers;
  2308. int ret = -EINVAL;
  2309. table->UvdLevelCount =
  2310. adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
  2311. for (count = 0; count < table->UvdLevelCount; count++) {
  2312. table->UvdLevel[count].VclkFrequency =
  2313. adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
  2314. table->UvdLevel[count].DclkFrequency =
  2315. adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
  2316. table->UvdLevel[count].MinVddc =
  2317. adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
  2318. table->UvdLevel[count].MinVddcPhases = 1;
  2319. ret = amdgpu_atombios_get_clock_dividers(adev,
  2320. COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
  2321. table->UvdLevel[count].VclkFrequency, false, &dividers);
  2322. if (ret)
  2323. return ret;
  2324. table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
  2325. ret = amdgpu_atombios_get_clock_dividers(adev,
  2326. COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
  2327. table->UvdLevel[count].DclkFrequency, false, &dividers);
  2328. if (ret)
  2329. return ret;
  2330. table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
  2331. table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
  2332. table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
  2333. table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
  2334. }
  2335. return ret;
  2336. }
  2337. static int ci_populate_smc_vce_level(struct amdgpu_device *adev,
  2338. SMU7_Discrete_DpmTable *table)
  2339. {
  2340. u32 count;
  2341. struct atom_clock_dividers dividers;
  2342. int ret = -EINVAL;
  2343. table->VceLevelCount =
  2344. adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
  2345. for (count = 0; count < table->VceLevelCount; count++) {
  2346. table->VceLevel[count].Frequency =
  2347. adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
  2348. table->VceLevel[count].MinVoltage =
  2349. (u16)adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
  2350. table->VceLevel[count].MinPhases = 1;
  2351. ret = amdgpu_atombios_get_clock_dividers(adev,
  2352. COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
  2353. table->VceLevel[count].Frequency, false, &dividers);
  2354. if (ret)
  2355. return ret;
  2356. table->VceLevel[count].Divider = (u8)dividers.post_divider;
  2357. table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
  2358. table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
  2359. }
  2360. return ret;
  2361. }
  2362. static int ci_populate_smc_acp_level(struct amdgpu_device *adev,
  2363. SMU7_Discrete_DpmTable *table)
  2364. {
  2365. u32 count;
  2366. struct atom_clock_dividers dividers;
  2367. int ret = -EINVAL;
  2368. table->AcpLevelCount = (u8)
  2369. (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
  2370. for (count = 0; count < table->AcpLevelCount; count++) {
  2371. table->AcpLevel[count].Frequency =
  2372. adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
  2373. table->AcpLevel[count].MinVoltage =
  2374. adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
  2375. table->AcpLevel[count].MinPhases = 1;
  2376. ret = amdgpu_atombios_get_clock_dividers(adev,
  2377. COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
  2378. table->AcpLevel[count].Frequency, false, &dividers);
  2379. if (ret)
  2380. return ret;
  2381. table->AcpLevel[count].Divider = (u8)dividers.post_divider;
  2382. table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
  2383. table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
  2384. }
  2385. return ret;
  2386. }
  2387. static int ci_populate_smc_samu_level(struct amdgpu_device *adev,
  2388. SMU7_Discrete_DpmTable *table)
  2389. {
  2390. u32 count;
  2391. struct atom_clock_dividers dividers;
  2392. int ret = -EINVAL;
  2393. table->SamuLevelCount =
  2394. adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
  2395. for (count = 0; count < table->SamuLevelCount; count++) {
  2396. table->SamuLevel[count].Frequency =
  2397. adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
  2398. table->SamuLevel[count].MinVoltage =
  2399. adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
  2400. table->SamuLevel[count].MinPhases = 1;
  2401. ret = amdgpu_atombios_get_clock_dividers(adev,
  2402. COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
  2403. table->SamuLevel[count].Frequency, false, &dividers);
  2404. if (ret)
  2405. return ret;
  2406. table->SamuLevel[count].Divider = (u8)dividers.post_divider;
  2407. table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
  2408. table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
  2409. }
  2410. return ret;
  2411. }
  2412. static int ci_calculate_mclk_params(struct amdgpu_device *adev,
  2413. u32 memory_clock,
  2414. SMU7_Discrete_MemoryLevel *mclk,
  2415. bool strobe_mode,
  2416. bool dll_state_on)
  2417. {
  2418. struct ci_power_info *pi = ci_get_pi(adev);
  2419. u32 dll_cntl = pi->clock_registers.dll_cntl;
  2420. u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
  2421. u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
  2422. u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
  2423. u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
  2424. u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
  2425. u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
  2426. u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
  2427. u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
  2428. struct atom_mpll_param mpll_param;
  2429. int ret;
  2430. ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
  2431. if (ret)
  2432. return ret;
  2433. mpll_func_cntl &= ~MPLL_FUNC_CNTL__BWCTRL_MASK;
  2434. mpll_func_cntl |= (mpll_param.bwcntl << MPLL_FUNC_CNTL__BWCTRL__SHIFT);
  2435. mpll_func_cntl_1 &= ~(MPLL_FUNC_CNTL_1__CLKF_MASK | MPLL_FUNC_CNTL_1__CLKFRAC_MASK |
  2436. MPLL_FUNC_CNTL_1__VCO_MODE_MASK);
  2437. mpll_func_cntl_1 |= (mpll_param.clkf) << MPLL_FUNC_CNTL_1__CLKF__SHIFT |
  2438. (mpll_param.clkfrac << MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT) |
  2439. (mpll_param.vco_mode << MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT);
  2440. mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK;
  2441. mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
  2442. if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
  2443. mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK |
  2444. MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK);
  2445. mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) |
  2446. (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT);
  2447. }
  2448. if (pi->caps_mclk_ss_support) {
  2449. struct amdgpu_atom_ss ss;
  2450. u32 freq_nom;
  2451. u32 tmp;
  2452. u32 reference_clock = adev->clock.mpll.reference_freq;
  2453. if (mpll_param.qdr == 1)
  2454. freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
  2455. else
  2456. freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
  2457. tmp = (freq_nom / reference_clock);
  2458. tmp = tmp * tmp;
  2459. if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
  2460. ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
  2461. u32 clks = reference_clock * 5 / ss.rate;
  2462. u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
  2463. mpll_ss1 &= ~MPLL_SS1__CLKV_MASK;
  2464. mpll_ss1 |= (clkv << MPLL_SS1__CLKV__SHIFT);
  2465. mpll_ss2 &= ~MPLL_SS2__CLKS_MASK;
  2466. mpll_ss2 |= (clks << MPLL_SS2__CLKS__SHIFT);
  2467. }
  2468. }
  2469. mclk_pwrmgt_cntl &= ~MCLK_PWRMGT_CNTL__DLL_SPEED_MASK;
  2470. mclk_pwrmgt_cntl |= (mpll_param.dll_speed << MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT);
  2471. if (dll_state_on)
  2472. mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
  2473. MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK;
  2474. else
  2475. mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
  2476. MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
  2477. mclk->MclkFrequency = memory_clock;
  2478. mclk->MpllFuncCntl = mpll_func_cntl;
  2479. mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
  2480. mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
  2481. mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
  2482. mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
  2483. mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
  2484. mclk->DllCntl = dll_cntl;
  2485. mclk->MpllSs1 = mpll_ss1;
  2486. mclk->MpllSs2 = mpll_ss2;
  2487. return 0;
  2488. }
  2489. static int ci_populate_single_memory_level(struct amdgpu_device *adev,
  2490. u32 memory_clock,
  2491. SMU7_Discrete_MemoryLevel *memory_level)
  2492. {
  2493. struct ci_power_info *pi = ci_get_pi(adev);
  2494. int ret;
  2495. bool dll_state_on;
  2496. if (adev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
  2497. ret = ci_get_dependency_volt_by_clk(adev,
  2498. &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
  2499. memory_clock, &memory_level->MinVddc);
  2500. if (ret)
  2501. return ret;
  2502. }
  2503. if (adev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
  2504. ret = ci_get_dependency_volt_by_clk(adev,
  2505. &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
  2506. memory_clock, &memory_level->MinVddci);
  2507. if (ret)
  2508. return ret;
  2509. }
  2510. if (adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
  2511. ret = ci_get_dependency_volt_by_clk(adev,
  2512. &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
  2513. memory_clock, &memory_level->MinMvdd);
  2514. if (ret)
  2515. return ret;
  2516. }
  2517. memory_level->MinVddcPhases = 1;
  2518. if (pi->vddc_phase_shed_control)
  2519. ci_populate_phase_value_based_on_mclk(adev,
  2520. &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
  2521. memory_clock,
  2522. &memory_level->MinVddcPhases);
  2523. memory_level->EnabledForActivity = 1;
  2524. memory_level->EnabledForThrottle = 1;
  2525. memory_level->UpH = 0;
  2526. memory_level->DownH = 100;
  2527. memory_level->VoltageDownH = 0;
  2528. memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
  2529. memory_level->StutterEnable = false;
  2530. memory_level->StrobeEnable = false;
  2531. memory_level->EdcReadEnable = false;
  2532. memory_level->EdcWriteEnable = false;
  2533. memory_level->RttEnable = false;
  2534. memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
  2535. if (pi->mclk_stutter_mode_threshold &&
  2536. (memory_clock <= pi->mclk_stutter_mode_threshold) &&
  2537. (!pi->uvd_enabled) &&
  2538. (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
  2539. (adev->pm.dpm.new_active_crtc_count <= 2))
  2540. memory_level->StutterEnable = true;
  2541. if (pi->mclk_strobe_mode_threshold &&
  2542. (memory_clock <= pi->mclk_strobe_mode_threshold))
  2543. memory_level->StrobeEnable = 1;
  2544. if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
  2545. memory_level->StrobeRatio =
  2546. ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
  2547. if (pi->mclk_edc_enable_threshold &&
  2548. (memory_clock > pi->mclk_edc_enable_threshold))
  2549. memory_level->EdcReadEnable = true;
  2550. if (pi->mclk_edc_wr_enable_threshold &&
  2551. (memory_clock > pi->mclk_edc_wr_enable_threshold))
  2552. memory_level->EdcWriteEnable = true;
  2553. if (memory_level->StrobeEnable) {
  2554. if (ci_get_mclk_frequency_ratio(memory_clock, true) >=
  2555. ((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
  2556. dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
  2557. else
  2558. dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
  2559. } else {
  2560. dll_state_on = pi->dll_default_on;
  2561. }
  2562. } else {
  2563. memory_level->StrobeRatio = ci_get_ddr3_mclk_frequency_ratio(memory_clock);
  2564. dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
  2565. }
  2566. ret = ci_calculate_mclk_params(adev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
  2567. if (ret)
  2568. return ret;
  2569. memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
  2570. memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
  2571. memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
  2572. memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
  2573. memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
  2574. memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
  2575. memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
  2576. memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
  2577. memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
  2578. memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
  2579. memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
  2580. memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
  2581. memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
  2582. memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
  2583. memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
  2584. return 0;
  2585. }
  2586. static int ci_populate_smc_acpi_level(struct amdgpu_device *adev,
  2587. SMU7_Discrete_DpmTable *table)
  2588. {
  2589. struct ci_power_info *pi = ci_get_pi(adev);
  2590. struct atom_clock_dividers dividers;
  2591. SMU7_Discrete_VoltageLevel voltage_level;
  2592. u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
  2593. u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
  2594. u32 dll_cntl = pi->clock_registers.dll_cntl;
  2595. u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
  2596. int ret;
  2597. table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
  2598. if (pi->acpi_vddc)
  2599. table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
  2600. else
  2601. table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
  2602. table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
  2603. table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;
  2604. ret = amdgpu_atombios_get_clock_dividers(adev,
  2605. COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
  2606. table->ACPILevel.SclkFrequency, false, &dividers);
  2607. if (ret)
  2608. return ret;
  2609. table->ACPILevel.SclkDid = (u8)dividers.post_divider;
  2610. table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
  2611. table->ACPILevel.DeepSleepDivId = 0;
  2612. spll_func_cntl &= ~CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK;
  2613. spll_func_cntl |= CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK;
  2614. spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK;
  2615. spll_func_cntl_2 |= (4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT);
  2616. table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
  2617. table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
  2618. table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
  2619. table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
  2620. table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
  2621. table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
  2622. table->ACPILevel.CcPwrDynRm = 0;
  2623. table->ACPILevel.CcPwrDynRm1 = 0;
  2624. table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
  2625. table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
  2626. table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
  2627. table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
  2628. table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
  2629. table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
  2630. table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
  2631. table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
  2632. table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
  2633. table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
  2634. table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
  2635. table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
  2636. table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
  2637. if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
  2638. if (pi->acpi_vddci)
  2639. table->MemoryACPILevel.MinVddci =
  2640. cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
  2641. else
  2642. table->MemoryACPILevel.MinVddci =
  2643. cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
  2644. }
  2645. if (ci_populate_mvdd_value(adev, 0, &voltage_level))
  2646. table->MemoryACPILevel.MinMvdd = 0;
  2647. else
  2648. table->MemoryACPILevel.MinMvdd =
  2649. cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
  2650. mclk_pwrmgt_cntl |= MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK |
  2651. MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK;
  2652. mclk_pwrmgt_cntl &= ~(MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK |
  2653. MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK);
  2654. dll_cntl &= ~(DLL_CNTL__MRDCK0_BYPASS_MASK | DLL_CNTL__MRDCK1_BYPASS_MASK);
  2655. table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
  2656. table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
  2657. table->MemoryACPILevel.MpllAdFuncCntl =
  2658. cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
  2659. table->MemoryACPILevel.MpllDqFuncCntl =
  2660. cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
  2661. table->MemoryACPILevel.MpllFuncCntl =
  2662. cpu_to_be32(pi->clock_registers.mpll_func_cntl);
  2663. table->MemoryACPILevel.MpllFuncCntl_1 =
  2664. cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
  2665. table->MemoryACPILevel.MpllFuncCntl_2 =
  2666. cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
  2667. table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
  2668. table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
  2669. table->MemoryACPILevel.EnabledForThrottle = 0;
  2670. table->MemoryACPILevel.EnabledForActivity = 0;
  2671. table->MemoryACPILevel.UpH = 0;
  2672. table->MemoryACPILevel.DownH = 100;
  2673. table->MemoryACPILevel.VoltageDownH = 0;
  2674. table->MemoryACPILevel.ActivityLevel =
  2675. cpu_to_be16((u16)pi->mclk_activity_target);
  2676. table->MemoryACPILevel.StutterEnable = false;
  2677. table->MemoryACPILevel.StrobeEnable = false;
  2678. table->MemoryACPILevel.EdcReadEnable = false;
  2679. table->MemoryACPILevel.EdcWriteEnable = false;
  2680. table->MemoryACPILevel.RttEnable = false;
  2681. return 0;
  2682. }
  2683. static int ci_enable_ulv(struct amdgpu_device *adev, bool enable)
  2684. {
  2685. struct ci_power_info *pi = ci_get_pi(adev);
  2686. struct ci_ulv_parm *ulv = &pi->ulv;
  2687. if (ulv->supported) {
  2688. if (enable)
  2689. return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
  2690. 0 : -EINVAL;
  2691. else
  2692. return (amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
  2693. 0 : -EINVAL;
  2694. }
  2695. return 0;
  2696. }
  2697. static int ci_populate_ulv_level(struct amdgpu_device *adev,
  2698. SMU7_Discrete_Ulv *state)
  2699. {
  2700. struct ci_power_info *pi = ci_get_pi(adev);
  2701. u16 ulv_voltage = adev->pm.dpm.backbias_response_time;
  2702. state->CcPwrDynRm = 0;
  2703. state->CcPwrDynRm1 = 0;
  2704. if (ulv_voltage == 0) {
  2705. pi->ulv.supported = false;
  2706. return 0;
  2707. }
  2708. if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
  2709. if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
  2710. state->VddcOffset = 0;
  2711. else
  2712. state->VddcOffset =
  2713. adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
  2714. } else {
  2715. if (ulv_voltage > adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
  2716. state->VddcOffsetVid = 0;
  2717. else
  2718. state->VddcOffsetVid = (u8)
  2719. ((adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
  2720. VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
  2721. }
  2722. state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
  2723. state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
  2724. state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
  2725. state->VddcOffset = cpu_to_be16(state->VddcOffset);
  2726. return 0;
  2727. }
  2728. static int ci_calculate_sclk_params(struct amdgpu_device *adev,
  2729. u32 engine_clock,
  2730. SMU7_Discrete_GraphicsLevel *sclk)
  2731. {
  2732. struct ci_power_info *pi = ci_get_pi(adev);
  2733. struct atom_clock_dividers dividers;
  2734. u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
  2735. u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
  2736. u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
  2737. u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
  2738. u32 reference_clock = adev->clock.spll.reference_freq;
  2739. u32 reference_divider;
  2740. u32 fbdiv;
  2741. int ret;
  2742. ret = amdgpu_atombios_get_clock_dividers(adev,
  2743. COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
  2744. engine_clock, false, &dividers);
  2745. if (ret)
  2746. return ret;
  2747. reference_divider = 1 + dividers.ref_div;
  2748. fbdiv = dividers.fb_div & 0x3FFFFFF;
  2749. spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK;
  2750. spll_func_cntl_3 |= (fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT);
  2751. spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK;
  2752. if (pi->caps_sclk_ss_support) {
  2753. struct amdgpu_atom_ss ss;
  2754. u32 vco_freq = engine_clock * dividers.post_div;
  2755. if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
  2756. ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
  2757. u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
  2758. u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
  2759. cg_spll_spread_spectrum &= ~(CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK | CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK);
  2760. cg_spll_spread_spectrum |= (clk_s << CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT);
  2761. cg_spll_spread_spectrum |= (1 << CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT);
  2762. cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK;
  2763. cg_spll_spread_spectrum_2 |= (clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT);
  2764. }
  2765. }
  2766. sclk->SclkFrequency = engine_clock;
  2767. sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
  2768. sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
  2769. sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
  2770. sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
  2771. sclk->SclkDid = (u8)dividers.post_divider;
  2772. return 0;
  2773. }
  2774. static int ci_populate_single_graphic_level(struct amdgpu_device *adev,
  2775. u32 engine_clock,
  2776. u16 sclk_activity_level_t,
  2777. SMU7_Discrete_GraphicsLevel *graphic_level)
  2778. {
  2779. struct ci_power_info *pi = ci_get_pi(adev);
  2780. int ret;
  2781. ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level);
  2782. if (ret)
  2783. return ret;
  2784. ret = ci_get_dependency_volt_by_clk(adev,
  2785. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
  2786. engine_clock, &graphic_level->MinVddc);
  2787. if (ret)
  2788. return ret;
  2789. graphic_level->SclkFrequency = engine_clock;
  2790. graphic_level->Flags = 0;
  2791. graphic_level->MinVddcPhases = 1;
  2792. if (pi->vddc_phase_shed_control)
  2793. ci_populate_phase_value_based_on_sclk(adev,
  2794. &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
  2795. engine_clock,
  2796. &graphic_level->MinVddcPhases);
  2797. graphic_level->ActivityLevel = sclk_activity_level_t;
  2798. graphic_level->CcPwrDynRm = 0;
  2799. graphic_level->CcPwrDynRm1 = 0;
  2800. graphic_level->EnabledForThrottle = 1;
  2801. graphic_level->UpH = 0;
  2802. graphic_level->DownH = 0;
  2803. graphic_level->VoltageDownH = 0;
  2804. graphic_level->PowerThrottle = 0;
  2805. if (pi->caps_sclk_ds)
  2806. graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(engine_clock,
  2807. CISLAND_MINIMUM_ENGINE_CLOCK);
  2808. graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
  2809. graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
  2810. graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
  2811. graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
  2812. graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
  2813. graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
  2814. graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
  2815. graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
  2816. graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
  2817. graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
  2818. graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
  2819. graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
  2820. return 0;
  2821. }
  2822. static int ci_populate_all_graphic_levels(struct amdgpu_device *adev)
  2823. {
  2824. struct ci_power_info *pi = ci_get_pi(adev);
  2825. struct ci_dpm_table *dpm_table = &pi->dpm_table;
  2826. u32 level_array_address = pi->dpm_table_start +
  2827. offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
  2828. u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
  2829. SMU7_MAX_LEVELS_GRAPHICS;
  2830. SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
  2831. u32 i, ret;
  2832. memset(levels, 0, level_array_size);
  2833. for (i = 0; i < dpm_table->sclk_table.count; i++) {
  2834. ret = ci_populate_single_graphic_level(adev,
  2835. dpm_table->sclk_table.dpm_levels[i].value,
  2836. (u16)pi->activity_target[i],
  2837. &pi->smc_state_table.GraphicsLevel[i]);
  2838. if (ret)
  2839. return ret;
  2840. if (i > 1)
  2841. pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
  2842. if (i == (dpm_table->sclk_table.count - 1))
  2843. pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
  2844. PPSMC_DISPLAY_WATERMARK_HIGH;
  2845. }
  2846. pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
  2847. pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
  2848. pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
  2849. ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
  2850. ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
  2851. (u8 *)levels, level_array_size,
  2852. pi->sram_end);
  2853. if (ret)
  2854. return ret;
  2855. return 0;
  2856. }
  2857. static int ci_populate_ulv_state(struct amdgpu_device *adev,
  2858. SMU7_Discrete_Ulv *ulv_level)
  2859. {
  2860. return ci_populate_ulv_level(adev, ulv_level);
  2861. }
  2862. static int ci_populate_all_memory_levels(struct amdgpu_device *adev)
  2863. {
  2864. struct ci_power_info *pi = ci_get_pi(adev);
  2865. struct ci_dpm_table *dpm_table = &pi->dpm_table;
  2866. u32 level_array_address = pi->dpm_table_start +
  2867. offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
  2868. u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
  2869. SMU7_MAX_LEVELS_MEMORY;
  2870. SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
  2871. u32 i, ret;
  2872. memset(levels, 0, level_array_size);
  2873. for (i = 0; i < dpm_table->mclk_table.count; i++) {
  2874. if (dpm_table->mclk_table.dpm_levels[i].value == 0)
  2875. return -EINVAL;
  2876. ret = ci_populate_single_memory_level(adev,
  2877. dpm_table->mclk_table.dpm_levels[i].value,
  2878. &pi->smc_state_table.MemoryLevel[i]);
  2879. if (ret)
  2880. return ret;
  2881. }
  2882. if ((dpm_table->mclk_table.count >= 2) &&
  2883. ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {
  2884. pi->smc_state_table.MemoryLevel[1].MinVddc =
  2885. pi->smc_state_table.MemoryLevel[0].MinVddc;
  2886. pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
  2887. pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
  2888. }
  2889. pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
  2890. pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
  2891. pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
  2892. ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
  2893. pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
  2894. PPSMC_DISPLAY_WATERMARK_HIGH;
  2895. ret = amdgpu_ci_copy_bytes_to_smc(adev, level_array_address,
  2896. (u8 *)levels, level_array_size,
  2897. pi->sram_end);
  2898. if (ret)
  2899. return ret;
  2900. return 0;
  2901. }
  2902. static void ci_reset_single_dpm_table(struct amdgpu_device *adev,
  2903. struct ci_single_dpm_table* dpm_table,
  2904. u32 count)
  2905. {
  2906. u32 i;
  2907. dpm_table->count = count;
  2908. for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
  2909. dpm_table->dpm_levels[i].enabled = false;
  2910. }
  2911. static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
  2912. u32 index, u32 pcie_gen, u32 pcie_lanes)
  2913. {
  2914. dpm_table->dpm_levels[index].value = pcie_gen;
  2915. dpm_table->dpm_levels[index].param1 = pcie_lanes;
  2916. dpm_table->dpm_levels[index].enabled = true;
  2917. }
  2918. static int ci_setup_default_pcie_tables(struct amdgpu_device *adev)
  2919. {
  2920. struct ci_power_info *pi = ci_get_pi(adev);
  2921. if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
  2922. return -EINVAL;
  2923. if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
  2924. pi->pcie_gen_powersaving = pi->pcie_gen_performance;
  2925. pi->pcie_lane_powersaving = pi->pcie_lane_performance;
  2926. } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
  2927. pi->pcie_gen_performance = pi->pcie_gen_powersaving;
  2928. pi->pcie_lane_performance = pi->pcie_lane_powersaving;
  2929. }
  2930. ci_reset_single_dpm_table(adev,
  2931. &pi->dpm_table.pcie_speed_table,
  2932. SMU7_MAX_LEVELS_LINK);
  2933. if (adev->asic_type == CHIP_BONAIRE)
  2934. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
  2935. pi->pcie_gen_powersaving.min,
  2936. pi->pcie_lane_powersaving.max);
  2937. else
  2938. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
  2939. pi->pcie_gen_powersaving.min,
  2940. pi->pcie_lane_powersaving.min);
  2941. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
  2942. pi->pcie_gen_performance.min,
  2943. pi->pcie_lane_performance.min);
  2944. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
  2945. pi->pcie_gen_powersaving.min,
  2946. pi->pcie_lane_powersaving.max);
  2947. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
  2948. pi->pcie_gen_performance.min,
  2949. pi->pcie_lane_performance.max);
  2950. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
  2951. pi->pcie_gen_powersaving.max,
  2952. pi->pcie_lane_powersaving.max);
  2953. ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
  2954. pi->pcie_gen_performance.max,
  2955. pi->pcie_lane_performance.max);
  2956. pi->dpm_table.pcie_speed_table.count = 6;
  2957. return 0;
  2958. }
  2959. static int ci_setup_default_dpm_tables(struct amdgpu_device *adev)
  2960. {
  2961. struct ci_power_info *pi = ci_get_pi(adev);
  2962. struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
  2963. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  2964. struct amdgpu_clock_voltage_dependency_table *allowed_mclk_table =
  2965. &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
  2966. struct amdgpu_cac_leakage_table *std_voltage_table =
  2967. &adev->pm.dpm.dyn_state.cac_leakage_table;
  2968. u32 i;
  2969. if (allowed_sclk_vddc_table == NULL)
  2970. return -EINVAL;
  2971. if (allowed_sclk_vddc_table->count < 1)
  2972. return -EINVAL;
  2973. if (allowed_mclk_table == NULL)
  2974. return -EINVAL;
  2975. if (allowed_mclk_table->count < 1)
  2976. return -EINVAL;
  2977. memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
  2978. ci_reset_single_dpm_table(adev,
  2979. &pi->dpm_table.sclk_table,
  2980. SMU7_MAX_LEVELS_GRAPHICS);
  2981. ci_reset_single_dpm_table(adev,
  2982. &pi->dpm_table.mclk_table,
  2983. SMU7_MAX_LEVELS_MEMORY);
  2984. ci_reset_single_dpm_table(adev,
  2985. &pi->dpm_table.vddc_table,
  2986. SMU7_MAX_LEVELS_VDDC);
  2987. ci_reset_single_dpm_table(adev,
  2988. &pi->dpm_table.vddci_table,
  2989. SMU7_MAX_LEVELS_VDDCI);
  2990. ci_reset_single_dpm_table(adev,
  2991. &pi->dpm_table.mvdd_table,
  2992. SMU7_MAX_LEVELS_MVDD);
  2993. pi->dpm_table.sclk_table.count = 0;
  2994. for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
  2995. if ((i == 0) ||
  2996. (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
  2997. allowed_sclk_vddc_table->entries[i].clk)) {
  2998. pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
  2999. allowed_sclk_vddc_table->entries[i].clk;
  3000. pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
  3001. (i == 0) ? true : false;
  3002. pi->dpm_table.sclk_table.count++;
  3003. }
  3004. }
  3005. pi->dpm_table.mclk_table.count = 0;
  3006. for (i = 0; i < allowed_mclk_table->count; i++) {
  3007. if ((i == 0) ||
  3008. (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
  3009. allowed_mclk_table->entries[i].clk)) {
  3010. pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
  3011. allowed_mclk_table->entries[i].clk;
  3012. pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
  3013. (i == 0) ? true : false;
  3014. pi->dpm_table.mclk_table.count++;
  3015. }
  3016. }
  3017. for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
  3018. pi->dpm_table.vddc_table.dpm_levels[i].value =
  3019. allowed_sclk_vddc_table->entries[i].v;
  3020. pi->dpm_table.vddc_table.dpm_levels[i].param1 =
  3021. std_voltage_table->entries[i].leakage;
  3022. pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
  3023. }
  3024. pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
  3025. allowed_mclk_table = &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
  3026. if (allowed_mclk_table) {
  3027. for (i = 0; i < allowed_mclk_table->count; i++) {
  3028. pi->dpm_table.vddci_table.dpm_levels[i].value =
  3029. allowed_mclk_table->entries[i].v;
  3030. pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
  3031. }
  3032. pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
  3033. }
  3034. allowed_mclk_table = &adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
  3035. if (allowed_mclk_table) {
  3036. for (i = 0; i < allowed_mclk_table->count; i++) {
  3037. pi->dpm_table.mvdd_table.dpm_levels[i].value =
  3038. allowed_mclk_table->entries[i].v;
  3039. pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
  3040. }
  3041. pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
  3042. }
  3043. ci_setup_default_pcie_tables(adev);
  3044. /* save a copy of the default DPM table */
  3045. memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),
  3046. sizeof(struct ci_dpm_table));
  3047. return 0;
  3048. }
  3049. static int ci_find_boot_level(struct ci_single_dpm_table *table,
  3050. u32 value, u32 *boot_level)
  3051. {
  3052. u32 i;
  3053. int ret = -EINVAL;
  3054. for(i = 0; i < table->count; i++) {
  3055. if (value == table->dpm_levels[i].value) {
  3056. *boot_level = i;
  3057. ret = 0;
  3058. }
  3059. }
  3060. return ret;
  3061. }
  3062. static void ci_save_default_power_profile(struct amdgpu_device *adev)
  3063. {
  3064. struct ci_power_info *pi = ci_get_pi(adev);
  3065. struct SMU7_Discrete_GraphicsLevel *levels =
  3066. pi->smc_state_table.GraphicsLevel;
  3067. uint32_t min_level = 0;
  3068. pi->default_gfx_power_profile.activity_threshold =
  3069. be16_to_cpu(levels[0].ActivityLevel);
  3070. pi->default_gfx_power_profile.up_hyst = levels[0].UpH;
  3071. pi->default_gfx_power_profile.down_hyst = levels[0].DownH;
  3072. pi->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
  3073. pi->default_compute_power_profile = pi->default_gfx_power_profile;
  3074. pi->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
  3075. /* Optimize compute power profile: Use only highest
  3076. * 2 power levels (if more than 2 are available), Hysteresis:
  3077. * 0ms up, 5ms down
  3078. */
  3079. if (pi->smc_state_table.GraphicsDpmLevelCount > 2)
  3080. min_level = pi->smc_state_table.GraphicsDpmLevelCount - 2;
  3081. else if (pi->smc_state_table.GraphicsDpmLevelCount == 2)
  3082. min_level = 1;
  3083. pi->default_compute_power_profile.min_sclk =
  3084. be32_to_cpu(levels[min_level].SclkFrequency);
  3085. pi->default_compute_power_profile.up_hyst = 0;
  3086. pi->default_compute_power_profile.down_hyst = 5;
  3087. pi->gfx_power_profile = pi->default_gfx_power_profile;
  3088. pi->compute_power_profile = pi->default_compute_power_profile;
  3089. }
  3090. static int ci_init_smc_table(struct amdgpu_device *adev)
  3091. {
  3092. struct ci_power_info *pi = ci_get_pi(adev);
  3093. struct ci_ulv_parm *ulv = &pi->ulv;
  3094. struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
  3095. SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
  3096. int ret;
  3097. ret = ci_setup_default_dpm_tables(adev);
  3098. if (ret)
  3099. return ret;
  3100. if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
  3101. ci_populate_smc_voltage_tables(adev, table);
  3102. ci_init_fps_limits(adev);
  3103. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
  3104. table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
  3105. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
  3106. table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
  3107. if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
  3108. table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
  3109. if (ulv->supported) {
  3110. ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);
  3111. if (ret)
  3112. return ret;
  3113. WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
  3114. }
  3115. ret = ci_populate_all_graphic_levels(adev);
  3116. if (ret)
  3117. return ret;
  3118. ret = ci_populate_all_memory_levels(adev);
  3119. if (ret)
  3120. return ret;
  3121. ci_populate_smc_link_level(adev, table);
  3122. ret = ci_populate_smc_acpi_level(adev, table);
  3123. if (ret)
  3124. return ret;
  3125. ret = ci_populate_smc_vce_level(adev, table);
  3126. if (ret)
  3127. return ret;
  3128. ret = ci_populate_smc_acp_level(adev, table);
  3129. if (ret)
  3130. return ret;
  3131. ret = ci_populate_smc_samu_level(adev, table);
  3132. if (ret)
  3133. return ret;
  3134. ret = ci_do_program_memory_timing_parameters(adev);
  3135. if (ret)
  3136. return ret;
  3137. ret = ci_populate_smc_uvd_level(adev, table);
  3138. if (ret)
  3139. return ret;
  3140. table->UvdBootLevel = 0;
  3141. table->VceBootLevel = 0;
  3142. table->AcpBootLevel = 0;
  3143. table->SamuBootLevel = 0;
  3144. table->GraphicsBootLevel = 0;
  3145. table->MemoryBootLevel = 0;
  3146. ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
  3147. pi->vbios_boot_state.sclk_bootup_value,
  3148. (u32 *)&pi->smc_state_table.GraphicsBootLevel);
  3149. ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
  3150. pi->vbios_boot_state.mclk_bootup_value,
  3151. (u32 *)&pi->smc_state_table.MemoryBootLevel);
  3152. table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
  3153. table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
  3154. table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
  3155. ci_populate_smc_initial_state(adev, amdgpu_boot_state);
  3156. ret = ci_populate_bapm_parameters_in_dpm_table(adev);
  3157. if (ret)
  3158. return ret;
  3159. table->UVDInterval = 1;
  3160. table->VCEInterval = 1;
  3161. table->ACPInterval = 1;
  3162. table->SAMUInterval = 1;
  3163. table->GraphicsVoltageChangeEnable = 1;
  3164. table->GraphicsThermThrottleEnable = 1;
  3165. table->GraphicsInterval = 1;
  3166. table->VoltageInterval = 1;
  3167. table->ThermalInterval = 1;
  3168. table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
  3169. CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
  3170. table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
  3171. CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
  3172. table->MemoryVoltageChangeEnable = 1;
  3173. table->MemoryInterval = 1;
  3174. table->VoltageResponseTime = 0;
  3175. table->VddcVddciDelta = 4000;
  3176. table->PhaseResponseTime = 0;
  3177. table->MemoryThermThrottleEnable = 1;
  3178. table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
  3179. table->PCIeGenInterval = 1;
  3180. if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
  3181. table->SVI2Enable = 1;
  3182. else
  3183. table->SVI2Enable = 0;
  3184. table->ThermGpio = 17;
  3185. table->SclkStepSize = 0x4000;
  3186. table->SystemFlags = cpu_to_be32(table->SystemFlags);
  3187. table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
  3188. table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
  3189. table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
  3190. table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
  3191. table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
  3192. table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
  3193. table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
  3194. table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
  3195. table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
  3196. table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
  3197. table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
  3198. table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
  3199. table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
  3200. ret = amdgpu_ci_copy_bytes_to_smc(adev,
  3201. pi->dpm_table_start +
  3202. offsetof(SMU7_Discrete_DpmTable, SystemFlags),
  3203. (u8 *)&table->SystemFlags,
  3204. sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
  3205. pi->sram_end);
  3206. if (ret)
  3207. return ret;
  3208. ci_save_default_power_profile(adev);
  3209. return 0;
  3210. }
  3211. static void ci_trim_single_dpm_states(struct amdgpu_device *adev,
  3212. struct ci_single_dpm_table *dpm_table,
  3213. u32 low_limit, u32 high_limit)
  3214. {
  3215. u32 i;
  3216. for (i = 0; i < dpm_table->count; i++) {
  3217. if ((dpm_table->dpm_levels[i].value < low_limit) ||
  3218. (dpm_table->dpm_levels[i].value > high_limit))
  3219. dpm_table->dpm_levels[i].enabled = false;
  3220. else
  3221. dpm_table->dpm_levels[i].enabled = true;
  3222. }
  3223. }
  3224. static void ci_trim_pcie_dpm_states(struct amdgpu_device *adev,
  3225. u32 speed_low, u32 lanes_low,
  3226. u32 speed_high, u32 lanes_high)
  3227. {
  3228. struct ci_power_info *pi = ci_get_pi(adev);
  3229. struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
  3230. u32 i, j;
  3231. for (i = 0; i < pcie_table->count; i++) {
  3232. if ((pcie_table->dpm_levels[i].value < speed_low) ||
  3233. (pcie_table->dpm_levels[i].param1 < lanes_low) ||
  3234. (pcie_table->dpm_levels[i].value > speed_high) ||
  3235. (pcie_table->dpm_levels[i].param1 > lanes_high))
  3236. pcie_table->dpm_levels[i].enabled = false;
  3237. else
  3238. pcie_table->dpm_levels[i].enabled = true;
  3239. }
  3240. for (i = 0; i < pcie_table->count; i++) {
  3241. if (pcie_table->dpm_levels[i].enabled) {
  3242. for (j = i + 1; j < pcie_table->count; j++) {
  3243. if (pcie_table->dpm_levels[j].enabled) {
  3244. if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
  3245. (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
  3246. pcie_table->dpm_levels[j].enabled = false;
  3247. }
  3248. }
  3249. }
  3250. }
  3251. }
  3252. static int ci_trim_dpm_states(struct amdgpu_device *adev,
  3253. struct amdgpu_ps *amdgpu_state)
  3254. {
  3255. struct ci_ps *state = ci_get_ps(amdgpu_state);
  3256. struct ci_power_info *pi = ci_get_pi(adev);
  3257. u32 high_limit_count;
  3258. if (state->performance_level_count < 1)
  3259. return -EINVAL;
  3260. if (state->performance_level_count == 1)
  3261. high_limit_count = 0;
  3262. else
  3263. high_limit_count = 1;
  3264. ci_trim_single_dpm_states(adev,
  3265. &pi->dpm_table.sclk_table,
  3266. state->performance_levels[0].sclk,
  3267. state->performance_levels[high_limit_count].sclk);
  3268. ci_trim_single_dpm_states(adev,
  3269. &pi->dpm_table.mclk_table,
  3270. state->performance_levels[0].mclk,
  3271. state->performance_levels[high_limit_count].mclk);
  3272. ci_trim_pcie_dpm_states(adev,
  3273. state->performance_levels[0].pcie_gen,
  3274. state->performance_levels[0].pcie_lane,
  3275. state->performance_levels[high_limit_count].pcie_gen,
  3276. state->performance_levels[high_limit_count].pcie_lane);
  3277. return 0;
  3278. }
  3279. static int ci_apply_disp_minimum_voltage_request(struct amdgpu_device *adev)
  3280. {
  3281. struct amdgpu_clock_voltage_dependency_table *disp_voltage_table =
  3282. &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
  3283. struct amdgpu_clock_voltage_dependency_table *vddc_table =
  3284. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  3285. u32 requested_voltage = 0;
  3286. u32 i;
  3287. if (disp_voltage_table == NULL)
  3288. return -EINVAL;
  3289. if (!disp_voltage_table->count)
  3290. return -EINVAL;
  3291. for (i = 0; i < disp_voltage_table->count; i++) {
  3292. if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
  3293. requested_voltage = disp_voltage_table->entries[i].v;
  3294. }
  3295. for (i = 0; i < vddc_table->count; i++) {
  3296. if (requested_voltage <= vddc_table->entries[i].v) {
  3297. requested_voltage = vddc_table->entries[i].v;
  3298. return (amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3299. PPSMC_MSG_VddC_Request,
  3300. requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
  3301. 0 : -EINVAL;
  3302. }
  3303. }
  3304. return -EINVAL;
  3305. }
  3306. static int ci_upload_dpm_level_enable_mask(struct amdgpu_device *adev)
  3307. {
  3308. struct ci_power_info *pi = ci_get_pi(adev);
  3309. PPSMC_Result result;
  3310. ci_apply_disp_minimum_voltage_request(adev);
  3311. if (!pi->sclk_dpm_key_disabled) {
  3312. if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
  3313. result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3314. PPSMC_MSG_SCLKDPM_SetEnabledMask,
  3315. pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
  3316. if (result != PPSMC_Result_OK)
  3317. return -EINVAL;
  3318. }
  3319. }
  3320. if (!pi->mclk_dpm_key_disabled) {
  3321. if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
  3322. result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3323. PPSMC_MSG_MCLKDPM_SetEnabledMask,
  3324. pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
  3325. if (result != PPSMC_Result_OK)
  3326. return -EINVAL;
  3327. }
  3328. }
  3329. #if 0
  3330. if (!pi->pcie_dpm_key_disabled) {
  3331. if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
  3332. result = amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3333. PPSMC_MSG_PCIeDPM_SetEnabledMask,
  3334. pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
  3335. if (result != PPSMC_Result_OK)
  3336. return -EINVAL;
  3337. }
  3338. }
  3339. #endif
  3340. return 0;
  3341. }
  3342. static void ci_find_dpm_states_clocks_in_dpm_table(struct amdgpu_device *adev,
  3343. struct amdgpu_ps *amdgpu_state)
  3344. {
  3345. struct ci_power_info *pi = ci_get_pi(adev);
  3346. struct ci_ps *state = ci_get_ps(amdgpu_state);
  3347. struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
  3348. u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
  3349. struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
  3350. u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
  3351. u32 i;
  3352. pi->need_update_smu7_dpm_table = 0;
  3353. for (i = 0; i < sclk_table->count; i++) {
  3354. if (sclk == sclk_table->dpm_levels[i].value)
  3355. break;
  3356. }
  3357. if (i >= sclk_table->count) {
  3358. pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
  3359. } else {
  3360. /* XXX check display min clock requirements */
  3361. if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
  3362. pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
  3363. }
  3364. for (i = 0; i < mclk_table->count; i++) {
  3365. if (mclk == mclk_table->dpm_levels[i].value)
  3366. break;
  3367. }
  3368. if (i >= mclk_table->count)
  3369. pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
  3370. if (adev->pm.dpm.current_active_crtc_count !=
  3371. adev->pm.dpm.new_active_crtc_count)
  3372. pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
  3373. }
  3374. static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct amdgpu_device *adev,
  3375. struct amdgpu_ps *amdgpu_state)
  3376. {
  3377. struct ci_power_info *pi = ci_get_pi(adev);
  3378. struct ci_ps *state = ci_get_ps(amdgpu_state);
  3379. u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
  3380. u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
  3381. struct ci_dpm_table *dpm_table = &pi->dpm_table;
  3382. int ret;
  3383. if (!pi->need_update_smu7_dpm_table)
  3384. return 0;
  3385. if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
  3386. dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
  3387. if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
  3388. dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
  3389. if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
  3390. ret = ci_populate_all_graphic_levels(adev);
  3391. if (ret)
  3392. return ret;
  3393. }
  3394. if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
  3395. ret = ci_populate_all_memory_levels(adev);
  3396. if (ret)
  3397. return ret;
  3398. }
  3399. return 0;
  3400. }
  3401. static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
  3402. {
  3403. struct ci_power_info *pi = ci_get_pi(adev);
  3404. const struct amdgpu_clock_and_voltage_limits *max_limits;
  3405. int i;
  3406. if (adev->pm.dpm.ac_power)
  3407. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  3408. else
  3409. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
  3410. if (enable) {
  3411. pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
  3412. for (i = adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
  3413. if (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
  3414. pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
  3415. if (!pi->caps_uvd_dpm)
  3416. break;
  3417. }
  3418. }
  3419. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3420. PPSMC_MSG_UVDDPM_SetEnabledMask,
  3421. pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
  3422. if (pi->last_mclk_dpm_enable_mask & 0x1) {
  3423. pi->uvd_enabled = true;
  3424. pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
  3425. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3426. PPSMC_MSG_MCLKDPM_SetEnabledMask,
  3427. pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
  3428. }
  3429. } else {
  3430. if (pi->uvd_enabled) {
  3431. pi->uvd_enabled = false;
  3432. pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
  3433. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3434. PPSMC_MSG_MCLKDPM_SetEnabledMask,
  3435. pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
  3436. }
  3437. }
  3438. return (amdgpu_ci_send_msg_to_smc(adev, enable ?
  3439. PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
  3440. 0 : -EINVAL;
  3441. }
  3442. static int ci_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
  3443. {
  3444. struct ci_power_info *pi = ci_get_pi(adev);
  3445. const struct amdgpu_clock_and_voltage_limits *max_limits;
  3446. int i;
  3447. if (adev->pm.dpm.ac_power)
  3448. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  3449. else
  3450. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
  3451. if (enable) {
  3452. pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
  3453. for (i = adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
  3454. if (adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
  3455. pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
  3456. if (!pi->caps_vce_dpm)
  3457. break;
  3458. }
  3459. }
  3460. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3461. PPSMC_MSG_VCEDPM_SetEnabledMask,
  3462. pi->dpm_level_enable_mask.vce_dpm_enable_mask);
  3463. }
  3464. return (amdgpu_ci_send_msg_to_smc(adev, enable ?
  3465. PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
  3466. 0 : -EINVAL;
  3467. }
  3468. #if 0
  3469. static int ci_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
  3470. {
  3471. struct ci_power_info *pi = ci_get_pi(adev);
  3472. const struct amdgpu_clock_and_voltage_limits *max_limits;
  3473. int i;
  3474. if (adev->pm.dpm.ac_power)
  3475. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  3476. else
  3477. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
  3478. if (enable) {
  3479. pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
  3480. for (i = adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
  3481. if (adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
  3482. pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
  3483. if (!pi->caps_samu_dpm)
  3484. break;
  3485. }
  3486. }
  3487. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3488. PPSMC_MSG_SAMUDPM_SetEnabledMask,
  3489. pi->dpm_level_enable_mask.samu_dpm_enable_mask);
  3490. }
  3491. return (amdgpu_ci_send_msg_to_smc(adev, enable ?
  3492. PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
  3493. 0 : -EINVAL;
  3494. }
  3495. static int ci_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
  3496. {
  3497. struct ci_power_info *pi = ci_get_pi(adev);
  3498. const struct amdgpu_clock_and_voltage_limits *max_limits;
  3499. int i;
  3500. if (adev->pm.dpm.ac_power)
  3501. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  3502. else
  3503. max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
  3504. if (enable) {
  3505. pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
  3506. for (i = adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
  3507. if (adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
  3508. pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
  3509. if (!pi->caps_acp_dpm)
  3510. break;
  3511. }
  3512. }
  3513. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  3514. PPSMC_MSG_ACPDPM_SetEnabledMask,
  3515. pi->dpm_level_enable_mask.acp_dpm_enable_mask);
  3516. }
  3517. return (amdgpu_ci_send_msg_to_smc(adev, enable ?
  3518. PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
  3519. 0 : -EINVAL;
  3520. }
  3521. #endif
  3522. static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
  3523. {
  3524. struct ci_power_info *pi = ci_get_pi(adev);
  3525. u32 tmp;
  3526. int ret = 0;
  3527. if (!gate) {
  3528. /* turn the clocks on when decoding */
  3529. if (pi->caps_uvd_dpm ||
  3530. (adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
  3531. pi->smc_state_table.UvdBootLevel = 0;
  3532. else
  3533. pi->smc_state_table.UvdBootLevel =
  3534. adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
  3535. tmp = RREG32_SMC(ixDPM_TABLE_475);
  3536. tmp &= ~DPM_TABLE_475__UvdBootLevel_MASK;
  3537. tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);
  3538. WREG32_SMC(ixDPM_TABLE_475, tmp);
  3539. ret = ci_enable_uvd_dpm(adev, true);
  3540. } else {
  3541. ret = ci_enable_uvd_dpm(adev, false);
  3542. if (ret)
  3543. return ret;
  3544. }
  3545. return ret;
  3546. }
  3547. static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)
  3548. {
  3549. u8 i;
  3550. u32 min_evclk = 30000; /* ??? */
  3551. struct amdgpu_vce_clock_voltage_dependency_table *table =
  3552. &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
  3553. for (i = 0; i < table->count; i++) {
  3554. if (table->entries[i].evclk >= min_evclk)
  3555. return i;
  3556. }
  3557. return table->count - 1;
  3558. }
  3559. static int ci_update_vce_dpm(struct amdgpu_device *adev,
  3560. struct amdgpu_ps *amdgpu_new_state,
  3561. struct amdgpu_ps *amdgpu_current_state)
  3562. {
  3563. struct ci_power_info *pi = ci_get_pi(adev);
  3564. int ret = 0;
  3565. u32 tmp;
  3566. if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) {
  3567. if (amdgpu_new_state->evclk) {
  3568. pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);
  3569. tmp = RREG32_SMC(ixDPM_TABLE_475);
  3570. tmp &= ~DPM_TABLE_475__VceBootLevel_MASK;
  3571. tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);
  3572. WREG32_SMC(ixDPM_TABLE_475, tmp);
  3573. ret = ci_enable_vce_dpm(adev, true);
  3574. } else {
  3575. ret = ci_enable_vce_dpm(adev, false);
  3576. if (ret)
  3577. return ret;
  3578. }
  3579. }
  3580. return ret;
  3581. }
  3582. #if 0
  3583. static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
  3584. {
  3585. return ci_enable_samu_dpm(adev, gate);
  3586. }
  3587. static int ci_update_acp_dpm(struct amdgpu_device *adev, bool gate)
  3588. {
  3589. struct ci_power_info *pi = ci_get_pi(adev);
  3590. u32 tmp;
  3591. if (!gate) {
  3592. pi->smc_state_table.AcpBootLevel = 0;
  3593. tmp = RREG32_SMC(ixDPM_TABLE_475);
  3594. tmp &= ~AcpBootLevel_MASK;
  3595. tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
  3596. WREG32_SMC(ixDPM_TABLE_475, tmp);
  3597. }
  3598. return ci_enable_acp_dpm(adev, !gate);
  3599. }
  3600. #endif
  3601. static int ci_generate_dpm_level_enable_mask(struct amdgpu_device *adev,
  3602. struct amdgpu_ps *amdgpu_state)
  3603. {
  3604. struct ci_power_info *pi = ci_get_pi(adev);
  3605. int ret;
  3606. ret = ci_trim_dpm_states(adev, amdgpu_state);
  3607. if (ret)
  3608. return ret;
  3609. pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
  3610. ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
  3611. pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
  3612. ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
  3613. pi->last_mclk_dpm_enable_mask =
  3614. pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
  3615. if (pi->uvd_enabled) {
  3616. if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
  3617. pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
  3618. }
  3619. pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
  3620. ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
  3621. return 0;
  3622. }
  3623. static u32 ci_get_lowest_enabled_level(struct amdgpu_device *adev,
  3624. u32 level_mask)
  3625. {
  3626. u32 level = 0;
  3627. while ((level_mask & (1 << level)) == 0)
  3628. level++;
  3629. return level;
  3630. }
  3631. static int ci_dpm_force_performance_level(struct amdgpu_device *adev,
  3632. enum amd_dpm_forced_level level)
  3633. {
  3634. struct ci_power_info *pi = ci_get_pi(adev);
  3635. u32 tmp, levels, i;
  3636. int ret;
  3637. if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
  3638. if ((!pi->pcie_dpm_key_disabled) &&
  3639. pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
  3640. levels = 0;
  3641. tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
  3642. while (tmp >>= 1)
  3643. levels++;
  3644. if (levels) {
  3645. ret = ci_dpm_force_state_pcie(adev, level);
  3646. if (ret)
  3647. return ret;
  3648. for (i = 0; i < adev->usec_timeout; i++) {
  3649. tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
  3650. TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
  3651. TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
  3652. if (tmp == levels)
  3653. break;
  3654. udelay(1);
  3655. }
  3656. }
  3657. }
  3658. if ((!pi->sclk_dpm_key_disabled) &&
  3659. pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
  3660. levels = 0;
  3661. tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
  3662. while (tmp >>= 1)
  3663. levels++;
  3664. if (levels) {
  3665. ret = ci_dpm_force_state_sclk(adev, levels);
  3666. if (ret)
  3667. return ret;
  3668. for (i = 0; i < adev->usec_timeout; i++) {
  3669. tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
  3670. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
  3671. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
  3672. if (tmp == levels)
  3673. break;
  3674. udelay(1);
  3675. }
  3676. }
  3677. }
  3678. if ((!pi->mclk_dpm_key_disabled) &&
  3679. pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
  3680. levels = 0;
  3681. tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
  3682. while (tmp >>= 1)
  3683. levels++;
  3684. if (levels) {
  3685. ret = ci_dpm_force_state_mclk(adev, levels);
  3686. if (ret)
  3687. return ret;
  3688. for (i = 0; i < adev->usec_timeout; i++) {
  3689. tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
  3690. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
  3691. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
  3692. if (tmp == levels)
  3693. break;
  3694. udelay(1);
  3695. }
  3696. }
  3697. }
  3698. } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
  3699. if ((!pi->sclk_dpm_key_disabled) &&
  3700. pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
  3701. levels = ci_get_lowest_enabled_level(adev,
  3702. pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
  3703. ret = ci_dpm_force_state_sclk(adev, levels);
  3704. if (ret)
  3705. return ret;
  3706. for (i = 0; i < adev->usec_timeout; i++) {
  3707. tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
  3708. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK) >>
  3709. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT;
  3710. if (tmp == levels)
  3711. break;
  3712. udelay(1);
  3713. }
  3714. }
  3715. if ((!pi->mclk_dpm_key_disabled) &&
  3716. pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
  3717. levels = ci_get_lowest_enabled_level(adev,
  3718. pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
  3719. ret = ci_dpm_force_state_mclk(adev, levels);
  3720. if (ret)
  3721. return ret;
  3722. for (i = 0; i < adev->usec_timeout; i++) {
  3723. tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) &
  3724. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK) >>
  3725. TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT;
  3726. if (tmp == levels)
  3727. break;
  3728. udelay(1);
  3729. }
  3730. }
  3731. if ((!pi->pcie_dpm_key_disabled) &&
  3732. pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
  3733. levels = ci_get_lowest_enabled_level(adev,
  3734. pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
  3735. ret = ci_dpm_force_state_pcie(adev, levels);
  3736. if (ret)
  3737. return ret;
  3738. for (i = 0; i < adev->usec_timeout; i++) {
  3739. tmp = (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX_1) &
  3740. TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK) >>
  3741. TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT;
  3742. if (tmp == levels)
  3743. break;
  3744. udelay(1);
  3745. }
  3746. }
  3747. } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
  3748. if (!pi->pcie_dpm_key_disabled) {
  3749. PPSMC_Result smc_result;
  3750. smc_result = amdgpu_ci_send_msg_to_smc(adev,
  3751. PPSMC_MSG_PCIeDPM_UnForceLevel);
  3752. if (smc_result != PPSMC_Result_OK)
  3753. return -EINVAL;
  3754. }
  3755. ret = ci_upload_dpm_level_enable_mask(adev);
  3756. if (ret)
  3757. return ret;
  3758. }
  3759. adev->pm.dpm.forced_level = level;
  3760. return 0;
  3761. }
  3762. static int ci_set_mc_special_registers(struct amdgpu_device *adev,
  3763. struct ci_mc_reg_table *table)
  3764. {
  3765. u8 i, j, k;
  3766. u32 temp_reg;
  3767. for (i = 0, j = table->last; i < table->last; i++) {
  3768. if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3769. return -EINVAL;
  3770. switch(table->mc_reg_address[i].s1) {
  3771. case mmMC_SEQ_MISC1:
  3772. temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
  3773. table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
  3774. table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
  3775. for (k = 0; k < table->num_entries; k++) {
  3776. table->mc_reg_table_entry[k].mc_data[j] =
  3777. ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
  3778. }
  3779. j++;
  3780. if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3781. return -EINVAL;
  3782. temp_reg = RREG32(mmMC_PMG_CMD_MRS);
  3783. table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
  3784. table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
  3785. for (k = 0; k < table->num_entries; k++) {
  3786. table->mc_reg_table_entry[k].mc_data[j] =
  3787. (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
  3788. if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
  3789. table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
  3790. }
  3791. j++;
  3792. if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3793. return -EINVAL;
  3794. if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
  3795. table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
  3796. table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
  3797. for (k = 0; k < table->num_entries; k++) {
  3798. table->mc_reg_table_entry[k].mc_data[j] =
  3799. (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
  3800. }
  3801. j++;
  3802. if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3803. return -EINVAL;
  3804. }
  3805. break;
  3806. case mmMC_SEQ_RESERVE_M:
  3807. temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
  3808. table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
  3809. table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
  3810. for (k = 0; k < table->num_entries; k++) {
  3811. table->mc_reg_table_entry[k].mc_data[j] =
  3812. (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
  3813. }
  3814. j++;
  3815. if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3816. return -EINVAL;
  3817. break;
  3818. default:
  3819. break;
  3820. }
  3821. }
  3822. table->last = j;
  3823. return 0;
  3824. }
  3825. static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
  3826. {
  3827. bool result = true;
  3828. switch(in_reg) {
  3829. case mmMC_SEQ_RAS_TIMING:
  3830. *out_reg = mmMC_SEQ_RAS_TIMING_LP;
  3831. break;
  3832. case mmMC_SEQ_DLL_STBY:
  3833. *out_reg = mmMC_SEQ_DLL_STBY_LP;
  3834. break;
  3835. case mmMC_SEQ_G5PDX_CMD0:
  3836. *out_reg = mmMC_SEQ_G5PDX_CMD0_LP;
  3837. break;
  3838. case mmMC_SEQ_G5PDX_CMD1:
  3839. *out_reg = mmMC_SEQ_G5PDX_CMD1_LP;
  3840. break;
  3841. case mmMC_SEQ_G5PDX_CTRL:
  3842. *out_reg = mmMC_SEQ_G5PDX_CTRL_LP;
  3843. break;
  3844. case mmMC_SEQ_CAS_TIMING:
  3845. *out_reg = mmMC_SEQ_CAS_TIMING_LP;
  3846. break;
  3847. case mmMC_SEQ_MISC_TIMING:
  3848. *out_reg = mmMC_SEQ_MISC_TIMING_LP;
  3849. break;
  3850. case mmMC_SEQ_MISC_TIMING2:
  3851. *out_reg = mmMC_SEQ_MISC_TIMING2_LP;
  3852. break;
  3853. case mmMC_SEQ_PMG_DVS_CMD:
  3854. *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP;
  3855. break;
  3856. case mmMC_SEQ_PMG_DVS_CTL:
  3857. *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP;
  3858. break;
  3859. case mmMC_SEQ_RD_CTL_D0:
  3860. *out_reg = mmMC_SEQ_RD_CTL_D0_LP;
  3861. break;
  3862. case mmMC_SEQ_RD_CTL_D1:
  3863. *out_reg = mmMC_SEQ_RD_CTL_D1_LP;
  3864. break;
  3865. case mmMC_SEQ_WR_CTL_D0:
  3866. *out_reg = mmMC_SEQ_WR_CTL_D0_LP;
  3867. break;
  3868. case mmMC_SEQ_WR_CTL_D1:
  3869. *out_reg = mmMC_SEQ_WR_CTL_D1_LP;
  3870. break;
  3871. case mmMC_PMG_CMD_EMRS:
  3872. *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP;
  3873. break;
  3874. case mmMC_PMG_CMD_MRS:
  3875. *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP;
  3876. break;
  3877. case mmMC_PMG_CMD_MRS1:
  3878. *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP;
  3879. break;
  3880. case mmMC_SEQ_PMG_TIMING:
  3881. *out_reg = mmMC_SEQ_PMG_TIMING_LP;
  3882. break;
  3883. case mmMC_PMG_CMD_MRS2:
  3884. *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP;
  3885. break;
  3886. case mmMC_SEQ_WR_CTL_2:
  3887. *out_reg = mmMC_SEQ_WR_CTL_2_LP;
  3888. break;
  3889. default:
  3890. result = false;
  3891. break;
  3892. }
  3893. return result;
  3894. }
  3895. static void ci_set_valid_flag(struct ci_mc_reg_table *table)
  3896. {
  3897. u8 i, j;
  3898. for (i = 0; i < table->last; i++) {
  3899. for (j = 1; j < table->num_entries; j++) {
  3900. if (table->mc_reg_table_entry[j-1].mc_data[i] !=
  3901. table->mc_reg_table_entry[j].mc_data[i]) {
  3902. table->valid_flag |= 1 << i;
  3903. break;
  3904. }
  3905. }
  3906. }
  3907. }
  3908. static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
  3909. {
  3910. u32 i;
  3911. u16 address;
  3912. for (i = 0; i < table->last; i++) {
  3913. table->mc_reg_address[i].s0 =
  3914. ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
  3915. address : table->mc_reg_address[i].s1;
  3916. }
  3917. }
  3918. static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
  3919. struct ci_mc_reg_table *ci_table)
  3920. {
  3921. u8 i, j;
  3922. if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3923. return -EINVAL;
  3924. if (table->num_entries > MAX_AC_TIMING_ENTRIES)
  3925. return -EINVAL;
  3926. for (i = 0; i < table->last; i++)
  3927. ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
  3928. ci_table->last = table->last;
  3929. for (i = 0; i < table->num_entries; i++) {
  3930. ci_table->mc_reg_table_entry[i].mclk_max =
  3931. table->mc_reg_table_entry[i].mclk_max;
  3932. for (j = 0; j < table->last; j++)
  3933. ci_table->mc_reg_table_entry[i].mc_data[j] =
  3934. table->mc_reg_table_entry[i].mc_data[j];
  3935. }
  3936. ci_table->num_entries = table->num_entries;
  3937. return 0;
  3938. }
  3939. static int ci_register_patching_mc_seq(struct amdgpu_device *adev,
  3940. struct ci_mc_reg_table *table)
  3941. {
  3942. u8 i, k;
  3943. u32 tmp;
  3944. bool patch;
  3945. tmp = RREG32(mmMC_SEQ_MISC0);
  3946. patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
  3947. if (patch &&
  3948. ((adev->pdev->device == 0x67B0) ||
  3949. (adev->pdev->device == 0x67B1))) {
  3950. for (i = 0; i < table->last; i++) {
  3951. if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  3952. return -EINVAL;
  3953. switch (table->mc_reg_address[i].s1) {
  3954. case mmMC_SEQ_MISC1:
  3955. for (k = 0; k < table->num_entries; k++) {
  3956. if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
  3957. (table->mc_reg_table_entry[k].mclk_max == 137500))
  3958. table->mc_reg_table_entry[k].mc_data[i] =
  3959. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
  3960. 0x00000007;
  3961. }
  3962. break;
  3963. case mmMC_SEQ_WR_CTL_D0:
  3964. for (k = 0; k < table->num_entries; k++) {
  3965. if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
  3966. (table->mc_reg_table_entry[k].mclk_max == 137500))
  3967. table->mc_reg_table_entry[k].mc_data[i] =
  3968. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
  3969. 0x0000D0DD;
  3970. }
  3971. break;
  3972. case mmMC_SEQ_WR_CTL_D1:
  3973. for (k = 0; k < table->num_entries; k++) {
  3974. if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
  3975. (table->mc_reg_table_entry[k].mclk_max == 137500))
  3976. table->mc_reg_table_entry[k].mc_data[i] =
  3977. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
  3978. 0x0000D0DD;
  3979. }
  3980. break;
  3981. case mmMC_SEQ_WR_CTL_2:
  3982. for (k = 0; k < table->num_entries; k++) {
  3983. if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
  3984. (table->mc_reg_table_entry[k].mclk_max == 137500))
  3985. table->mc_reg_table_entry[k].mc_data[i] = 0;
  3986. }
  3987. break;
  3988. case mmMC_SEQ_CAS_TIMING:
  3989. for (k = 0; k < table->num_entries; k++) {
  3990. if (table->mc_reg_table_entry[k].mclk_max == 125000)
  3991. table->mc_reg_table_entry[k].mc_data[i] =
  3992. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
  3993. 0x000C0140;
  3994. else if (table->mc_reg_table_entry[k].mclk_max == 137500)
  3995. table->mc_reg_table_entry[k].mc_data[i] =
  3996. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
  3997. 0x000C0150;
  3998. }
  3999. break;
  4000. case mmMC_SEQ_MISC_TIMING:
  4001. for (k = 0; k < table->num_entries; k++) {
  4002. if (table->mc_reg_table_entry[k].mclk_max == 125000)
  4003. table->mc_reg_table_entry[k].mc_data[i] =
  4004. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
  4005. 0x00000030;
  4006. else if (table->mc_reg_table_entry[k].mclk_max == 137500)
  4007. table->mc_reg_table_entry[k].mc_data[i] =
  4008. (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
  4009. 0x00000035;
  4010. }
  4011. break;
  4012. default:
  4013. break;
  4014. }
  4015. }
  4016. WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
  4017. tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
  4018. tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
  4019. WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);
  4020. WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);
  4021. }
  4022. return 0;
  4023. }
  4024. static int ci_initialize_mc_reg_table(struct amdgpu_device *adev)
  4025. {
  4026. struct ci_power_info *pi = ci_get_pi(adev);
  4027. struct atom_mc_reg_table *table;
  4028. struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
  4029. u8 module_index = ci_get_memory_module_index(adev);
  4030. int ret;
  4031. table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
  4032. if (!table)
  4033. return -ENOMEM;
  4034. WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
  4035. WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
  4036. WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
  4037. WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
  4038. WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
  4039. WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
  4040. WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
  4041. WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
  4042. WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
  4043. WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
  4044. WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
  4045. WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
  4046. WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
  4047. WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
  4048. WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
  4049. WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
  4050. WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
  4051. WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
  4052. WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
  4053. WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
  4054. ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
  4055. if (ret)
  4056. goto init_mc_done;
  4057. ret = ci_copy_vbios_mc_reg_table(table, ci_table);
  4058. if (ret)
  4059. goto init_mc_done;
  4060. ci_set_s0_mc_reg_index(ci_table);
  4061. ret = ci_register_patching_mc_seq(adev, ci_table);
  4062. if (ret)
  4063. goto init_mc_done;
  4064. ret = ci_set_mc_special_registers(adev, ci_table);
  4065. if (ret)
  4066. goto init_mc_done;
  4067. ci_set_valid_flag(ci_table);
  4068. init_mc_done:
  4069. kfree(table);
  4070. return ret;
  4071. }
  4072. static int ci_populate_mc_reg_addresses(struct amdgpu_device *adev,
  4073. SMU7_Discrete_MCRegisters *mc_reg_table)
  4074. {
  4075. struct ci_power_info *pi = ci_get_pi(adev);
  4076. u32 i, j;
  4077. for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
  4078. if (pi->mc_reg_table.valid_flag & (1 << j)) {
  4079. if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
  4080. return -EINVAL;
  4081. mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
  4082. mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
  4083. i++;
  4084. }
  4085. }
  4086. mc_reg_table->last = (u8)i;
  4087. return 0;
  4088. }
  4089. static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
  4090. SMU7_Discrete_MCRegisterSet *data,
  4091. u32 num_entries, u32 valid_flag)
  4092. {
  4093. u32 i, j;
  4094. for (i = 0, j = 0; j < num_entries; j++) {
  4095. if (valid_flag & (1 << j)) {
  4096. data->value[i] = cpu_to_be32(entry->mc_data[j]);
  4097. i++;
  4098. }
  4099. }
  4100. }
  4101. static void ci_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
  4102. const u32 memory_clock,
  4103. SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
  4104. {
  4105. struct ci_power_info *pi = ci_get_pi(adev);
  4106. u32 i = 0;
  4107. for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
  4108. if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
  4109. break;
  4110. }
  4111. if ((i == pi->mc_reg_table.num_entries) && (i > 0))
  4112. --i;
  4113. ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
  4114. mc_reg_table_data, pi->mc_reg_table.last,
  4115. pi->mc_reg_table.valid_flag);
  4116. }
  4117. static void ci_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
  4118. SMU7_Discrete_MCRegisters *mc_reg_table)
  4119. {
  4120. struct ci_power_info *pi = ci_get_pi(adev);
  4121. u32 i;
  4122. for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
  4123. ci_convert_mc_reg_table_entry_to_smc(adev,
  4124. pi->dpm_table.mclk_table.dpm_levels[i].value,
  4125. &mc_reg_table->data[i]);
  4126. }
  4127. static int ci_populate_initial_mc_reg_table(struct amdgpu_device *adev)
  4128. {
  4129. struct ci_power_info *pi = ci_get_pi(adev);
  4130. int ret;
  4131. memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
  4132. ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);
  4133. if (ret)
  4134. return ret;
  4135. ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
  4136. return amdgpu_ci_copy_bytes_to_smc(adev,
  4137. pi->mc_reg_table_start,
  4138. (u8 *)&pi->smc_mc_reg_table,
  4139. sizeof(SMU7_Discrete_MCRegisters),
  4140. pi->sram_end);
  4141. }
  4142. static int ci_update_and_upload_mc_reg_table(struct amdgpu_device *adev)
  4143. {
  4144. struct ci_power_info *pi = ci_get_pi(adev);
  4145. if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
  4146. return 0;
  4147. memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
  4148. ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);
  4149. return amdgpu_ci_copy_bytes_to_smc(adev,
  4150. pi->mc_reg_table_start +
  4151. offsetof(SMU7_Discrete_MCRegisters, data[0]),
  4152. (u8 *)&pi->smc_mc_reg_table.data[0],
  4153. sizeof(SMU7_Discrete_MCRegisterSet) *
  4154. pi->dpm_table.mclk_table.count,
  4155. pi->sram_end);
  4156. }
  4157. static void ci_enable_voltage_control(struct amdgpu_device *adev)
  4158. {
  4159. u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
  4160. tmp |= GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK;
  4161. WREG32_SMC(ixGENERAL_PWRMGT, tmp);
  4162. }
  4163. static enum amdgpu_pcie_gen ci_get_maximum_link_speed(struct amdgpu_device *adev,
  4164. struct amdgpu_ps *amdgpu_state)
  4165. {
  4166. struct ci_ps *state = ci_get_ps(amdgpu_state);
  4167. int i;
  4168. u16 pcie_speed, max_speed = 0;
  4169. for (i = 0; i < state->performance_level_count; i++) {
  4170. pcie_speed = state->performance_levels[i].pcie_gen;
  4171. if (max_speed < pcie_speed)
  4172. max_speed = pcie_speed;
  4173. }
  4174. return max_speed;
  4175. }
  4176. static u16 ci_get_current_pcie_speed(struct amdgpu_device *adev)
  4177. {
  4178. u32 speed_cntl = 0;
  4179. speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL) &
  4180. PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK;
  4181. speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
  4182. return (u16)speed_cntl;
  4183. }
  4184. static int ci_get_current_pcie_lane_number(struct amdgpu_device *adev)
  4185. {
  4186. u32 link_width = 0;
  4187. link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) &
  4188. PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK;
  4189. link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
  4190. switch (link_width) {
  4191. case 1:
  4192. return 1;
  4193. case 2:
  4194. return 2;
  4195. case 3:
  4196. return 4;
  4197. case 4:
  4198. return 8;
  4199. case 0:
  4200. case 6:
  4201. default:
  4202. return 16;
  4203. }
  4204. }
  4205. static void ci_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
  4206. struct amdgpu_ps *amdgpu_new_state,
  4207. struct amdgpu_ps *amdgpu_current_state)
  4208. {
  4209. struct ci_power_info *pi = ci_get_pi(adev);
  4210. enum amdgpu_pcie_gen target_link_speed =
  4211. ci_get_maximum_link_speed(adev, amdgpu_new_state);
  4212. enum amdgpu_pcie_gen current_link_speed;
  4213. if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
  4214. current_link_speed = ci_get_maximum_link_speed(adev, amdgpu_current_state);
  4215. else
  4216. current_link_speed = pi->force_pcie_gen;
  4217. pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
  4218. pi->pspp_notify_required = false;
  4219. if (target_link_speed > current_link_speed) {
  4220. switch (target_link_speed) {
  4221. #ifdef CONFIG_ACPI
  4222. case AMDGPU_PCIE_GEN3:
  4223. if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
  4224. break;
  4225. pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
  4226. if (current_link_speed == AMDGPU_PCIE_GEN2)
  4227. break;
  4228. case AMDGPU_PCIE_GEN2:
  4229. if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
  4230. break;
  4231. #endif
  4232. default:
  4233. pi->force_pcie_gen = ci_get_current_pcie_speed(adev);
  4234. break;
  4235. }
  4236. } else {
  4237. if (target_link_speed < current_link_speed)
  4238. pi->pspp_notify_required = true;
  4239. }
  4240. }
  4241. static void ci_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
  4242. struct amdgpu_ps *amdgpu_new_state,
  4243. struct amdgpu_ps *amdgpu_current_state)
  4244. {
  4245. struct ci_power_info *pi = ci_get_pi(adev);
  4246. enum amdgpu_pcie_gen target_link_speed =
  4247. ci_get_maximum_link_speed(adev, amdgpu_new_state);
  4248. u8 request;
  4249. if (pi->pspp_notify_required) {
  4250. if (target_link_speed == AMDGPU_PCIE_GEN3)
  4251. request = PCIE_PERF_REQ_PECI_GEN3;
  4252. else if (target_link_speed == AMDGPU_PCIE_GEN2)
  4253. request = PCIE_PERF_REQ_PECI_GEN2;
  4254. else
  4255. request = PCIE_PERF_REQ_PECI_GEN1;
  4256. if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
  4257. (ci_get_current_pcie_speed(adev) > 0))
  4258. return;
  4259. #ifdef CONFIG_ACPI
  4260. amdgpu_acpi_pcie_performance_request(adev, request, false);
  4261. #endif
  4262. }
  4263. }
  4264. static int ci_set_private_data_variables_based_on_pptable(struct amdgpu_device *adev)
  4265. {
  4266. struct ci_power_info *pi = ci_get_pi(adev);
  4267. struct amdgpu_clock_voltage_dependency_table *allowed_sclk_vddc_table =
  4268. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  4269. struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddc_table =
  4270. &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
  4271. struct amdgpu_clock_voltage_dependency_table *allowed_mclk_vddci_table =
  4272. &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
  4273. if (allowed_sclk_vddc_table == NULL)
  4274. return -EINVAL;
  4275. if (allowed_sclk_vddc_table->count < 1)
  4276. return -EINVAL;
  4277. if (allowed_mclk_vddc_table == NULL)
  4278. return -EINVAL;
  4279. if (allowed_mclk_vddc_table->count < 1)
  4280. return -EINVAL;
  4281. if (allowed_mclk_vddci_table == NULL)
  4282. return -EINVAL;
  4283. if (allowed_mclk_vddci_table->count < 1)
  4284. return -EINVAL;
  4285. pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
  4286. pi->max_vddc_in_pp_table =
  4287. allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
  4288. pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
  4289. pi->max_vddci_in_pp_table =
  4290. allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
  4291. adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
  4292. allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
  4293. adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
  4294. allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
  4295. adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
  4296. allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
  4297. adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
  4298. allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
  4299. return 0;
  4300. }
  4301. static void ci_patch_with_vddc_leakage(struct amdgpu_device *adev, u16 *vddc)
  4302. {
  4303. struct ci_power_info *pi = ci_get_pi(adev);
  4304. struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
  4305. u32 leakage_index;
  4306. for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
  4307. if (leakage_table->leakage_id[leakage_index] == *vddc) {
  4308. *vddc = leakage_table->actual_voltage[leakage_index];
  4309. break;
  4310. }
  4311. }
  4312. }
  4313. static void ci_patch_with_vddci_leakage(struct amdgpu_device *adev, u16 *vddci)
  4314. {
  4315. struct ci_power_info *pi = ci_get_pi(adev);
  4316. struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
  4317. u32 leakage_index;
  4318. for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
  4319. if (leakage_table->leakage_id[leakage_index] == *vddci) {
  4320. *vddci = leakage_table->actual_voltage[leakage_index];
  4321. break;
  4322. }
  4323. }
  4324. }
  4325. static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
  4326. struct amdgpu_clock_voltage_dependency_table *table)
  4327. {
  4328. u32 i;
  4329. if (table) {
  4330. for (i = 0; i < table->count; i++)
  4331. ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
  4332. }
  4333. }
  4334. static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct amdgpu_device *adev,
  4335. struct amdgpu_clock_voltage_dependency_table *table)
  4336. {
  4337. u32 i;
  4338. if (table) {
  4339. for (i = 0; i < table->count; i++)
  4340. ci_patch_with_vddci_leakage(adev, &table->entries[i].v);
  4341. }
  4342. }
  4343. static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
  4344. struct amdgpu_vce_clock_voltage_dependency_table *table)
  4345. {
  4346. u32 i;
  4347. if (table) {
  4348. for (i = 0; i < table->count; i++)
  4349. ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
  4350. }
  4351. }
  4352. static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct amdgpu_device *adev,
  4353. struct amdgpu_uvd_clock_voltage_dependency_table *table)
  4354. {
  4355. u32 i;
  4356. if (table) {
  4357. for (i = 0; i < table->count; i++)
  4358. ci_patch_with_vddc_leakage(adev, &table->entries[i].v);
  4359. }
  4360. }
  4361. static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct amdgpu_device *adev,
  4362. struct amdgpu_phase_shedding_limits_table *table)
  4363. {
  4364. u32 i;
  4365. if (table) {
  4366. for (i = 0; i < table->count; i++)
  4367. ci_patch_with_vddc_leakage(adev, &table->entries[i].voltage);
  4368. }
  4369. }
  4370. static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct amdgpu_device *adev,
  4371. struct amdgpu_clock_and_voltage_limits *table)
  4372. {
  4373. if (table) {
  4374. ci_patch_with_vddc_leakage(adev, (u16 *)&table->vddc);
  4375. ci_patch_with_vddci_leakage(adev, (u16 *)&table->vddci);
  4376. }
  4377. }
  4378. static void ci_patch_cac_leakage_table_with_vddc_leakage(struct amdgpu_device *adev,
  4379. struct amdgpu_cac_leakage_table *table)
  4380. {
  4381. u32 i;
  4382. if (table) {
  4383. for (i = 0; i < table->count; i++)
  4384. ci_patch_with_vddc_leakage(adev, &table->entries[i].vddc);
  4385. }
  4386. }
  4387. static void ci_patch_dependency_tables_with_leakage(struct amdgpu_device *adev)
  4388. {
  4389. ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4390. &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
  4391. ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4392. &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
  4393. ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4394. &adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
  4395. ci_patch_clock_voltage_dependency_table_with_vddci_leakage(adev,
  4396. &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
  4397. ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4398. &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
  4399. ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4400. &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
  4401. ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4402. &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
  4403. ci_patch_clock_voltage_dependency_table_with_vddc_leakage(adev,
  4404. &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
  4405. ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(adev,
  4406. &adev->pm.dpm.dyn_state.phase_shedding_limits_table);
  4407. ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
  4408. &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
  4409. ci_patch_clock_voltage_limits_with_vddc_leakage(adev,
  4410. &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
  4411. ci_patch_cac_leakage_table_with_vddc_leakage(adev,
  4412. &adev->pm.dpm.dyn_state.cac_leakage_table);
  4413. }
  4414. static void ci_update_current_ps(struct amdgpu_device *adev,
  4415. struct amdgpu_ps *rps)
  4416. {
  4417. struct ci_ps *new_ps = ci_get_ps(rps);
  4418. struct ci_power_info *pi = ci_get_pi(adev);
  4419. pi->current_rps = *rps;
  4420. pi->current_ps = *new_ps;
  4421. pi->current_rps.ps_priv = &pi->current_ps;
  4422. adev->pm.dpm.current_ps = &pi->current_rps;
  4423. }
  4424. static void ci_update_requested_ps(struct amdgpu_device *adev,
  4425. struct amdgpu_ps *rps)
  4426. {
  4427. struct ci_ps *new_ps = ci_get_ps(rps);
  4428. struct ci_power_info *pi = ci_get_pi(adev);
  4429. pi->requested_rps = *rps;
  4430. pi->requested_ps = *new_ps;
  4431. pi->requested_rps.ps_priv = &pi->requested_ps;
  4432. adev->pm.dpm.requested_ps = &pi->requested_rps;
  4433. }
  4434. static int ci_dpm_pre_set_power_state(struct amdgpu_device *adev)
  4435. {
  4436. struct ci_power_info *pi = ci_get_pi(adev);
  4437. struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
  4438. struct amdgpu_ps *new_ps = &requested_ps;
  4439. ci_update_requested_ps(adev, new_ps);
  4440. ci_apply_state_adjust_rules(adev, &pi->requested_rps);
  4441. return 0;
  4442. }
  4443. static void ci_dpm_post_set_power_state(struct amdgpu_device *adev)
  4444. {
  4445. struct ci_power_info *pi = ci_get_pi(adev);
  4446. struct amdgpu_ps *new_ps = &pi->requested_rps;
  4447. ci_update_current_ps(adev, new_ps);
  4448. }
  4449. static void ci_dpm_setup_asic(struct amdgpu_device *adev)
  4450. {
  4451. ci_read_clock_registers(adev);
  4452. ci_enable_acpi_power_management(adev);
  4453. ci_init_sclk_t(adev);
  4454. }
  4455. static int ci_dpm_enable(struct amdgpu_device *adev)
  4456. {
  4457. struct ci_power_info *pi = ci_get_pi(adev);
  4458. struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
  4459. int ret;
  4460. if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
  4461. ci_enable_voltage_control(adev);
  4462. ret = ci_construct_voltage_tables(adev);
  4463. if (ret) {
  4464. DRM_ERROR("ci_construct_voltage_tables failed\n");
  4465. return ret;
  4466. }
  4467. }
  4468. if (pi->caps_dynamic_ac_timing) {
  4469. ret = ci_initialize_mc_reg_table(adev);
  4470. if (ret)
  4471. pi->caps_dynamic_ac_timing = false;
  4472. }
  4473. if (pi->dynamic_ss)
  4474. ci_enable_spread_spectrum(adev, true);
  4475. if (pi->thermal_protection)
  4476. ci_enable_thermal_protection(adev, true);
  4477. ci_program_sstp(adev);
  4478. ci_enable_display_gap(adev);
  4479. ci_program_vc(adev);
  4480. ret = ci_upload_firmware(adev);
  4481. if (ret) {
  4482. DRM_ERROR("ci_upload_firmware failed\n");
  4483. return ret;
  4484. }
  4485. ret = ci_process_firmware_header(adev);
  4486. if (ret) {
  4487. DRM_ERROR("ci_process_firmware_header failed\n");
  4488. return ret;
  4489. }
  4490. ret = ci_initial_switch_from_arb_f0_to_f1(adev);
  4491. if (ret) {
  4492. DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
  4493. return ret;
  4494. }
  4495. ret = ci_init_smc_table(adev);
  4496. if (ret) {
  4497. DRM_ERROR("ci_init_smc_table failed\n");
  4498. return ret;
  4499. }
  4500. ret = ci_init_arb_table_index(adev);
  4501. if (ret) {
  4502. DRM_ERROR("ci_init_arb_table_index failed\n");
  4503. return ret;
  4504. }
  4505. if (pi->caps_dynamic_ac_timing) {
  4506. ret = ci_populate_initial_mc_reg_table(adev);
  4507. if (ret) {
  4508. DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
  4509. return ret;
  4510. }
  4511. }
  4512. ret = ci_populate_pm_base(adev);
  4513. if (ret) {
  4514. DRM_ERROR("ci_populate_pm_base failed\n");
  4515. return ret;
  4516. }
  4517. ci_dpm_start_smc(adev);
  4518. ci_enable_vr_hot_gpio_interrupt(adev);
  4519. ret = ci_notify_smc_display_change(adev, false);
  4520. if (ret) {
  4521. DRM_ERROR("ci_notify_smc_display_change failed\n");
  4522. return ret;
  4523. }
  4524. ci_enable_sclk_control(adev, true);
  4525. ret = ci_enable_ulv(adev, true);
  4526. if (ret) {
  4527. DRM_ERROR("ci_enable_ulv failed\n");
  4528. return ret;
  4529. }
  4530. ret = ci_enable_ds_master_switch(adev, true);
  4531. if (ret) {
  4532. DRM_ERROR("ci_enable_ds_master_switch failed\n");
  4533. return ret;
  4534. }
  4535. ret = ci_start_dpm(adev);
  4536. if (ret) {
  4537. DRM_ERROR("ci_start_dpm failed\n");
  4538. return ret;
  4539. }
  4540. ret = ci_enable_didt(adev, true);
  4541. if (ret) {
  4542. DRM_ERROR("ci_enable_didt failed\n");
  4543. return ret;
  4544. }
  4545. ret = ci_enable_smc_cac(adev, true);
  4546. if (ret) {
  4547. DRM_ERROR("ci_enable_smc_cac failed\n");
  4548. return ret;
  4549. }
  4550. ret = ci_enable_power_containment(adev, true);
  4551. if (ret) {
  4552. DRM_ERROR("ci_enable_power_containment failed\n");
  4553. return ret;
  4554. }
  4555. ret = ci_power_control_set_level(adev);
  4556. if (ret) {
  4557. DRM_ERROR("ci_power_control_set_level failed\n");
  4558. return ret;
  4559. }
  4560. ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
  4561. ret = ci_enable_thermal_based_sclk_dpm(adev, true);
  4562. if (ret) {
  4563. DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
  4564. return ret;
  4565. }
  4566. ci_thermal_start_thermal_controller(adev);
  4567. ci_update_current_ps(adev, boot_ps);
  4568. return 0;
  4569. }
  4570. static void ci_dpm_disable(struct amdgpu_device *adev)
  4571. {
  4572. struct ci_power_info *pi = ci_get_pi(adev);
  4573. struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
  4574. amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
  4575. AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
  4576. amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
  4577. AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
  4578. ci_dpm_powergate_uvd(adev, true);
  4579. if (!amdgpu_ci_is_smc_running(adev))
  4580. return;
  4581. ci_thermal_stop_thermal_controller(adev);
  4582. if (pi->thermal_protection)
  4583. ci_enable_thermal_protection(adev, false);
  4584. ci_enable_power_containment(adev, false);
  4585. ci_enable_smc_cac(adev, false);
  4586. ci_enable_didt(adev, false);
  4587. ci_enable_spread_spectrum(adev, false);
  4588. ci_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
  4589. ci_stop_dpm(adev);
  4590. ci_enable_ds_master_switch(adev, false);
  4591. ci_enable_ulv(adev, false);
  4592. ci_clear_vc(adev);
  4593. ci_reset_to_default(adev);
  4594. ci_dpm_stop_smc(adev);
  4595. ci_force_switch_to_arb_f0(adev);
  4596. ci_enable_thermal_based_sclk_dpm(adev, false);
  4597. ci_update_current_ps(adev, boot_ps);
  4598. }
  4599. static int ci_dpm_set_power_state(struct amdgpu_device *adev)
  4600. {
  4601. struct ci_power_info *pi = ci_get_pi(adev);
  4602. struct amdgpu_ps *new_ps = &pi->requested_rps;
  4603. struct amdgpu_ps *old_ps = &pi->current_rps;
  4604. int ret;
  4605. ci_find_dpm_states_clocks_in_dpm_table(adev, new_ps);
  4606. if (pi->pcie_performance_request)
  4607. ci_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
  4608. ret = ci_freeze_sclk_mclk_dpm(adev);
  4609. if (ret) {
  4610. DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
  4611. return ret;
  4612. }
  4613. ret = ci_populate_and_upload_sclk_mclk_dpm_levels(adev, new_ps);
  4614. if (ret) {
  4615. DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
  4616. return ret;
  4617. }
  4618. ret = ci_generate_dpm_level_enable_mask(adev, new_ps);
  4619. if (ret) {
  4620. DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
  4621. return ret;
  4622. }
  4623. ret = ci_update_vce_dpm(adev, new_ps, old_ps);
  4624. if (ret) {
  4625. DRM_ERROR("ci_update_vce_dpm failed\n");
  4626. return ret;
  4627. }
  4628. ret = ci_update_sclk_t(adev);
  4629. if (ret) {
  4630. DRM_ERROR("ci_update_sclk_t failed\n");
  4631. return ret;
  4632. }
  4633. if (pi->caps_dynamic_ac_timing) {
  4634. ret = ci_update_and_upload_mc_reg_table(adev);
  4635. if (ret) {
  4636. DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
  4637. return ret;
  4638. }
  4639. }
  4640. ret = ci_program_memory_timing_parameters(adev);
  4641. if (ret) {
  4642. DRM_ERROR("ci_program_memory_timing_parameters failed\n");
  4643. return ret;
  4644. }
  4645. ret = ci_unfreeze_sclk_mclk_dpm(adev);
  4646. if (ret) {
  4647. DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
  4648. return ret;
  4649. }
  4650. ret = ci_upload_dpm_level_enable_mask(adev);
  4651. if (ret) {
  4652. DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
  4653. return ret;
  4654. }
  4655. if (pi->pcie_performance_request)
  4656. ci_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
  4657. return 0;
  4658. }
  4659. #if 0
  4660. static void ci_dpm_reset_asic(struct amdgpu_device *adev)
  4661. {
  4662. ci_set_boot_state(adev);
  4663. }
  4664. #endif
  4665. static void ci_dpm_display_configuration_changed(struct amdgpu_device *adev)
  4666. {
  4667. ci_program_display_gap(adev);
  4668. }
  4669. union power_info {
  4670. struct _ATOM_POWERPLAY_INFO info;
  4671. struct _ATOM_POWERPLAY_INFO_V2 info_2;
  4672. struct _ATOM_POWERPLAY_INFO_V3 info_3;
  4673. struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  4674. struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  4675. struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  4676. };
  4677. union pplib_clock_info {
  4678. struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  4679. struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  4680. struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  4681. struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  4682. struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  4683. struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
  4684. };
  4685. union pplib_power_state {
  4686. struct _ATOM_PPLIB_STATE v1;
  4687. struct _ATOM_PPLIB_STATE_V2 v2;
  4688. };
  4689. static void ci_parse_pplib_non_clock_info(struct amdgpu_device *adev,
  4690. struct amdgpu_ps *rps,
  4691. struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
  4692. u8 table_rev)
  4693. {
  4694. rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
  4695. rps->class = le16_to_cpu(non_clock_info->usClassification);
  4696. rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
  4697. if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
  4698. rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
  4699. rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
  4700. } else {
  4701. rps->vclk = 0;
  4702. rps->dclk = 0;
  4703. }
  4704. if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
  4705. adev->pm.dpm.boot_ps = rps;
  4706. if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
  4707. adev->pm.dpm.uvd_ps = rps;
  4708. }
  4709. static void ci_parse_pplib_clock_info(struct amdgpu_device *adev,
  4710. struct amdgpu_ps *rps, int index,
  4711. union pplib_clock_info *clock_info)
  4712. {
  4713. struct ci_power_info *pi = ci_get_pi(adev);
  4714. struct ci_ps *ps = ci_get_ps(rps);
  4715. struct ci_pl *pl = &ps->performance_levels[index];
  4716. ps->performance_level_count = index + 1;
  4717. pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
  4718. pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
  4719. pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
  4720. pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
  4721. pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
  4722. pi->sys_pcie_mask,
  4723. pi->vbios_boot_state.pcie_gen_bootup_value,
  4724. clock_info->ci.ucPCIEGen);
  4725. pl->pcie_lane = amdgpu_get_pcie_lane_support(adev,
  4726. pi->vbios_boot_state.pcie_lane_bootup_value,
  4727. le16_to_cpu(clock_info->ci.usPCIELane));
  4728. if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
  4729. pi->acpi_pcie_gen = pl->pcie_gen;
  4730. }
  4731. if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
  4732. pi->ulv.supported = true;
  4733. pi->ulv.pl = *pl;
  4734. pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
  4735. }
  4736. /* patch up boot state */
  4737. if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
  4738. pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
  4739. pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
  4740. pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
  4741. pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
  4742. }
  4743. switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
  4744. case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
  4745. pi->use_pcie_powersaving_levels = true;
  4746. if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
  4747. pi->pcie_gen_powersaving.max = pl->pcie_gen;
  4748. if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
  4749. pi->pcie_gen_powersaving.min = pl->pcie_gen;
  4750. if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
  4751. pi->pcie_lane_powersaving.max = pl->pcie_lane;
  4752. if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
  4753. pi->pcie_lane_powersaving.min = pl->pcie_lane;
  4754. break;
  4755. case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
  4756. pi->use_pcie_performance_levels = true;
  4757. if (pi->pcie_gen_performance.max < pl->pcie_gen)
  4758. pi->pcie_gen_performance.max = pl->pcie_gen;
  4759. if (pi->pcie_gen_performance.min > pl->pcie_gen)
  4760. pi->pcie_gen_performance.min = pl->pcie_gen;
  4761. if (pi->pcie_lane_performance.max < pl->pcie_lane)
  4762. pi->pcie_lane_performance.max = pl->pcie_lane;
  4763. if (pi->pcie_lane_performance.min > pl->pcie_lane)
  4764. pi->pcie_lane_performance.min = pl->pcie_lane;
  4765. break;
  4766. default:
  4767. break;
  4768. }
  4769. }
  4770. static int ci_parse_power_table(struct amdgpu_device *adev)
  4771. {
  4772. struct amdgpu_mode_info *mode_info = &adev->mode_info;
  4773. struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
  4774. union pplib_power_state *power_state;
  4775. int i, j, k, non_clock_array_index, clock_array_index;
  4776. union pplib_clock_info *clock_info;
  4777. struct _StateArray *state_array;
  4778. struct _ClockInfoArray *clock_info_array;
  4779. struct _NonClockInfoArray *non_clock_info_array;
  4780. union power_info *power_info;
  4781. int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
  4782. u16 data_offset;
  4783. u8 frev, crev;
  4784. u8 *power_state_offset;
  4785. struct ci_ps *ps;
  4786. if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
  4787. &frev, &crev, &data_offset))
  4788. return -EINVAL;
  4789. power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
  4790. amdgpu_add_thermal_controller(adev);
  4791. state_array = (struct _StateArray *)
  4792. (mode_info->atom_context->bios + data_offset +
  4793. le16_to_cpu(power_info->pplib.usStateArrayOffset));
  4794. clock_info_array = (struct _ClockInfoArray *)
  4795. (mode_info->atom_context->bios + data_offset +
  4796. le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
  4797. non_clock_info_array = (struct _NonClockInfoArray *)
  4798. (mode_info->atom_context->bios + data_offset +
  4799. le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
  4800. adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
  4801. state_array->ucNumEntries, GFP_KERNEL);
  4802. if (!adev->pm.dpm.ps)
  4803. return -ENOMEM;
  4804. power_state_offset = (u8 *)state_array->states;
  4805. for (i = 0; i < state_array->ucNumEntries; i++) {
  4806. u8 *idx;
  4807. power_state = (union pplib_power_state *)power_state_offset;
  4808. non_clock_array_index = power_state->v2.nonClockInfoIndex;
  4809. non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
  4810. &non_clock_info_array->nonClockInfo[non_clock_array_index];
  4811. ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
  4812. if (ps == NULL) {
  4813. kfree(adev->pm.dpm.ps);
  4814. return -ENOMEM;
  4815. }
  4816. adev->pm.dpm.ps[i].ps_priv = ps;
  4817. ci_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
  4818. non_clock_info,
  4819. non_clock_info_array->ucEntrySize);
  4820. k = 0;
  4821. idx = (u8 *)&power_state->v2.clockInfoIndex[0];
  4822. for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
  4823. clock_array_index = idx[j];
  4824. if (clock_array_index >= clock_info_array->ucNumEntries)
  4825. continue;
  4826. if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
  4827. break;
  4828. clock_info = (union pplib_clock_info *)
  4829. ((u8 *)&clock_info_array->clockInfo[0] +
  4830. (clock_array_index * clock_info_array->ucEntrySize));
  4831. ci_parse_pplib_clock_info(adev,
  4832. &adev->pm.dpm.ps[i], k,
  4833. clock_info);
  4834. k++;
  4835. }
  4836. power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
  4837. }
  4838. adev->pm.dpm.num_ps = state_array->ucNumEntries;
  4839. /* fill in the vce power states */
  4840. for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
  4841. u32 sclk, mclk;
  4842. clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
  4843. clock_info = (union pplib_clock_info *)
  4844. &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
  4845. sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
  4846. sclk |= clock_info->ci.ucEngineClockHigh << 16;
  4847. mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
  4848. mclk |= clock_info->ci.ucMemoryClockHigh << 16;
  4849. adev->pm.dpm.vce_states[i].sclk = sclk;
  4850. adev->pm.dpm.vce_states[i].mclk = mclk;
  4851. }
  4852. return 0;
  4853. }
  4854. static int ci_get_vbios_boot_values(struct amdgpu_device *adev,
  4855. struct ci_vbios_boot_state *boot_state)
  4856. {
  4857. struct amdgpu_mode_info *mode_info = &adev->mode_info;
  4858. int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
  4859. ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
  4860. u8 frev, crev;
  4861. u16 data_offset;
  4862. if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
  4863. &frev, &crev, &data_offset)) {
  4864. firmware_info =
  4865. (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
  4866. data_offset);
  4867. boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
  4868. boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
  4869. boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
  4870. boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(adev);
  4871. boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(adev);
  4872. boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
  4873. boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
  4874. return 0;
  4875. }
  4876. return -EINVAL;
  4877. }
  4878. static void ci_dpm_fini(struct amdgpu_device *adev)
  4879. {
  4880. int i;
  4881. for (i = 0; i < adev->pm.dpm.num_ps; i++) {
  4882. kfree(adev->pm.dpm.ps[i].ps_priv);
  4883. }
  4884. kfree(adev->pm.dpm.ps);
  4885. kfree(adev->pm.dpm.priv);
  4886. kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
  4887. amdgpu_free_extended_power_table(adev);
  4888. }
  4889. /**
  4890. * ci_dpm_init_microcode - load ucode images from disk
  4891. *
  4892. * @adev: amdgpu_device pointer
  4893. *
  4894. * Use the firmware interface to load the ucode images into
  4895. * the driver (not loaded into hw).
  4896. * Returns 0 on success, error on failure.
  4897. */
  4898. static int ci_dpm_init_microcode(struct amdgpu_device *adev)
  4899. {
  4900. const char *chip_name;
  4901. char fw_name[30];
  4902. int err;
  4903. DRM_DEBUG("\n");
  4904. switch (adev->asic_type) {
  4905. case CHIP_BONAIRE:
  4906. if ((adev->pdev->revision == 0x80) ||
  4907. (adev->pdev->revision == 0x81) ||
  4908. (adev->pdev->device == 0x665f))
  4909. chip_name = "bonaire_k";
  4910. else
  4911. chip_name = "bonaire";
  4912. break;
  4913. case CHIP_HAWAII:
  4914. if (adev->pdev->revision == 0x80)
  4915. chip_name = "hawaii_k";
  4916. else
  4917. chip_name = "hawaii";
  4918. break;
  4919. case CHIP_KAVERI:
  4920. case CHIP_KABINI:
  4921. case CHIP_MULLINS:
  4922. default: BUG();
  4923. }
  4924. snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
  4925. err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
  4926. if (err)
  4927. goto out;
  4928. err = amdgpu_ucode_validate(adev->pm.fw);
  4929. out:
  4930. if (err) {
  4931. pr_err("cik_smc: Failed to load firmware \"%s\"\n", fw_name);
  4932. release_firmware(adev->pm.fw);
  4933. adev->pm.fw = NULL;
  4934. }
  4935. return err;
  4936. }
  4937. static int ci_dpm_init(struct amdgpu_device *adev)
  4938. {
  4939. int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
  4940. SMU7_Discrete_DpmTable *dpm_table;
  4941. struct amdgpu_gpio_rec gpio;
  4942. u16 data_offset, size;
  4943. u8 frev, crev;
  4944. struct ci_power_info *pi;
  4945. int ret;
  4946. pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
  4947. if (pi == NULL)
  4948. return -ENOMEM;
  4949. adev->pm.dpm.priv = pi;
  4950. pi->sys_pcie_mask =
  4951. (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
  4952. CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
  4953. pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
  4954. pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;
  4955. pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;
  4956. pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;
  4957. pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;
  4958. pi->pcie_lane_performance.max = 0;
  4959. pi->pcie_lane_performance.min = 16;
  4960. pi->pcie_lane_powersaving.max = 0;
  4961. pi->pcie_lane_powersaving.min = 16;
  4962. ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);
  4963. if (ret) {
  4964. ci_dpm_fini(adev);
  4965. return ret;
  4966. }
  4967. ret = amdgpu_get_platform_caps(adev);
  4968. if (ret) {
  4969. ci_dpm_fini(adev);
  4970. return ret;
  4971. }
  4972. ret = amdgpu_parse_extended_power_table(adev);
  4973. if (ret) {
  4974. ci_dpm_fini(adev);
  4975. return ret;
  4976. }
  4977. ret = ci_parse_power_table(adev);
  4978. if (ret) {
  4979. ci_dpm_fini(adev);
  4980. return ret;
  4981. }
  4982. pi->dll_default_on = false;
  4983. pi->sram_end = SMC_RAM_END;
  4984. pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
  4985. pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
  4986. pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
  4987. pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
  4988. pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
  4989. pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
  4990. pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
  4991. pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
  4992. pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
  4993. pi->sclk_dpm_key_disabled = 0;
  4994. pi->mclk_dpm_key_disabled = 0;
  4995. pi->pcie_dpm_key_disabled = 0;
  4996. pi->thermal_sclk_dpm_enabled = 0;
  4997. if (amdgpu_pp_feature_mask & SCLK_DEEP_SLEEP_MASK)
  4998. pi->caps_sclk_ds = true;
  4999. else
  5000. pi->caps_sclk_ds = false;
  5001. pi->mclk_strobe_mode_threshold = 40000;
  5002. pi->mclk_stutter_mode_threshold = 40000;
  5003. pi->mclk_edc_enable_threshold = 40000;
  5004. pi->mclk_edc_wr_enable_threshold = 40000;
  5005. ci_initialize_powertune_defaults(adev);
  5006. pi->caps_fps = false;
  5007. pi->caps_sclk_throttle_low_notification = false;
  5008. pi->caps_uvd_dpm = true;
  5009. pi->caps_vce_dpm = true;
  5010. ci_get_leakage_voltages(adev);
  5011. ci_patch_dependency_tables_with_leakage(adev);
  5012. ci_set_private_data_variables_based_on_pptable(adev);
  5013. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
  5014. kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
  5015. if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
  5016. ci_dpm_fini(adev);
  5017. return -ENOMEM;
  5018. }
  5019. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
  5020. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
  5021. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
  5022. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
  5023. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
  5024. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
  5025. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
  5026. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
  5027. adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
  5028. adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
  5029. adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
  5030. adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
  5031. adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
  5032. adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
  5033. adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
  5034. adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
  5035. if (adev->asic_type == CHIP_HAWAII) {
  5036. pi->thermal_temp_setting.temperature_low = 94500;
  5037. pi->thermal_temp_setting.temperature_high = 95000;
  5038. pi->thermal_temp_setting.temperature_shutdown = 104000;
  5039. } else {
  5040. pi->thermal_temp_setting.temperature_low = 99500;
  5041. pi->thermal_temp_setting.temperature_high = 100000;
  5042. pi->thermal_temp_setting.temperature_shutdown = 104000;
  5043. }
  5044. pi->uvd_enabled = false;
  5045. dpm_table = &pi->smc_state_table;
  5046. gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_VRHOT_GPIO_PINID);
  5047. if (gpio.valid) {
  5048. dpm_table->VRHotGpio = gpio.shift;
  5049. adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
  5050. } else {
  5051. dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
  5052. adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
  5053. }
  5054. gpio = amdgpu_atombios_lookup_gpio(adev, PP_AC_DC_SWITCH_GPIO_PINID);
  5055. if (gpio.valid) {
  5056. dpm_table->AcDcGpio = gpio.shift;
  5057. adev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
  5058. } else {
  5059. dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
  5060. adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
  5061. }
  5062. gpio = amdgpu_atombios_lookup_gpio(adev, VDDC_PCC_GPIO_PINID);
  5063. if (gpio.valid) {
  5064. u32 tmp = RREG32_SMC(ixCNB_PWRMGT_CNTL);
  5065. switch (gpio.shift) {
  5066. case 0:
  5067. tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
  5068. tmp |= 1 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
  5069. break;
  5070. case 1:
  5071. tmp &= ~CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK;
  5072. tmp |= 2 << CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT;
  5073. break;
  5074. case 2:
  5075. tmp |= CNB_PWRMGT_CNTL__GNB_SLOW_MASK;
  5076. break;
  5077. case 3:
  5078. tmp |= CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK;
  5079. break;
  5080. case 4:
  5081. tmp |= CNB_PWRMGT_CNTL__DPM_ENABLED_MASK;
  5082. break;
  5083. default:
  5084. DRM_INFO("Invalid PCC GPIO: %u!\n", gpio.shift);
  5085. break;
  5086. }
  5087. WREG32_SMC(ixCNB_PWRMGT_CNTL, tmp);
  5088. }
  5089. pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
  5090. pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
  5091. pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
  5092. if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
  5093. pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
  5094. else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
  5095. pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
  5096. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
  5097. if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
  5098. pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
  5099. else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
  5100. pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
  5101. else
  5102. adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
  5103. }
  5104. if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
  5105. if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
  5106. pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
  5107. else if (amdgpu_atombios_is_voltage_gpio(adev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
  5108. pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
  5109. else
  5110. adev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
  5111. }
  5112. pi->vddc_phase_shed_control = true;
  5113. #if defined(CONFIG_ACPI)
  5114. pi->pcie_performance_request =
  5115. amdgpu_acpi_is_pcie_performance_request_supported(adev);
  5116. #else
  5117. pi->pcie_performance_request = false;
  5118. #endif
  5119. if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,
  5120. &frev, &crev, &data_offset)) {
  5121. pi->caps_sclk_ss_support = true;
  5122. pi->caps_mclk_ss_support = true;
  5123. pi->dynamic_ss = true;
  5124. } else {
  5125. pi->caps_sclk_ss_support = false;
  5126. pi->caps_mclk_ss_support = false;
  5127. pi->dynamic_ss = true;
  5128. }
  5129. if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
  5130. pi->thermal_protection = true;
  5131. else
  5132. pi->thermal_protection = false;
  5133. pi->caps_dynamic_ac_timing = true;
  5134. pi->uvd_power_gated = true;
  5135. /* make sure dc limits are valid */
  5136. if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
  5137. (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
  5138. adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
  5139. adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
  5140. pi->fan_ctrl_is_in_default_mode = true;
  5141. return 0;
  5142. }
  5143. static void
  5144. ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
  5145. struct seq_file *m)
  5146. {
  5147. struct ci_power_info *pi = ci_get_pi(adev);
  5148. struct amdgpu_ps *rps = &pi->current_rps;
  5149. u32 sclk = ci_get_average_sclk_freq(adev);
  5150. u32 mclk = ci_get_average_mclk_freq(adev);
  5151. u32 activity_percent = 50;
  5152. int ret;
  5153. ret = ci_read_smc_soft_register(adev, offsetof(SMU7_SoftRegisters, AverageGraphicsA),
  5154. &activity_percent);
  5155. if (ret == 0) {
  5156. activity_percent += 0x80;
  5157. activity_percent >>= 8;
  5158. activity_percent = activity_percent > 100 ? 100 : activity_percent;
  5159. }
  5160. seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
  5161. seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
  5162. seq_printf(m, "power level avg sclk: %u mclk: %u\n",
  5163. sclk, mclk);
  5164. seq_printf(m, "GPU load: %u %%\n", activity_percent);
  5165. }
  5166. static void ci_dpm_print_power_state(struct amdgpu_device *adev,
  5167. struct amdgpu_ps *rps)
  5168. {
  5169. struct ci_ps *ps = ci_get_ps(rps);
  5170. struct ci_pl *pl;
  5171. int i;
  5172. amdgpu_dpm_print_class_info(rps->class, rps->class2);
  5173. amdgpu_dpm_print_cap_info(rps->caps);
  5174. printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
  5175. for (i = 0; i < ps->performance_level_count; i++) {
  5176. pl = &ps->performance_levels[i];
  5177. printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
  5178. i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
  5179. }
  5180. amdgpu_dpm_print_ps_status(adev, rps);
  5181. }
  5182. static inline bool ci_are_power_levels_equal(const struct ci_pl *ci_cpl1,
  5183. const struct ci_pl *ci_cpl2)
  5184. {
  5185. return ((ci_cpl1->mclk == ci_cpl2->mclk) &&
  5186. (ci_cpl1->sclk == ci_cpl2->sclk) &&
  5187. (ci_cpl1->pcie_gen == ci_cpl2->pcie_gen) &&
  5188. (ci_cpl1->pcie_lane == ci_cpl2->pcie_lane));
  5189. }
  5190. static int ci_check_state_equal(struct amdgpu_device *adev,
  5191. struct amdgpu_ps *cps,
  5192. struct amdgpu_ps *rps,
  5193. bool *equal)
  5194. {
  5195. struct ci_ps *ci_cps;
  5196. struct ci_ps *ci_rps;
  5197. int i;
  5198. if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
  5199. return -EINVAL;
  5200. ci_cps = ci_get_ps(cps);
  5201. ci_rps = ci_get_ps(rps);
  5202. if (ci_cps == NULL) {
  5203. *equal = false;
  5204. return 0;
  5205. }
  5206. if (ci_cps->performance_level_count != ci_rps->performance_level_count) {
  5207. *equal = false;
  5208. return 0;
  5209. }
  5210. for (i = 0; i < ci_cps->performance_level_count; i++) {
  5211. if (!ci_are_power_levels_equal(&(ci_cps->performance_levels[i]),
  5212. &(ci_rps->performance_levels[i]))) {
  5213. *equal = false;
  5214. return 0;
  5215. }
  5216. }
  5217. /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
  5218. *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
  5219. *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
  5220. return 0;
  5221. }
  5222. static u32 ci_dpm_get_sclk(struct amdgpu_device *adev, bool low)
  5223. {
  5224. struct ci_power_info *pi = ci_get_pi(adev);
  5225. struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
  5226. if (low)
  5227. return requested_state->performance_levels[0].sclk;
  5228. else
  5229. return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
  5230. }
  5231. static u32 ci_dpm_get_mclk(struct amdgpu_device *adev, bool low)
  5232. {
  5233. struct ci_power_info *pi = ci_get_pi(adev);
  5234. struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
  5235. if (low)
  5236. return requested_state->performance_levels[0].mclk;
  5237. else
  5238. return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
  5239. }
  5240. /* get temperature in millidegrees */
  5241. static int ci_dpm_get_temp(struct amdgpu_device *adev)
  5242. {
  5243. u32 temp;
  5244. int actual_temp = 0;
  5245. temp = (RREG32_SMC(ixCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
  5246. CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
  5247. if (temp & 0x200)
  5248. actual_temp = 255;
  5249. else
  5250. actual_temp = temp & 0x1ff;
  5251. actual_temp = actual_temp * 1000;
  5252. return actual_temp;
  5253. }
  5254. static int ci_set_temperature_range(struct amdgpu_device *adev)
  5255. {
  5256. int ret;
  5257. ret = ci_thermal_enable_alert(adev, false);
  5258. if (ret)
  5259. return ret;
  5260. ret = ci_thermal_set_temperature_range(adev, CISLANDS_TEMP_RANGE_MIN,
  5261. CISLANDS_TEMP_RANGE_MAX);
  5262. if (ret)
  5263. return ret;
  5264. ret = ci_thermal_enable_alert(adev, true);
  5265. if (ret)
  5266. return ret;
  5267. return ret;
  5268. }
  5269. static int ci_dpm_early_init(void *handle)
  5270. {
  5271. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5272. ci_dpm_set_dpm_funcs(adev);
  5273. ci_dpm_set_irq_funcs(adev);
  5274. return 0;
  5275. }
  5276. static int ci_dpm_late_init(void *handle)
  5277. {
  5278. int ret;
  5279. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5280. if (!amdgpu_dpm)
  5281. return 0;
  5282. /* init the sysfs and debugfs files late */
  5283. ret = amdgpu_pm_sysfs_init(adev);
  5284. if (ret)
  5285. return ret;
  5286. ret = ci_set_temperature_range(adev);
  5287. if (ret)
  5288. return ret;
  5289. return 0;
  5290. }
  5291. static int ci_dpm_sw_init(void *handle)
  5292. {
  5293. int ret;
  5294. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5295. ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230,
  5296. &adev->pm.dpm.thermal.irq);
  5297. if (ret)
  5298. return ret;
  5299. ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231,
  5300. &adev->pm.dpm.thermal.irq);
  5301. if (ret)
  5302. return ret;
  5303. /* default to balanced state */
  5304. adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
  5305. adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
  5306. adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
  5307. adev->pm.default_sclk = adev->clock.default_sclk;
  5308. adev->pm.default_mclk = adev->clock.default_mclk;
  5309. adev->pm.current_sclk = adev->clock.default_sclk;
  5310. adev->pm.current_mclk = adev->clock.default_mclk;
  5311. adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
  5312. ret = ci_dpm_init_microcode(adev);
  5313. if (ret)
  5314. return ret;
  5315. if (amdgpu_dpm == 0)
  5316. return 0;
  5317. INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
  5318. mutex_lock(&adev->pm.mutex);
  5319. ret = ci_dpm_init(adev);
  5320. if (ret)
  5321. goto dpm_failed;
  5322. adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
  5323. if (amdgpu_dpm == 1)
  5324. amdgpu_pm_print_power_states(adev);
  5325. mutex_unlock(&adev->pm.mutex);
  5326. DRM_INFO("amdgpu: dpm initialized\n");
  5327. return 0;
  5328. dpm_failed:
  5329. ci_dpm_fini(adev);
  5330. mutex_unlock(&adev->pm.mutex);
  5331. DRM_ERROR("amdgpu: dpm initialization failed\n");
  5332. return ret;
  5333. }
  5334. static int ci_dpm_sw_fini(void *handle)
  5335. {
  5336. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5337. flush_work(&adev->pm.dpm.thermal.work);
  5338. mutex_lock(&adev->pm.mutex);
  5339. amdgpu_pm_sysfs_fini(adev);
  5340. ci_dpm_fini(adev);
  5341. mutex_unlock(&adev->pm.mutex);
  5342. release_firmware(adev->pm.fw);
  5343. adev->pm.fw = NULL;
  5344. return 0;
  5345. }
  5346. static int ci_dpm_hw_init(void *handle)
  5347. {
  5348. int ret;
  5349. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5350. if (!amdgpu_dpm) {
  5351. ret = ci_upload_firmware(adev);
  5352. if (ret) {
  5353. DRM_ERROR("ci_upload_firmware failed\n");
  5354. return ret;
  5355. }
  5356. ci_dpm_start_smc(adev);
  5357. return 0;
  5358. }
  5359. mutex_lock(&adev->pm.mutex);
  5360. ci_dpm_setup_asic(adev);
  5361. ret = ci_dpm_enable(adev);
  5362. if (ret)
  5363. adev->pm.dpm_enabled = false;
  5364. else
  5365. adev->pm.dpm_enabled = true;
  5366. mutex_unlock(&adev->pm.mutex);
  5367. return ret;
  5368. }
  5369. static int ci_dpm_hw_fini(void *handle)
  5370. {
  5371. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5372. if (adev->pm.dpm_enabled) {
  5373. mutex_lock(&adev->pm.mutex);
  5374. ci_dpm_disable(adev);
  5375. mutex_unlock(&adev->pm.mutex);
  5376. } else {
  5377. ci_dpm_stop_smc(adev);
  5378. }
  5379. return 0;
  5380. }
  5381. static int ci_dpm_suspend(void *handle)
  5382. {
  5383. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5384. if (adev->pm.dpm_enabled) {
  5385. mutex_lock(&adev->pm.mutex);
  5386. amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
  5387. AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
  5388. amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
  5389. AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
  5390. adev->pm.dpm.last_user_state = adev->pm.dpm.user_state;
  5391. adev->pm.dpm.last_state = adev->pm.dpm.state;
  5392. adev->pm.dpm.user_state = POWER_STATE_TYPE_INTERNAL_BOOT;
  5393. adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_BOOT;
  5394. mutex_unlock(&adev->pm.mutex);
  5395. amdgpu_pm_compute_clocks(adev);
  5396. }
  5397. return 0;
  5398. }
  5399. static int ci_dpm_resume(void *handle)
  5400. {
  5401. int ret;
  5402. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  5403. if (adev->pm.dpm_enabled) {
  5404. /* asic init will reset to the boot state */
  5405. mutex_lock(&adev->pm.mutex);
  5406. ci_dpm_setup_asic(adev);
  5407. ret = ci_dpm_enable(adev);
  5408. if (ret)
  5409. adev->pm.dpm_enabled = false;
  5410. else
  5411. adev->pm.dpm_enabled = true;
  5412. adev->pm.dpm.user_state = adev->pm.dpm.last_user_state;
  5413. adev->pm.dpm.state = adev->pm.dpm.last_state;
  5414. mutex_unlock(&adev->pm.mutex);
  5415. if (adev->pm.dpm_enabled)
  5416. amdgpu_pm_compute_clocks(adev);
  5417. }
  5418. return 0;
  5419. }
  5420. static bool ci_dpm_is_idle(void *handle)
  5421. {
  5422. /* XXX */
  5423. return true;
  5424. }
  5425. static int ci_dpm_wait_for_idle(void *handle)
  5426. {
  5427. /* XXX */
  5428. return 0;
  5429. }
  5430. static int ci_dpm_soft_reset(void *handle)
  5431. {
  5432. return 0;
  5433. }
  5434. static int ci_dpm_set_interrupt_state(struct amdgpu_device *adev,
  5435. struct amdgpu_irq_src *source,
  5436. unsigned type,
  5437. enum amdgpu_interrupt_state state)
  5438. {
  5439. u32 cg_thermal_int;
  5440. switch (type) {
  5441. case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
  5442. switch (state) {
  5443. case AMDGPU_IRQ_STATE_DISABLE:
  5444. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
  5445. cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
  5446. WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
  5447. break;
  5448. case AMDGPU_IRQ_STATE_ENABLE:
  5449. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
  5450. cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
  5451. WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
  5452. break;
  5453. default:
  5454. break;
  5455. }
  5456. break;
  5457. case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
  5458. switch (state) {
  5459. case AMDGPU_IRQ_STATE_DISABLE:
  5460. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
  5461. cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
  5462. WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
  5463. break;
  5464. case AMDGPU_IRQ_STATE_ENABLE:
  5465. cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT);
  5466. cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
  5467. WREG32_SMC(ixCG_THERMAL_INT, cg_thermal_int);
  5468. break;
  5469. default:
  5470. break;
  5471. }
  5472. break;
  5473. default:
  5474. break;
  5475. }
  5476. return 0;
  5477. }
  5478. static int ci_dpm_process_interrupt(struct amdgpu_device *adev,
  5479. struct amdgpu_irq_src *source,
  5480. struct amdgpu_iv_entry *entry)
  5481. {
  5482. bool queue_thermal = false;
  5483. if (entry == NULL)
  5484. return -EINVAL;
  5485. switch (entry->src_id) {
  5486. case 230: /* thermal low to high */
  5487. DRM_DEBUG("IH: thermal low to high\n");
  5488. adev->pm.dpm.thermal.high_to_low = false;
  5489. queue_thermal = true;
  5490. break;
  5491. case 231: /* thermal high to low */
  5492. DRM_DEBUG("IH: thermal high to low\n");
  5493. adev->pm.dpm.thermal.high_to_low = true;
  5494. queue_thermal = true;
  5495. break;
  5496. default:
  5497. break;
  5498. }
  5499. if (queue_thermal)
  5500. schedule_work(&adev->pm.dpm.thermal.work);
  5501. return 0;
  5502. }
  5503. static int ci_dpm_set_clockgating_state(void *handle,
  5504. enum amd_clockgating_state state)
  5505. {
  5506. return 0;
  5507. }
  5508. static int ci_dpm_set_powergating_state(void *handle,
  5509. enum amd_powergating_state state)
  5510. {
  5511. return 0;
  5512. }
  5513. static int ci_dpm_print_clock_levels(struct amdgpu_device *adev,
  5514. enum pp_clock_type type, char *buf)
  5515. {
  5516. struct ci_power_info *pi = ci_get_pi(adev);
  5517. struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
  5518. struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
  5519. struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
  5520. int i, now, size = 0;
  5521. uint32_t clock, pcie_speed;
  5522. switch (type) {
  5523. case PP_SCLK:
  5524. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetSclkFrequency);
  5525. clock = RREG32(mmSMC_MSG_ARG_0);
  5526. for (i = 0; i < sclk_table->count; i++) {
  5527. if (clock > sclk_table->dpm_levels[i].value)
  5528. continue;
  5529. break;
  5530. }
  5531. now = i;
  5532. for (i = 0; i < sclk_table->count; i++)
  5533. size += sprintf(buf + size, "%d: %uMhz %s\n",
  5534. i, sclk_table->dpm_levels[i].value / 100,
  5535. (i == now) ? "*" : "");
  5536. break;
  5537. case PP_MCLK:
  5538. amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_API_GetMclkFrequency);
  5539. clock = RREG32(mmSMC_MSG_ARG_0);
  5540. for (i = 0; i < mclk_table->count; i++) {
  5541. if (clock > mclk_table->dpm_levels[i].value)
  5542. continue;
  5543. break;
  5544. }
  5545. now = i;
  5546. for (i = 0; i < mclk_table->count; i++)
  5547. size += sprintf(buf + size, "%d: %uMhz %s\n",
  5548. i, mclk_table->dpm_levels[i].value / 100,
  5549. (i == now) ? "*" : "");
  5550. break;
  5551. case PP_PCIE:
  5552. pcie_speed = ci_get_current_pcie_speed(adev);
  5553. for (i = 0; i < pcie_table->count; i++) {
  5554. if (pcie_speed != pcie_table->dpm_levels[i].value)
  5555. continue;
  5556. break;
  5557. }
  5558. now = i;
  5559. for (i = 0; i < pcie_table->count; i++)
  5560. size += sprintf(buf + size, "%d: %s %s\n", i,
  5561. (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
  5562. (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
  5563. (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
  5564. (i == now) ? "*" : "");
  5565. break;
  5566. default:
  5567. break;
  5568. }
  5569. return size;
  5570. }
  5571. static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
  5572. enum pp_clock_type type, uint32_t mask)
  5573. {
  5574. struct ci_power_info *pi = ci_get_pi(adev);
  5575. if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
  5576. AMD_DPM_FORCED_LEVEL_LOW |
  5577. AMD_DPM_FORCED_LEVEL_HIGH))
  5578. return -EINVAL;
  5579. switch (type) {
  5580. case PP_SCLK:
  5581. if (!pi->sclk_dpm_key_disabled)
  5582. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  5583. PPSMC_MSG_SCLKDPM_SetEnabledMask,
  5584. pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
  5585. break;
  5586. case PP_MCLK:
  5587. if (!pi->mclk_dpm_key_disabled)
  5588. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  5589. PPSMC_MSG_MCLKDPM_SetEnabledMask,
  5590. pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
  5591. break;
  5592. case PP_PCIE:
  5593. {
  5594. uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
  5595. uint32_t level = 0;
  5596. while (tmp >>= 1)
  5597. level++;
  5598. if (!pi->pcie_dpm_key_disabled)
  5599. amdgpu_ci_send_msg_to_smc_with_parameter(adev,
  5600. PPSMC_MSG_PCIeDPM_ForceLevel,
  5601. level);
  5602. break;
  5603. }
  5604. default:
  5605. break;
  5606. }
  5607. return 0;
  5608. }
  5609. static int ci_dpm_get_sclk_od(struct amdgpu_device *adev)
  5610. {
  5611. struct ci_power_info *pi = ci_get_pi(adev);
  5612. struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);
  5613. struct ci_single_dpm_table *golden_sclk_table =
  5614. &(pi->golden_dpm_table.sclk_table);
  5615. int value;
  5616. value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
  5617. golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
  5618. 100 /
  5619. golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
  5620. return value;
  5621. }
  5622. static int ci_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value)
  5623. {
  5624. struct ci_power_info *pi = ci_get_pi(adev);
  5625. struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
  5626. struct ci_single_dpm_table *golden_sclk_table =
  5627. &(pi->golden_dpm_table.sclk_table);
  5628. if (value > 20)
  5629. value = 20;
  5630. ps->performance_levels[ps->performance_level_count - 1].sclk =
  5631. golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value *
  5632. value / 100 +
  5633. golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
  5634. return 0;
  5635. }
  5636. static int ci_dpm_get_mclk_od(struct amdgpu_device *adev)
  5637. {
  5638. struct ci_power_info *pi = ci_get_pi(adev);
  5639. struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);
  5640. struct ci_single_dpm_table *golden_mclk_table =
  5641. &(pi->golden_dpm_table.mclk_table);
  5642. int value;
  5643. value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
  5644. golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
  5645. 100 /
  5646. golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
  5647. return value;
  5648. }
  5649. static int ci_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value)
  5650. {
  5651. struct ci_power_info *pi = ci_get_pi(adev);
  5652. struct ci_ps *ps = ci_get_ps(adev->pm.dpm.requested_ps);
  5653. struct ci_single_dpm_table *golden_mclk_table =
  5654. &(pi->golden_dpm_table.mclk_table);
  5655. if (value > 20)
  5656. value = 20;
  5657. ps->performance_levels[ps->performance_level_count - 1].mclk =
  5658. golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value *
  5659. value / 100 +
  5660. golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
  5661. return 0;
  5662. }
  5663. static int ci_dpm_get_power_profile_state(struct amdgpu_device *adev,
  5664. struct amd_pp_profile *query)
  5665. {
  5666. struct ci_power_info *pi = ci_get_pi(adev);
  5667. if (!pi || !query)
  5668. return -EINVAL;
  5669. if (query->type == AMD_PP_GFX_PROFILE)
  5670. memcpy(query, &pi->gfx_power_profile,
  5671. sizeof(struct amd_pp_profile));
  5672. else if (query->type == AMD_PP_COMPUTE_PROFILE)
  5673. memcpy(query, &pi->compute_power_profile,
  5674. sizeof(struct amd_pp_profile));
  5675. else
  5676. return -EINVAL;
  5677. return 0;
  5678. }
  5679. static int ci_populate_requested_graphic_levels(struct amdgpu_device *adev,
  5680. struct amd_pp_profile *request)
  5681. {
  5682. struct ci_power_info *pi = ci_get_pi(adev);
  5683. struct ci_dpm_table *dpm_table = &(pi->dpm_table);
  5684. struct SMU7_Discrete_GraphicsLevel *levels =
  5685. pi->smc_state_table.GraphicsLevel;
  5686. uint32_t array = pi->dpm_table_start +
  5687. offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
  5688. uint32_t array_size = sizeof(struct SMU7_Discrete_GraphicsLevel) *
  5689. SMU7_MAX_LEVELS_GRAPHICS;
  5690. uint32_t i;
  5691. for (i = 0; i < dpm_table->sclk_table.count; i++) {
  5692. levels[i].ActivityLevel =
  5693. cpu_to_be16(request->activity_threshold);
  5694. levels[i].EnabledForActivity = 1;
  5695. levels[i].UpH = request->up_hyst;
  5696. levels[i].DownH = request->down_hyst;
  5697. }
  5698. return amdgpu_ci_copy_bytes_to_smc(adev, array, (uint8_t *)levels,
  5699. array_size, pi->sram_end);
  5700. }
  5701. static void ci_find_min_clock_masks(struct amdgpu_device *adev,
  5702. uint32_t *sclk_mask, uint32_t *mclk_mask,
  5703. uint32_t min_sclk, uint32_t min_mclk)
  5704. {
  5705. struct ci_power_info *pi = ci_get_pi(adev);
  5706. struct ci_dpm_table *dpm_table = &(pi->dpm_table);
  5707. uint32_t i;
  5708. for (i = 0; i < dpm_table->sclk_table.count; i++) {
  5709. if (dpm_table->sclk_table.dpm_levels[i].enabled &&
  5710. dpm_table->sclk_table.dpm_levels[i].value >= min_sclk)
  5711. *sclk_mask |= 1 << i;
  5712. }
  5713. for (i = 0; i < dpm_table->mclk_table.count; i++) {
  5714. if (dpm_table->mclk_table.dpm_levels[i].enabled &&
  5715. dpm_table->mclk_table.dpm_levels[i].value >= min_mclk)
  5716. *mclk_mask |= 1 << i;
  5717. }
  5718. }
  5719. static int ci_set_power_profile_state(struct amdgpu_device *adev,
  5720. struct amd_pp_profile *request)
  5721. {
  5722. struct ci_power_info *pi = ci_get_pi(adev);
  5723. int tmp_result, result = 0;
  5724. uint32_t sclk_mask = 0, mclk_mask = 0;
  5725. tmp_result = ci_freeze_sclk_mclk_dpm(adev);
  5726. if (tmp_result) {
  5727. DRM_ERROR("Failed to freeze SCLK MCLK DPM!");
  5728. result = tmp_result;
  5729. }
  5730. tmp_result = ci_populate_requested_graphic_levels(adev,
  5731. request);
  5732. if (tmp_result) {
  5733. DRM_ERROR("Failed to populate requested graphic levels!");
  5734. result = tmp_result;
  5735. }
  5736. tmp_result = ci_unfreeze_sclk_mclk_dpm(adev);
  5737. if (tmp_result) {
  5738. DRM_ERROR("Failed to unfreeze SCLK MCLK DPM!");
  5739. result = tmp_result;
  5740. }
  5741. ci_find_min_clock_masks(adev, &sclk_mask, &mclk_mask,
  5742. request->min_sclk, request->min_mclk);
  5743. if (sclk_mask) {
  5744. if (!pi->sclk_dpm_key_disabled)
  5745. amdgpu_ci_send_msg_to_smc_with_parameter(
  5746. adev,
  5747. PPSMC_MSG_SCLKDPM_SetEnabledMask,
  5748. pi->dpm_level_enable_mask.
  5749. sclk_dpm_enable_mask &
  5750. sclk_mask);
  5751. }
  5752. if (mclk_mask) {
  5753. if (!pi->mclk_dpm_key_disabled)
  5754. amdgpu_ci_send_msg_to_smc_with_parameter(
  5755. adev,
  5756. PPSMC_MSG_MCLKDPM_SetEnabledMask,
  5757. pi->dpm_level_enable_mask.
  5758. mclk_dpm_enable_mask &
  5759. mclk_mask);
  5760. }
  5761. return result;
  5762. }
  5763. static int ci_dpm_set_power_profile_state(struct amdgpu_device *adev,
  5764. struct amd_pp_profile *request)
  5765. {
  5766. struct ci_power_info *pi = ci_get_pi(adev);
  5767. int ret = -1;
  5768. if (!pi || !request)
  5769. return -EINVAL;
  5770. if (adev->pm.dpm.forced_level !=
  5771. AMD_DPM_FORCED_LEVEL_AUTO)
  5772. return -EINVAL;
  5773. if (request->min_sclk ||
  5774. request->min_mclk ||
  5775. request->activity_threshold ||
  5776. request->up_hyst ||
  5777. request->down_hyst) {
  5778. if (request->type == AMD_PP_GFX_PROFILE)
  5779. memcpy(&pi->gfx_power_profile, request,
  5780. sizeof(struct amd_pp_profile));
  5781. else if (request->type == AMD_PP_COMPUTE_PROFILE)
  5782. memcpy(&pi->compute_power_profile, request,
  5783. sizeof(struct amd_pp_profile));
  5784. else
  5785. return -EINVAL;
  5786. if (request->type == pi->current_power_profile)
  5787. ret = ci_set_power_profile_state(
  5788. adev,
  5789. request);
  5790. } else {
  5791. /* set power profile if it exists */
  5792. switch (request->type) {
  5793. case AMD_PP_GFX_PROFILE:
  5794. ret = ci_set_power_profile_state(
  5795. adev,
  5796. &pi->gfx_power_profile);
  5797. break;
  5798. case AMD_PP_COMPUTE_PROFILE:
  5799. ret = ci_set_power_profile_state(
  5800. adev,
  5801. &pi->compute_power_profile);
  5802. break;
  5803. default:
  5804. return -EINVAL;
  5805. }
  5806. }
  5807. if (!ret)
  5808. pi->current_power_profile = request->type;
  5809. return 0;
  5810. }
  5811. static int ci_dpm_reset_power_profile_state(struct amdgpu_device *adev,
  5812. struct amd_pp_profile *request)
  5813. {
  5814. struct ci_power_info *pi = ci_get_pi(adev);
  5815. if (!pi || !request)
  5816. return -EINVAL;
  5817. if (request->type == AMD_PP_GFX_PROFILE) {
  5818. pi->gfx_power_profile = pi->default_gfx_power_profile;
  5819. return ci_dpm_set_power_profile_state(adev,
  5820. &pi->gfx_power_profile);
  5821. } else if (request->type == AMD_PP_COMPUTE_PROFILE) {
  5822. pi->compute_power_profile =
  5823. pi->default_compute_power_profile;
  5824. return ci_dpm_set_power_profile_state(adev,
  5825. &pi->compute_power_profile);
  5826. } else
  5827. return -EINVAL;
  5828. }
  5829. static int ci_dpm_switch_power_profile(struct amdgpu_device *adev,
  5830. enum amd_pp_profile_type type)
  5831. {
  5832. struct ci_power_info *pi = ci_get_pi(adev);
  5833. struct amd_pp_profile request = {0};
  5834. if (!pi)
  5835. return -EINVAL;
  5836. if (pi->current_power_profile != type) {
  5837. request.type = type;
  5838. return ci_dpm_set_power_profile_state(adev, &request);
  5839. }
  5840. return 0;
  5841. }
  5842. static int ci_dpm_read_sensor(struct amdgpu_device *adev, int idx,
  5843. void *value, int *size)
  5844. {
  5845. u32 activity_percent = 50;
  5846. int ret;
  5847. /* size must be at least 4 bytes for all sensors */
  5848. if (*size < 4)
  5849. return -EINVAL;
  5850. switch (idx) {
  5851. case AMDGPU_PP_SENSOR_GFX_SCLK:
  5852. *((uint32_t *)value) = ci_get_average_sclk_freq(adev);
  5853. *size = 4;
  5854. return 0;
  5855. case AMDGPU_PP_SENSOR_GFX_MCLK:
  5856. *((uint32_t *)value) = ci_get_average_mclk_freq(adev);
  5857. *size = 4;
  5858. return 0;
  5859. case AMDGPU_PP_SENSOR_GPU_TEMP:
  5860. *((uint32_t *)value) = ci_dpm_get_temp(adev);
  5861. *size = 4;
  5862. return 0;
  5863. case AMDGPU_PP_SENSOR_GPU_LOAD:
  5864. ret = ci_read_smc_soft_register(adev,
  5865. offsetof(SMU7_SoftRegisters,
  5866. AverageGraphicsA),
  5867. &activity_percent);
  5868. if (ret == 0) {
  5869. activity_percent += 0x80;
  5870. activity_percent >>= 8;
  5871. activity_percent =
  5872. activity_percent > 100 ? 100 : activity_percent;
  5873. }
  5874. *((uint32_t *)value) = activity_percent;
  5875. *size = 4;
  5876. return 0;
  5877. default:
  5878. return -EINVAL;
  5879. }
  5880. }
  5881. const struct amd_ip_funcs ci_dpm_ip_funcs = {
  5882. .name = "ci_dpm",
  5883. .early_init = ci_dpm_early_init,
  5884. .late_init = ci_dpm_late_init,
  5885. .sw_init = ci_dpm_sw_init,
  5886. .sw_fini = ci_dpm_sw_fini,
  5887. .hw_init = ci_dpm_hw_init,
  5888. .hw_fini = ci_dpm_hw_fini,
  5889. .suspend = ci_dpm_suspend,
  5890. .resume = ci_dpm_resume,
  5891. .is_idle = ci_dpm_is_idle,
  5892. .wait_for_idle = ci_dpm_wait_for_idle,
  5893. .soft_reset = ci_dpm_soft_reset,
  5894. .set_clockgating_state = ci_dpm_set_clockgating_state,
  5895. .set_powergating_state = ci_dpm_set_powergating_state,
  5896. };
  5897. static const struct amdgpu_dpm_funcs ci_dpm_funcs = {
  5898. .get_temperature = &ci_dpm_get_temp,
  5899. .pre_set_power_state = &ci_dpm_pre_set_power_state,
  5900. .set_power_state = &ci_dpm_set_power_state,
  5901. .post_set_power_state = &ci_dpm_post_set_power_state,
  5902. .display_configuration_changed = &ci_dpm_display_configuration_changed,
  5903. .get_sclk = &ci_dpm_get_sclk,
  5904. .get_mclk = &ci_dpm_get_mclk,
  5905. .print_power_state = &ci_dpm_print_power_state,
  5906. .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
  5907. .force_performance_level = &ci_dpm_force_performance_level,
  5908. .vblank_too_short = &ci_dpm_vblank_too_short,
  5909. .powergate_uvd = &ci_dpm_powergate_uvd,
  5910. .set_fan_control_mode = &ci_dpm_set_fan_control_mode,
  5911. .get_fan_control_mode = &ci_dpm_get_fan_control_mode,
  5912. .set_fan_speed_percent = &ci_dpm_set_fan_speed_percent,
  5913. .get_fan_speed_percent = &ci_dpm_get_fan_speed_percent,
  5914. .print_clock_levels = ci_dpm_print_clock_levels,
  5915. .force_clock_level = ci_dpm_force_clock_level,
  5916. .get_sclk_od = ci_dpm_get_sclk_od,
  5917. .set_sclk_od = ci_dpm_set_sclk_od,
  5918. .get_mclk_od = ci_dpm_get_mclk_od,
  5919. .set_mclk_od = ci_dpm_set_mclk_od,
  5920. .check_state_equal = ci_check_state_equal,
  5921. .get_vce_clock_state = amdgpu_get_vce_clock_state,
  5922. .get_power_profile_state = ci_dpm_get_power_profile_state,
  5923. .set_power_profile_state = ci_dpm_set_power_profile_state,
  5924. .reset_power_profile_state = ci_dpm_reset_power_profile_state,
  5925. .switch_power_profile = ci_dpm_switch_power_profile,
  5926. .read_sensor = ci_dpm_read_sensor,
  5927. };
  5928. static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
  5929. {
  5930. if (adev->pm.funcs == NULL)
  5931. adev->pm.funcs = &ci_dpm_funcs;
  5932. }
  5933. static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
  5934. .set = ci_dpm_set_interrupt_state,
  5935. .process = ci_dpm_process_interrupt,
  5936. };
  5937. static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev)
  5938. {
  5939. adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
  5940. adev->pm.dpm.thermal.irq.funcs = &ci_dpm_irq_funcs;
  5941. }