bytcr_rt5640.c 24 KB

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  1. /*
  2. * byt_cr_dpcm_rt5640.c - ASoc Machine driver for Intel Byt CR platform
  3. *
  4. * Copyright (C) 2014 Intel Corp
  5. * Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
  6. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  18. */
  19. #include <linux/init.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/acpi.h>
  23. #include <linux/device.h>
  24. #include <linux/dmi.h>
  25. #include <linux/slab.h>
  26. #include <asm/cpu_device_id.h>
  27. #include <asm/platform_sst_audio.h>
  28. #include <linux/clk.h>
  29. #include <sound/pcm.h>
  30. #include <sound/pcm_params.h>
  31. #include <sound/soc.h>
  32. #include <sound/jack.h>
  33. #include "../../codecs/rt5640.h"
  34. #include "../atom/sst-atom-controls.h"
  35. #include "../common/sst-acpi.h"
  36. #include "../common/sst-dsp.h"
  37. enum {
  38. BYT_RT5640_DMIC1_MAP,
  39. BYT_RT5640_DMIC2_MAP,
  40. BYT_RT5640_IN1_MAP,
  41. BYT_RT5640_IN3_MAP,
  42. };
  43. #define BYT_RT5640_MAP(quirk) ((quirk) & 0xff)
  44. #define BYT_RT5640_DMIC_EN BIT(16)
  45. #define BYT_RT5640_MONO_SPEAKER BIT(17)
  46. #define BYT_RT5640_DIFF_MIC BIT(18) /* defaut is single-ended */
  47. #define BYT_RT5640_SSP2_AIF2 BIT(19) /* default is using AIF1 */
  48. #define BYT_RT5640_SSP0_AIF1 BIT(20)
  49. #define BYT_RT5640_SSP0_AIF2 BIT(21)
  50. #define BYT_RT5640_MCLK_EN BIT(22)
  51. #define BYT_RT5640_MCLK_25MHZ BIT(23)
  52. struct byt_rt5640_private {
  53. struct clk *mclk;
  54. };
  55. static unsigned long byt_rt5640_quirk = BYT_RT5640_MCLK_EN;
  56. static void log_quirks(struct device *dev)
  57. {
  58. if (BYT_RT5640_MAP(byt_rt5640_quirk) == BYT_RT5640_DMIC1_MAP)
  59. dev_info(dev, "quirk DMIC1_MAP enabled");
  60. if (BYT_RT5640_MAP(byt_rt5640_quirk) == BYT_RT5640_DMIC2_MAP)
  61. dev_info(dev, "quirk DMIC2_MAP enabled");
  62. if (BYT_RT5640_MAP(byt_rt5640_quirk) == BYT_RT5640_IN1_MAP)
  63. dev_info(dev, "quirk IN1_MAP enabled");
  64. if (BYT_RT5640_MAP(byt_rt5640_quirk) == BYT_RT5640_IN3_MAP)
  65. dev_info(dev, "quirk IN3_MAP enabled");
  66. if (byt_rt5640_quirk & BYT_RT5640_DMIC_EN)
  67. dev_info(dev, "quirk DMIC enabled");
  68. if (byt_rt5640_quirk & BYT_RT5640_MONO_SPEAKER)
  69. dev_info(dev, "quirk MONO_SPEAKER enabled");
  70. if (byt_rt5640_quirk & BYT_RT5640_DIFF_MIC)
  71. dev_info(dev, "quirk DIFF_MIC enabled");
  72. if (byt_rt5640_quirk & BYT_RT5640_SSP2_AIF2)
  73. dev_info(dev, "quirk SSP2_AIF2 enabled");
  74. if (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1)
  75. dev_info(dev, "quirk SSP0_AIF1 enabled");
  76. if (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)
  77. dev_info(dev, "quirk SSP0_AIF2 enabled");
  78. if (byt_rt5640_quirk & BYT_RT5640_MCLK_EN)
  79. dev_info(dev, "quirk MCLK_EN enabled");
  80. if (byt_rt5640_quirk & BYT_RT5640_MCLK_25MHZ)
  81. dev_info(dev, "quirk MCLK_25MHZ enabled");
  82. }
  83. #define BYT_CODEC_DAI1 "rt5640-aif1"
  84. #define BYT_CODEC_DAI2 "rt5640-aif2"
  85. static inline struct snd_soc_dai *byt_get_codec_dai(struct snd_soc_card *card)
  86. {
  87. struct snd_soc_pcm_runtime *rtd;
  88. list_for_each_entry(rtd, &card->rtd_list, list) {
  89. if (!strncmp(rtd->codec_dai->name, BYT_CODEC_DAI1,
  90. strlen(BYT_CODEC_DAI1)))
  91. return rtd->codec_dai;
  92. if (!strncmp(rtd->codec_dai->name, BYT_CODEC_DAI2,
  93. strlen(BYT_CODEC_DAI2)))
  94. return rtd->codec_dai;
  95. }
  96. return NULL;
  97. }
  98. static int platform_clock_control(struct snd_soc_dapm_widget *w,
  99. struct snd_kcontrol *k, int event)
  100. {
  101. struct snd_soc_dapm_context *dapm = w->dapm;
  102. struct snd_soc_card *card = dapm->card;
  103. struct snd_soc_dai *codec_dai;
  104. struct byt_rt5640_private *priv = snd_soc_card_get_drvdata(card);
  105. int ret;
  106. codec_dai = byt_get_codec_dai(card);
  107. if (!codec_dai) {
  108. dev_err(card->dev,
  109. "Codec dai not found; Unable to set platform clock\n");
  110. return -EIO;
  111. }
  112. if (SND_SOC_DAPM_EVENT_ON(event)) {
  113. if ((byt_rt5640_quirk & BYT_RT5640_MCLK_EN) && priv->mclk) {
  114. ret = clk_prepare_enable(priv->mclk);
  115. if (ret < 0) {
  116. dev_err(card->dev,
  117. "could not configure MCLK state");
  118. return ret;
  119. }
  120. }
  121. ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,
  122. 48000 * 512,
  123. SND_SOC_CLOCK_IN);
  124. } else {
  125. /*
  126. * Set codec clock source to internal clock before
  127. * turning off the platform clock. Codec needs clock
  128. * for Jack detection and button press
  129. */
  130. ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_RCCLK,
  131. 48000 * 512,
  132. SND_SOC_CLOCK_IN);
  133. if (!ret) {
  134. if ((byt_rt5640_quirk & BYT_RT5640_MCLK_EN) && priv->mclk)
  135. clk_disable_unprepare(priv->mclk);
  136. }
  137. }
  138. if (ret < 0) {
  139. dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
  140. return ret;
  141. }
  142. return 0;
  143. }
  144. static const struct snd_soc_dapm_widget byt_rt5640_widgets[] = {
  145. SND_SOC_DAPM_HP("Headphone", NULL),
  146. SND_SOC_DAPM_MIC("Headset Mic", NULL),
  147. SND_SOC_DAPM_MIC("Internal Mic", NULL),
  148. SND_SOC_DAPM_SPK("Speaker", NULL),
  149. SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
  150. platform_clock_control, SND_SOC_DAPM_PRE_PMU |
  151. SND_SOC_DAPM_POST_PMD),
  152. };
  153. static const struct snd_soc_dapm_route byt_rt5640_audio_map[] = {
  154. {"Headphone", NULL, "Platform Clock"},
  155. {"Headset Mic", NULL, "Platform Clock"},
  156. {"Internal Mic", NULL, "Platform Clock"},
  157. {"Speaker", NULL, "Platform Clock"},
  158. {"Headset Mic", NULL, "MICBIAS1"},
  159. {"IN2P", NULL, "Headset Mic"},
  160. {"Headphone", NULL, "HPOL"},
  161. {"Headphone", NULL, "HPOR"},
  162. };
  163. static const struct snd_soc_dapm_route byt_rt5640_intmic_dmic1_map[] = {
  164. {"DMIC1", NULL, "Internal Mic"},
  165. };
  166. static const struct snd_soc_dapm_route byt_rt5640_intmic_dmic2_map[] = {
  167. {"DMIC2", NULL, "Internal Mic"},
  168. };
  169. static const struct snd_soc_dapm_route byt_rt5640_intmic_in1_map[] = {
  170. {"Internal Mic", NULL, "MICBIAS1"},
  171. {"IN1P", NULL, "Internal Mic"},
  172. };
  173. static const struct snd_soc_dapm_route byt_rt5640_intmic_in3_map[] = {
  174. {"Internal Mic", NULL, "MICBIAS1"},
  175. {"IN3P", NULL, "Internal Mic"},
  176. };
  177. static const struct snd_soc_dapm_route byt_rt5640_ssp2_aif1_map[] = {
  178. {"ssp2 Tx", NULL, "codec_out0"},
  179. {"ssp2 Tx", NULL, "codec_out1"},
  180. {"codec_in0", NULL, "ssp2 Rx"},
  181. {"codec_in1", NULL, "ssp2 Rx"},
  182. {"AIF1 Playback", NULL, "ssp2 Tx"},
  183. {"ssp2 Rx", NULL, "AIF1 Capture"},
  184. };
  185. static const struct snd_soc_dapm_route byt_rt5640_ssp2_aif2_map[] = {
  186. {"ssp2 Tx", NULL, "codec_out0"},
  187. {"ssp2 Tx", NULL, "codec_out1"},
  188. {"codec_in0", NULL, "ssp2 Rx"},
  189. {"codec_in1", NULL, "ssp2 Rx"},
  190. {"AIF2 Playback", NULL, "ssp2 Tx"},
  191. {"ssp2 Rx", NULL, "AIF2 Capture"},
  192. };
  193. static const struct snd_soc_dapm_route byt_rt5640_ssp0_aif1_map[] = {
  194. {"ssp0 Tx", NULL, "modem_out"},
  195. {"modem_in", NULL, "ssp0 Rx"},
  196. {"AIF1 Playback", NULL, "ssp0 Tx"},
  197. {"ssp0 Rx", NULL, "AIF1 Capture"},
  198. };
  199. static const struct snd_soc_dapm_route byt_rt5640_ssp0_aif2_map[] = {
  200. {"ssp0 Tx", NULL, "modem_out"},
  201. {"modem_in", NULL, "ssp0 Rx"},
  202. {"AIF2 Playback", NULL, "ssp0 Tx"},
  203. {"ssp0 Rx", NULL, "AIF2 Capture"},
  204. };
  205. static const struct snd_soc_dapm_route byt_rt5640_stereo_spk_map[] = {
  206. {"Speaker", NULL, "SPOLP"},
  207. {"Speaker", NULL, "SPOLN"},
  208. {"Speaker", NULL, "SPORP"},
  209. {"Speaker", NULL, "SPORN"},
  210. };
  211. static const struct snd_soc_dapm_route byt_rt5640_mono_spk_map[] = {
  212. {"Speaker", NULL, "SPOLP"},
  213. {"Speaker", NULL, "SPOLN"},
  214. };
  215. static const struct snd_kcontrol_new byt_rt5640_controls[] = {
  216. SOC_DAPM_PIN_SWITCH("Headphone"),
  217. SOC_DAPM_PIN_SWITCH("Headset Mic"),
  218. SOC_DAPM_PIN_SWITCH("Internal Mic"),
  219. SOC_DAPM_PIN_SWITCH("Speaker"),
  220. };
  221. static int byt_rt5640_aif1_hw_params(struct snd_pcm_substream *substream,
  222. struct snd_pcm_hw_params *params)
  223. {
  224. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  225. struct snd_soc_dai *codec_dai = rtd->codec_dai;
  226. int ret;
  227. ret = snd_soc_dai_set_sysclk(codec_dai, RT5640_SCLK_S_PLL1,
  228. params_rate(params) * 512,
  229. SND_SOC_CLOCK_IN);
  230. if (ret < 0) {
  231. dev_err(rtd->dev, "can't set codec clock %d\n", ret);
  232. return ret;
  233. }
  234. if (!(byt_rt5640_quirk & BYT_RT5640_MCLK_EN)) {
  235. /* use bitclock as PLL input */
  236. if ((byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) ||
  237. (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) {
  238. /* 2x16 bit slots on SSP0 */
  239. ret = snd_soc_dai_set_pll(codec_dai, 0,
  240. RT5640_PLL1_S_BCLK1,
  241. params_rate(params) * 32,
  242. params_rate(params) * 512);
  243. } else {
  244. /* 2x15 bit slots on SSP2 */
  245. ret = snd_soc_dai_set_pll(codec_dai, 0,
  246. RT5640_PLL1_S_BCLK1,
  247. params_rate(params) * 50,
  248. params_rate(params) * 512);
  249. }
  250. } else {
  251. if (byt_rt5640_quirk & BYT_RT5640_MCLK_25MHZ) {
  252. ret = snd_soc_dai_set_pll(codec_dai, 0,
  253. RT5640_PLL1_S_MCLK,
  254. 25000000,
  255. params_rate(params) * 512);
  256. } else {
  257. ret = snd_soc_dai_set_pll(codec_dai, 0,
  258. RT5640_PLL1_S_MCLK,
  259. 19200000,
  260. params_rate(params) * 512);
  261. }
  262. }
  263. if (ret < 0) {
  264. dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
  265. return ret;
  266. }
  267. return 0;
  268. }
  269. static int byt_rt5640_quirk_cb(const struct dmi_system_id *id)
  270. {
  271. byt_rt5640_quirk = (unsigned long)id->driver_data;
  272. return 1;
  273. }
  274. static const struct dmi_system_id byt_rt5640_quirk_table[] = {
  275. {
  276. .callback = byt_rt5640_quirk_cb,
  277. .matches = {
  278. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
  279. DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "T100TA"),
  280. },
  281. .driver_data = (unsigned long *)(BYT_RT5640_IN1_MAP |
  282. BYT_RT5640_MCLK_EN),
  283. },
  284. {
  285. .callback = byt_rt5640_quirk_cb,
  286. .matches = {
  287. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
  288. DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "T100TAF"),
  289. },
  290. .driver_data = (unsigned long *)(BYT_RT5640_IN1_MAP |
  291. BYT_RT5640_MONO_SPEAKER |
  292. BYT_RT5640_DIFF_MIC |
  293. BYT_RT5640_SSP0_AIF2 |
  294. BYT_RT5640_MCLK_EN
  295. ),
  296. },
  297. {
  298. .callback = byt_rt5640_quirk_cb,
  299. .matches = {
  300. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "DellInc."),
  301. DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Venue 8 Pro 5830"),
  302. },
  303. .driver_data = (unsigned long *)(BYT_RT5640_DMIC2_MAP |
  304. BYT_RT5640_DMIC_EN |
  305. BYT_RT5640_MCLK_EN),
  306. },
  307. {
  308. .callback = byt_rt5640_quirk_cb,
  309. .matches = {
  310. DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
  311. DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "HP ElitePad 1000 G2"),
  312. },
  313. .driver_data = (unsigned long *)(BYT_RT5640_IN1_MAP |
  314. BYT_RT5640_MCLK_EN),
  315. },
  316. {
  317. .callback = byt_rt5640_quirk_cb,
  318. .matches = {
  319. DMI_MATCH(DMI_SYS_VENDOR, "Circuitco"),
  320. DMI_MATCH(DMI_PRODUCT_NAME, "Minnowboard Max B3 PLATFORM"),
  321. },
  322. .driver_data = (unsigned long *)(BYT_RT5640_DMIC1_MAP |
  323. BYT_RT5640_DMIC_EN),
  324. },
  325. {
  326. .callback = byt_rt5640_quirk_cb,
  327. .matches = {
  328. DMI_MATCH(DMI_BOARD_VENDOR, "TECLAST"),
  329. DMI_MATCH(DMI_BOARD_NAME, "tPAD"),
  330. },
  331. .driver_data = (unsigned long *)(BYT_RT5640_IN3_MAP |
  332. BYT_RT5640_MCLK_EN |
  333. BYT_RT5640_SSP0_AIF1),
  334. },
  335. {
  336. .callback = byt_rt5640_quirk_cb,
  337. .matches = {
  338. DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
  339. DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
  340. },
  341. .driver_data = (unsigned long *)(BYT_RT5640_IN1_MAP |
  342. BYT_RT5640_MCLK_EN |
  343. BYT_RT5640_SSP0_AIF1),
  344. },
  345. {}
  346. };
  347. static int byt_rt5640_init(struct snd_soc_pcm_runtime *runtime)
  348. {
  349. int ret;
  350. struct snd_soc_codec *codec = runtime->codec;
  351. struct snd_soc_card *card = runtime->card;
  352. const struct snd_soc_dapm_route *custom_map;
  353. struct byt_rt5640_private *priv = snd_soc_card_get_drvdata(card);
  354. int num_routes;
  355. card->dapm.idle_bias_off = true;
  356. rt5640_sel_asrc_clk_src(codec,
  357. RT5640_DA_STEREO_FILTER |
  358. RT5640_DA_MONO_L_FILTER |
  359. RT5640_DA_MONO_R_FILTER |
  360. RT5640_AD_STEREO_FILTER |
  361. RT5640_AD_MONO_L_FILTER |
  362. RT5640_AD_MONO_R_FILTER,
  363. RT5640_CLK_SEL_ASRC);
  364. ret = snd_soc_add_card_controls(card, byt_rt5640_controls,
  365. ARRAY_SIZE(byt_rt5640_controls));
  366. if (ret) {
  367. dev_err(card->dev, "unable to add card controls\n");
  368. return ret;
  369. }
  370. switch (BYT_RT5640_MAP(byt_rt5640_quirk)) {
  371. case BYT_RT5640_IN1_MAP:
  372. custom_map = byt_rt5640_intmic_in1_map;
  373. num_routes = ARRAY_SIZE(byt_rt5640_intmic_in1_map);
  374. break;
  375. case BYT_RT5640_IN3_MAP:
  376. custom_map = byt_rt5640_intmic_in3_map;
  377. num_routes = ARRAY_SIZE(byt_rt5640_intmic_in3_map);
  378. break;
  379. case BYT_RT5640_DMIC2_MAP:
  380. custom_map = byt_rt5640_intmic_dmic2_map;
  381. num_routes = ARRAY_SIZE(byt_rt5640_intmic_dmic2_map);
  382. break;
  383. default:
  384. custom_map = byt_rt5640_intmic_dmic1_map;
  385. num_routes = ARRAY_SIZE(byt_rt5640_intmic_dmic1_map);
  386. }
  387. ret = snd_soc_dapm_add_routes(&card->dapm, custom_map, num_routes);
  388. if (ret)
  389. return ret;
  390. if (byt_rt5640_quirk & BYT_RT5640_SSP2_AIF2) {
  391. ret = snd_soc_dapm_add_routes(&card->dapm,
  392. byt_rt5640_ssp2_aif2_map,
  393. ARRAY_SIZE(byt_rt5640_ssp2_aif2_map));
  394. } else if (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) {
  395. ret = snd_soc_dapm_add_routes(&card->dapm,
  396. byt_rt5640_ssp0_aif1_map,
  397. ARRAY_SIZE(byt_rt5640_ssp0_aif1_map));
  398. } else if (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2) {
  399. ret = snd_soc_dapm_add_routes(&card->dapm,
  400. byt_rt5640_ssp0_aif2_map,
  401. ARRAY_SIZE(byt_rt5640_ssp0_aif2_map));
  402. } else {
  403. ret = snd_soc_dapm_add_routes(&card->dapm,
  404. byt_rt5640_ssp2_aif1_map,
  405. ARRAY_SIZE(byt_rt5640_ssp2_aif1_map));
  406. }
  407. if (ret)
  408. return ret;
  409. if (byt_rt5640_quirk & BYT_RT5640_MONO_SPEAKER) {
  410. ret = snd_soc_dapm_add_routes(&card->dapm,
  411. byt_rt5640_mono_spk_map,
  412. ARRAY_SIZE(byt_rt5640_mono_spk_map));
  413. } else {
  414. ret = snd_soc_dapm_add_routes(&card->dapm,
  415. byt_rt5640_stereo_spk_map,
  416. ARRAY_SIZE(byt_rt5640_stereo_spk_map));
  417. }
  418. if (ret)
  419. return ret;
  420. if (byt_rt5640_quirk & BYT_RT5640_DIFF_MIC) {
  421. snd_soc_update_bits(codec, RT5640_IN1_IN2, RT5640_IN_DF1,
  422. RT5640_IN_DF1);
  423. }
  424. if (byt_rt5640_quirk & BYT_RT5640_DMIC_EN) {
  425. ret = rt5640_dmic_enable(codec, 0, 0);
  426. if (ret)
  427. return ret;
  428. }
  429. snd_soc_dapm_ignore_suspend(&card->dapm, "Headphone");
  430. snd_soc_dapm_ignore_suspend(&card->dapm, "Speaker");
  431. if ((byt_rt5640_quirk & BYT_RT5640_MCLK_EN) && priv->mclk) {
  432. /*
  433. * The firmware might enable the clock at
  434. * boot (this information may or may not
  435. * be reflected in the enable clock register).
  436. * To change the rate we must disable the clock
  437. * first to cover these cases. Due to common
  438. * clock framework restrictions that do not allow
  439. * to disable a clock that has not been enabled,
  440. * we need to enable the clock first.
  441. */
  442. ret = clk_prepare_enable(priv->mclk);
  443. if (!ret)
  444. clk_disable_unprepare(priv->mclk);
  445. if (byt_rt5640_quirk & BYT_RT5640_MCLK_25MHZ)
  446. ret = clk_set_rate(priv->mclk, 25000000);
  447. else
  448. ret = clk_set_rate(priv->mclk, 19200000);
  449. if (ret)
  450. dev_err(card->dev, "unable to set MCLK rate\n");
  451. }
  452. return ret;
  453. }
  454. static const struct snd_soc_pcm_stream byt_rt5640_dai_params = {
  455. .formats = SNDRV_PCM_FMTBIT_S24_LE,
  456. .rate_min = 48000,
  457. .rate_max = 48000,
  458. .channels_min = 2,
  459. .channels_max = 2,
  460. };
  461. static int byt_rt5640_codec_fixup(struct snd_soc_pcm_runtime *rtd,
  462. struct snd_pcm_hw_params *params)
  463. {
  464. struct snd_interval *rate = hw_param_interval(params,
  465. SNDRV_PCM_HW_PARAM_RATE);
  466. struct snd_interval *channels = hw_param_interval(params,
  467. SNDRV_PCM_HW_PARAM_CHANNELS);
  468. int ret;
  469. /* The DSP will covert the FE rate to 48k, stereo */
  470. rate->min = rate->max = 48000;
  471. channels->min = channels->max = 2;
  472. if ((byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) ||
  473. (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) {
  474. /* set SSP0 to 16-bit */
  475. params_set_format(params, SNDRV_PCM_FORMAT_S16_LE);
  476. /*
  477. * Default mode for SSP configuration is TDM 4 slot, override config
  478. * with explicit setting to I2S 2ch 16-bit. The word length is set with
  479. * dai_set_tdm_slot() since there is no other API exposed
  480. */
  481. ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
  482. SND_SOC_DAIFMT_I2S |
  483. SND_SOC_DAIFMT_NB_IF |
  484. SND_SOC_DAIFMT_CBS_CFS
  485. );
  486. if (ret < 0) {
  487. dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
  488. return ret;
  489. }
  490. ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x3, 0x3, 2, 16);
  491. if (ret < 0) {
  492. dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
  493. return ret;
  494. }
  495. } else {
  496. /* set SSP2 to 24-bit */
  497. params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
  498. /*
  499. * Default mode for SSP configuration is TDM 4 slot, override config
  500. * with explicit setting to I2S 2ch 24-bit. The word length is set with
  501. * dai_set_tdm_slot() since there is no other API exposed
  502. */
  503. ret = snd_soc_dai_set_fmt(rtd->cpu_dai,
  504. SND_SOC_DAIFMT_I2S |
  505. SND_SOC_DAIFMT_NB_IF |
  506. SND_SOC_DAIFMT_CBS_CFS
  507. );
  508. if (ret < 0) {
  509. dev_err(rtd->dev, "can't set format to I2S, err %d\n", ret);
  510. return ret;
  511. }
  512. ret = snd_soc_dai_set_tdm_slot(rtd->cpu_dai, 0x3, 0x3, 2, 24);
  513. if (ret < 0) {
  514. dev_err(rtd->dev, "can't set I2S config, err %d\n", ret);
  515. return ret;
  516. }
  517. }
  518. return 0;
  519. }
  520. static int byt_rt5640_aif1_startup(struct snd_pcm_substream *substream)
  521. {
  522. return snd_pcm_hw_constraint_single(substream->runtime,
  523. SNDRV_PCM_HW_PARAM_RATE, 48000);
  524. }
  525. static const struct snd_soc_ops byt_rt5640_aif1_ops = {
  526. .startup = byt_rt5640_aif1_startup,
  527. };
  528. static const struct snd_soc_ops byt_rt5640_be_ssp2_ops = {
  529. .hw_params = byt_rt5640_aif1_hw_params,
  530. };
  531. static struct snd_soc_dai_link byt_rt5640_dais[] = {
  532. [MERR_DPCM_AUDIO] = {
  533. .name = "Baytrail Audio Port",
  534. .stream_name = "Baytrail Audio",
  535. .cpu_dai_name = "media-cpu-dai",
  536. .codec_dai_name = "snd-soc-dummy-dai",
  537. .codec_name = "snd-soc-dummy",
  538. .platform_name = "sst-mfld-platform",
  539. .ignore_suspend = 1,
  540. .dynamic = 1,
  541. .dpcm_playback = 1,
  542. .dpcm_capture = 1,
  543. .ops = &byt_rt5640_aif1_ops,
  544. },
  545. [MERR_DPCM_DEEP_BUFFER] = {
  546. .name = "Deep-Buffer Audio Port",
  547. .stream_name = "Deep-Buffer Audio",
  548. .cpu_dai_name = "deepbuffer-cpu-dai",
  549. .codec_dai_name = "snd-soc-dummy-dai",
  550. .codec_name = "snd-soc-dummy",
  551. .platform_name = "sst-mfld-platform",
  552. .ignore_suspend = 1,
  553. .nonatomic = true,
  554. .dynamic = 1,
  555. .dpcm_playback = 1,
  556. .ops = &byt_rt5640_aif1_ops,
  557. },
  558. [MERR_DPCM_COMPR] = {
  559. .name = "Baytrail Compressed Port",
  560. .stream_name = "Baytrail Compress",
  561. .cpu_dai_name = "compress-cpu-dai",
  562. .codec_dai_name = "snd-soc-dummy-dai",
  563. .codec_name = "snd-soc-dummy",
  564. .platform_name = "sst-mfld-platform",
  565. },
  566. /* back ends */
  567. {
  568. .name = "SSP2-Codec",
  569. .id = 1,
  570. .cpu_dai_name = "ssp2-port", /* overwritten for ssp0 routing */
  571. .platform_name = "sst-mfld-platform",
  572. .no_pcm = 1,
  573. .codec_dai_name = "rt5640-aif1", /* changed w/ quirk */
  574. .codec_name = "i2c-10EC5640:00", /* overwritten with HID */
  575. .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF
  576. | SND_SOC_DAIFMT_CBS_CFS,
  577. .be_hw_params_fixup = byt_rt5640_codec_fixup,
  578. .ignore_suspend = 1,
  579. .dpcm_playback = 1,
  580. .dpcm_capture = 1,
  581. .init = byt_rt5640_init,
  582. .ops = &byt_rt5640_be_ssp2_ops,
  583. },
  584. };
  585. /* SoC card */
  586. static struct snd_soc_card byt_rt5640_card = {
  587. .name = "bytcr-rt5640",
  588. .owner = THIS_MODULE,
  589. .dai_link = byt_rt5640_dais,
  590. .num_links = ARRAY_SIZE(byt_rt5640_dais),
  591. .dapm_widgets = byt_rt5640_widgets,
  592. .num_dapm_widgets = ARRAY_SIZE(byt_rt5640_widgets),
  593. .dapm_routes = byt_rt5640_audio_map,
  594. .num_dapm_routes = ARRAY_SIZE(byt_rt5640_audio_map),
  595. .fully_routed = true,
  596. };
  597. static char byt_rt5640_codec_name[16]; /* i2c-<HID>:00 with HID being 8 chars */
  598. static char byt_rt5640_codec_aif_name[12]; /* = "rt5640-aif[1|2]" */
  599. static char byt_rt5640_cpu_dai_name[10]; /* = "ssp[0|2]-port" */
  600. static bool is_valleyview(void)
  601. {
  602. static const struct x86_cpu_id cpu_ids[] = {
  603. { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
  604. {}
  605. };
  606. if (!x86_match_cpu(cpu_ids))
  607. return false;
  608. return true;
  609. }
  610. struct acpi_chan_package { /* ACPICA seems to require 64 bit integers */
  611. u64 aif_value; /* 1: AIF1, 2: AIF2 */
  612. u64 mclock_value; /* usually 25MHz (0x17d7940), ignored */
  613. };
  614. static int snd_byt_rt5640_mc_probe(struct platform_device *pdev)
  615. {
  616. int ret_val = 0;
  617. struct sst_acpi_mach *mach;
  618. const char *i2c_name = NULL;
  619. int i;
  620. int dai_index;
  621. struct byt_rt5640_private *priv;
  622. bool is_bytcr = false;
  623. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_ATOMIC);
  624. if (!priv)
  625. return -ENOMEM;
  626. /* register the soc card */
  627. byt_rt5640_card.dev = &pdev->dev;
  628. mach = byt_rt5640_card.dev->platform_data;
  629. snd_soc_card_set_drvdata(&byt_rt5640_card, priv);
  630. /* fix index of codec dai */
  631. dai_index = MERR_DPCM_COMPR + 1;
  632. for (i = 0; i < ARRAY_SIZE(byt_rt5640_dais); i++) {
  633. if (!strcmp(byt_rt5640_dais[i].codec_name, "i2c-10EC5640:00")) {
  634. dai_index = i;
  635. break;
  636. }
  637. }
  638. /* fixup codec name based on HID */
  639. i2c_name = sst_acpi_find_name_from_hid(mach->id);
  640. if (i2c_name != NULL) {
  641. snprintf(byt_rt5640_codec_name, sizeof(byt_rt5640_codec_name),
  642. "%s%s", "i2c-", i2c_name);
  643. byt_rt5640_dais[dai_index].codec_name = byt_rt5640_codec_name;
  644. }
  645. /*
  646. * swap SSP0 if bytcr is detected
  647. * (will be overridden if DMI quirk is detected)
  648. */
  649. if (is_valleyview()) {
  650. struct sst_platform_info *p_info = mach->pdata;
  651. const struct sst_res_info *res_info = p_info->res_info;
  652. if (res_info->acpi_ipc_irq_index == 0)
  653. is_bytcr = true;
  654. }
  655. if (is_bytcr) {
  656. /*
  657. * Baytrail CR platforms may have CHAN package in BIOS, try
  658. * to find relevant routing quirk based as done on Windows
  659. * platforms. We have to read the information directly from the
  660. * BIOS, at this stage the card is not created and the links
  661. * with the codec driver/pdata are non-existent
  662. */
  663. struct acpi_chan_package chan_package;
  664. /* format specified: 2 64-bit integers */
  665. struct acpi_buffer format = {sizeof("NN"), "NN"};
  666. struct acpi_buffer state = {0, NULL};
  667. struct sst_acpi_package_context pkg_ctx;
  668. bool pkg_found = false;
  669. state.length = sizeof(chan_package);
  670. state.pointer = &chan_package;
  671. pkg_ctx.name = "CHAN";
  672. pkg_ctx.length = 2;
  673. pkg_ctx.format = &format;
  674. pkg_ctx.state = &state;
  675. pkg_ctx.data_valid = false;
  676. pkg_found = sst_acpi_find_package_from_hid(mach->id, &pkg_ctx);
  677. if (pkg_found) {
  678. if (chan_package.aif_value == 1) {
  679. dev_info(&pdev->dev, "BIOS Routing: AIF1 connected\n");
  680. byt_rt5640_quirk |= BYT_RT5640_SSP0_AIF1;
  681. } else if (chan_package.aif_value == 2) {
  682. dev_info(&pdev->dev, "BIOS Routing: AIF2 connected\n");
  683. byt_rt5640_quirk |= BYT_RT5640_SSP0_AIF2;
  684. } else {
  685. dev_info(&pdev->dev, "BIOS Routing isn't valid, ignored\n");
  686. pkg_found = false;
  687. }
  688. }
  689. if (!pkg_found) {
  690. /* no BIOS indications, assume SSP0-AIF2 connection */
  691. byt_rt5640_quirk |= BYT_RT5640_SSP0_AIF2;
  692. }
  693. /* change defaults for Baytrail-CR capture */
  694. byt_rt5640_quirk |= BYT_RT5640_IN1_MAP;
  695. byt_rt5640_quirk |= BYT_RT5640_DIFF_MIC;
  696. } else {
  697. byt_rt5640_quirk |= (BYT_RT5640_DMIC1_MAP |
  698. BYT_RT5640_DMIC_EN);
  699. }
  700. /* check quirks before creating card */
  701. dmi_check_system(byt_rt5640_quirk_table);
  702. log_quirks(&pdev->dev);
  703. if ((byt_rt5640_quirk & BYT_RT5640_SSP2_AIF2) ||
  704. (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) {
  705. /* fixup codec aif name */
  706. snprintf(byt_rt5640_codec_aif_name,
  707. sizeof(byt_rt5640_codec_aif_name),
  708. "%s", "rt5640-aif2");
  709. byt_rt5640_dais[dai_index].codec_dai_name =
  710. byt_rt5640_codec_aif_name;
  711. }
  712. if ((byt_rt5640_quirk & BYT_RT5640_SSP0_AIF1) ||
  713. (byt_rt5640_quirk & BYT_RT5640_SSP0_AIF2)) {
  714. /* fixup cpu dai name name */
  715. snprintf(byt_rt5640_cpu_dai_name,
  716. sizeof(byt_rt5640_cpu_dai_name),
  717. "%s", "ssp0-port");
  718. byt_rt5640_dais[dai_index].cpu_dai_name =
  719. byt_rt5640_cpu_dai_name;
  720. }
  721. if ((byt_rt5640_quirk & BYT_RT5640_MCLK_EN) && (is_valleyview())) {
  722. priv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
  723. if (IS_ERR(priv->mclk)) {
  724. ret_val = PTR_ERR(priv->mclk);
  725. dev_err(&pdev->dev,
  726. "Failed to get MCLK from pmc_plt_clk_3: %d\n",
  727. ret_val);
  728. /*
  729. * Fall back to bit clock usage for -ENOENT (clock not
  730. * available likely due to missing dependencies), bail
  731. * for all other errors, including -EPROBE_DEFER
  732. */
  733. if (ret_val != -ENOENT)
  734. return ret_val;
  735. byt_rt5640_quirk &= ~BYT_RT5640_MCLK_EN;
  736. }
  737. }
  738. ret_val = devm_snd_soc_register_card(&pdev->dev, &byt_rt5640_card);
  739. if (ret_val) {
  740. dev_err(&pdev->dev, "devm_snd_soc_register_card failed %d\n",
  741. ret_val);
  742. return ret_val;
  743. }
  744. platform_set_drvdata(pdev, &byt_rt5640_card);
  745. return ret_val;
  746. }
  747. static struct platform_driver snd_byt_rt5640_mc_driver = {
  748. .driver = {
  749. .name = "bytcr_rt5640",
  750. .pm = &snd_soc_pm_ops,
  751. },
  752. .probe = snd_byt_rt5640_mc_probe,
  753. };
  754. module_platform_driver(snd_byt_rt5640_mc_driver);
  755. MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");
  756. MODULE_AUTHOR("Subhransu S. Prusty <subhransu.s.prusty@intel.com>");
  757. MODULE_LICENSE("GPL v2");
  758. MODULE_ALIAS("platform:bytcr_rt5640");