sst.c 15 KB

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  1. /*
  2. * sst.c - Intel SST Driver for audio engine
  3. *
  4. * Copyright (C) 2008-14 Intel Corp
  5. * Authors: Vinod Koul <vinod.koul@intel.com>
  6. * Harsha Priya <priya.harsha@intel.com>
  7. * Dharageswari R <dharageswari.r@intel.com>
  8. * KP Jeeja <jeeja.kp@intel.com>
  9. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; version 2 of the License.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  21. */
  22. #include <linux/module.h>
  23. #include <linux/fs.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/firmware.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/pm_qos.h>
  28. #include <linux/async.h>
  29. #include <linux/acpi.h>
  30. #include <linux/sysfs.h>
  31. #include <sound/core.h>
  32. #include <sound/soc.h>
  33. #include <asm/platform_sst_audio.h>
  34. #include "../sst-mfld-platform.h"
  35. #include "sst.h"
  36. #include "../../common/sst-dsp.h"
  37. MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
  38. MODULE_AUTHOR("Harsha Priya <priya.harsha@intel.com>");
  39. MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine Driver");
  40. MODULE_LICENSE("GPL v2");
  41. static inline bool sst_is_process_reply(u32 msg_id)
  42. {
  43. return ((msg_id & PROCESS_MSG) ? true : false);
  44. }
  45. static inline bool sst_validate_mailbox_size(unsigned int size)
  46. {
  47. return ((size <= SST_MAILBOX_SIZE) ? true : false);
  48. }
  49. static irqreturn_t intel_sst_interrupt_mrfld(int irq, void *context)
  50. {
  51. union interrupt_reg_mrfld isr;
  52. union ipc_header_mrfld header;
  53. union sst_imr_reg_mrfld imr;
  54. struct ipc_post *msg = NULL;
  55. unsigned int size = 0;
  56. struct intel_sst_drv *drv = (struct intel_sst_drv *) context;
  57. irqreturn_t retval = IRQ_HANDLED;
  58. /* Interrupt arrived, check src */
  59. isr.full = sst_shim_read64(drv->shim, SST_ISRX);
  60. if (isr.part.done_interrupt) {
  61. /* Clear done bit */
  62. spin_lock(&drv->ipc_spin_lock);
  63. header.full = sst_shim_read64(drv->shim,
  64. drv->ipc_reg.ipcx);
  65. header.p.header_high.part.done = 0;
  66. sst_shim_write64(drv->shim, drv->ipc_reg.ipcx, header.full);
  67. /* write 1 to clear status register */;
  68. isr.part.done_interrupt = 1;
  69. sst_shim_write64(drv->shim, SST_ISRX, isr.full);
  70. spin_unlock(&drv->ipc_spin_lock);
  71. /* we can send more messages to DSP so trigger work */
  72. queue_work(drv->post_msg_wq, &drv->ipc_post_msg_wq);
  73. retval = IRQ_HANDLED;
  74. }
  75. if (isr.part.busy_interrupt) {
  76. /* message from dsp so copy that */
  77. spin_lock(&drv->ipc_spin_lock);
  78. imr.full = sst_shim_read64(drv->shim, SST_IMRX);
  79. imr.part.busy_interrupt = 1;
  80. sst_shim_write64(drv->shim, SST_IMRX, imr.full);
  81. spin_unlock(&drv->ipc_spin_lock);
  82. header.full = sst_shim_read64(drv->shim, drv->ipc_reg.ipcd);
  83. if (sst_create_ipc_msg(&msg, header.p.header_high.part.large)) {
  84. drv->ops->clear_interrupt(drv);
  85. return IRQ_HANDLED;
  86. }
  87. if (header.p.header_high.part.large) {
  88. size = header.p.header_low_payload;
  89. if (sst_validate_mailbox_size(size)) {
  90. memcpy_fromio(msg->mailbox_data,
  91. drv->mailbox + drv->mailbox_recv_offset, size);
  92. } else {
  93. dev_err(drv->dev,
  94. "Mailbox not copied, payload size is: %u\n", size);
  95. header.p.header_low_payload = 0;
  96. }
  97. }
  98. msg->mrfld_header = header;
  99. msg->is_process_reply =
  100. sst_is_process_reply(header.p.header_high.part.msg_id);
  101. spin_lock(&drv->rx_msg_lock);
  102. list_add_tail(&msg->node, &drv->rx_list);
  103. spin_unlock(&drv->rx_msg_lock);
  104. drv->ops->clear_interrupt(drv);
  105. retval = IRQ_WAKE_THREAD;
  106. }
  107. return retval;
  108. }
  109. static irqreturn_t intel_sst_irq_thread_mrfld(int irq, void *context)
  110. {
  111. struct intel_sst_drv *drv = (struct intel_sst_drv *) context;
  112. struct ipc_post *__msg, *msg = NULL;
  113. unsigned long irq_flags;
  114. spin_lock_irqsave(&drv->rx_msg_lock, irq_flags);
  115. if (list_empty(&drv->rx_list)) {
  116. spin_unlock_irqrestore(&drv->rx_msg_lock, irq_flags);
  117. return IRQ_HANDLED;
  118. }
  119. list_for_each_entry_safe(msg, __msg, &drv->rx_list, node) {
  120. list_del(&msg->node);
  121. spin_unlock_irqrestore(&drv->rx_msg_lock, irq_flags);
  122. if (msg->is_process_reply)
  123. drv->ops->process_message(msg);
  124. else
  125. drv->ops->process_reply(drv, msg);
  126. if (msg->is_large)
  127. kfree(msg->mailbox_data);
  128. kfree(msg);
  129. spin_lock_irqsave(&drv->rx_msg_lock, irq_flags);
  130. }
  131. spin_unlock_irqrestore(&drv->rx_msg_lock, irq_flags);
  132. return IRQ_HANDLED;
  133. }
  134. static int sst_save_dsp_context_v2(struct intel_sst_drv *sst)
  135. {
  136. int ret = 0;
  137. ret = sst_prepare_and_post_msg(sst, SST_TASK_ID_MEDIA, IPC_CMD,
  138. IPC_PREP_D3, PIPE_RSVD, 0, NULL, NULL,
  139. true, true, false, true);
  140. if (ret < 0) {
  141. dev_err(sst->dev, "not suspending FW!!, Err: %d\n", ret);
  142. return -EIO;
  143. }
  144. return 0;
  145. }
  146. static struct intel_sst_ops mrfld_ops = {
  147. .interrupt = intel_sst_interrupt_mrfld,
  148. .irq_thread = intel_sst_irq_thread_mrfld,
  149. .clear_interrupt = intel_sst_clear_intr_mrfld,
  150. .start = sst_start_mrfld,
  151. .reset = intel_sst_reset_dsp_mrfld,
  152. .post_message = sst_post_message_mrfld,
  153. .process_reply = sst_process_reply_mrfld,
  154. .save_dsp_context = sst_save_dsp_context_v2,
  155. .alloc_stream = sst_alloc_stream_mrfld,
  156. .post_download = sst_post_download_mrfld,
  157. };
  158. int sst_driver_ops(struct intel_sst_drv *sst)
  159. {
  160. switch (sst->dev_id) {
  161. case SST_MRFLD_PCI_ID:
  162. case SST_BYT_ACPI_ID:
  163. case SST_CHV_ACPI_ID:
  164. sst->tstamp = SST_TIME_STAMP_MRFLD;
  165. sst->ops = &mrfld_ops;
  166. return 0;
  167. default:
  168. dev_err(sst->dev,
  169. "SST Driver capabilities missing for dev_id: %x",
  170. sst->dev_id);
  171. return -EINVAL;
  172. };
  173. }
  174. void sst_process_pending_msg(struct work_struct *work)
  175. {
  176. struct intel_sst_drv *ctx = container_of(work,
  177. struct intel_sst_drv, ipc_post_msg_wq);
  178. ctx->ops->post_message(ctx, NULL, false);
  179. }
  180. static int sst_workqueue_init(struct intel_sst_drv *ctx)
  181. {
  182. INIT_LIST_HEAD(&ctx->memcpy_list);
  183. INIT_LIST_HEAD(&ctx->rx_list);
  184. INIT_LIST_HEAD(&ctx->ipc_dispatch_list);
  185. INIT_LIST_HEAD(&ctx->block_list);
  186. INIT_WORK(&ctx->ipc_post_msg_wq, sst_process_pending_msg);
  187. init_waitqueue_head(&ctx->wait_queue);
  188. ctx->post_msg_wq =
  189. create_singlethread_workqueue("sst_post_msg_wq");
  190. if (!ctx->post_msg_wq)
  191. return -EBUSY;
  192. return 0;
  193. }
  194. static void sst_init_locks(struct intel_sst_drv *ctx)
  195. {
  196. mutex_init(&ctx->sst_lock);
  197. spin_lock_init(&ctx->rx_msg_lock);
  198. spin_lock_init(&ctx->ipc_spin_lock);
  199. spin_lock_init(&ctx->block_lock);
  200. }
  201. int sst_alloc_drv_context(struct intel_sst_drv **ctx,
  202. struct device *dev, unsigned int dev_id)
  203. {
  204. *ctx = devm_kzalloc(dev, sizeof(struct intel_sst_drv), GFP_KERNEL);
  205. if (!(*ctx))
  206. return -ENOMEM;
  207. (*ctx)->dev = dev;
  208. (*ctx)->dev_id = dev_id;
  209. return 0;
  210. }
  211. EXPORT_SYMBOL_GPL(sst_alloc_drv_context);
  212. static ssize_t firmware_version_show(struct device *dev,
  213. struct device_attribute *attr, char *buf)
  214. {
  215. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  216. if (ctx->fw_version.type == 0 && ctx->fw_version.major == 0 &&
  217. ctx->fw_version.minor == 0 && ctx->fw_version.build == 0)
  218. return sprintf(buf, "FW not yet loaded\n");
  219. else
  220. return sprintf(buf, "v%02x.%02x.%02x.%02x\n",
  221. ctx->fw_version.type, ctx->fw_version.major,
  222. ctx->fw_version.minor, ctx->fw_version.build);
  223. }
  224. DEVICE_ATTR_RO(firmware_version);
  225. static const struct attribute *sst_fw_version_attrs[] = {
  226. &dev_attr_firmware_version.attr,
  227. NULL,
  228. };
  229. static const struct attribute_group sst_fw_version_attr_group = {
  230. .attrs = (struct attribute **)sst_fw_version_attrs,
  231. };
  232. int sst_context_init(struct intel_sst_drv *ctx)
  233. {
  234. int ret = 0, i;
  235. if (!ctx->pdata)
  236. return -EINVAL;
  237. if (!ctx->pdata->probe_data)
  238. return -EINVAL;
  239. memcpy(&ctx->info, ctx->pdata->probe_data, sizeof(ctx->info));
  240. ret = sst_driver_ops(ctx);
  241. if (ret != 0)
  242. return -EINVAL;
  243. sst_init_locks(ctx);
  244. sst_set_fw_state_locked(ctx, SST_RESET);
  245. /* pvt_id 0 reserved for async messages */
  246. ctx->pvt_id = 1;
  247. ctx->stream_cnt = 0;
  248. ctx->fw_in_mem = NULL;
  249. /* we use memcpy, so set to 0 */
  250. ctx->use_dma = 0;
  251. ctx->use_lli = 0;
  252. if (sst_workqueue_init(ctx))
  253. return -EINVAL;
  254. ctx->mailbox_recv_offset = ctx->pdata->ipc_info->mbox_recv_off;
  255. ctx->ipc_reg.ipcx = SST_IPCX + ctx->pdata->ipc_info->ipc_offset;
  256. ctx->ipc_reg.ipcd = SST_IPCD + ctx->pdata->ipc_info->ipc_offset;
  257. dev_info(ctx->dev, "Got drv data max stream %d\n",
  258. ctx->info.max_streams);
  259. for (i = 1; i <= ctx->info.max_streams; i++) {
  260. struct stream_info *stream = &ctx->streams[i];
  261. memset(stream, 0, sizeof(*stream));
  262. stream->pipe_id = PIPE_RSVD;
  263. mutex_init(&stream->lock);
  264. }
  265. /* Register the ISR */
  266. ret = devm_request_threaded_irq(ctx->dev, ctx->irq_num, ctx->ops->interrupt,
  267. ctx->ops->irq_thread, 0, SST_DRV_NAME,
  268. ctx);
  269. if (ret)
  270. goto do_free_mem;
  271. dev_dbg(ctx->dev, "Registered IRQ %#x\n", ctx->irq_num);
  272. /* default intr are unmasked so set this as masked */
  273. sst_shim_write64(ctx->shim, SST_IMRX, 0xFFFF0038);
  274. ctx->qos = devm_kzalloc(ctx->dev,
  275. sizeof(struct pm_qos_request), GFP_KERNEL);
  276. if (!ctx->qos) {
  277. ret = -ENOMEM;
  278. goto do_free_mem;
  279. }
  280. pm_qos_add_request(ctx->qos, PM_QOS_CPU_DMA_LATENCY,
  281. PM_QOS_DEFAULT_VALUE);
  282. dev_dbg(ctx->dev, "Requesting FW %s now...\n", ctx->firmware_name);
  283. ret = request_firmware_nowait(THIS_MODULE, true, ctx->firmware_name,
  284. ctx->dev, GFP_KERNEL, ctx, sst_firmware_load_cb);
  285. if (ret) {
  286. dev_err(ctx->dev, "Firmware download failed:%d\n", ret);
  287. goto do_free_mem;
  288. }
  289. ret = sysfs_create_group(&ctx->dev->kobj,
  290. &sst_fw_version_attr_group);
  291. if (ret) {
  292. dev_err(ctx->dev,
  293. "Unable to create sysfs\n");
  294. goto err_sysfs;
  295. }
  296. sst_register(ctx->dev);
  297. return 0;
  298. err_sysfs:
  299. sysfs_remove_group(&ctx->dev->kobj, &sst_fw_version_attr_group);
  300. do_free_mem:
  301. destroy_workqueue(ctx->post_msg_wq);
  302. return ret;
  303. }
  304. EXPORT_SYMBOL_GPL(sst_context_init);
  305. void sst_context_cleanup(struct intel_sst_drv *ctx)
  306. {
  307. pm_runtime_get_noresume(ctx->dev);
  308. pm_runtime_disable(ctx->dev);
  309. sst_unregister(ctx->dev);
  310. sst_set_fw_state_locked(ctx, SST_SHUTDOWN);
  311. sysfs_remove_group(&ctx->dev->kobj, &sst_fw_version_attr_group);
  312. flush_scheduled_work();
  313. destroy_workqueue(ctx->post_msg_wq);
  314. pm_qos_remove_request(ctx->qos);
  315. kfree(ctx->fw_sg_list.src);
  316. kfree(ctx->fw_sg_list.dst);
  317. ctx->fw_sg_list.list_len = 0;
  318. kfree(ctx->fw_in_mem);
  319. ctx->fw_in_mem = NULL;
  320. sst_memcpy_free_resources(ctx);
  321. ctx = NULL;
  322. }
  323. EXPORT_SYMBOL_GPL(sst_context_cleanup);
  324. static inline void sst_save_shim64(struct intel_sst_drv *ctx,
  325. void __iomem *shim,
  326. struct sst_shim_regs64 *shim_regs)
  327. {
  328. unsigned long irq_flags;
  329. spin_lock_irqsave(&ctx->ipc_spin_lock, irq_flags);
  330. shim_regs->imrx = sst_shim_read64(shim, SST_IMRX);
  331. shim_regs->csr = sst_shim_read64(shim, SST_CSR);
  332. spin_unlock_irqrestore(&ctx->ipc_spin_lock, irq_flags);
  333. }
  334. static inline void sst_restore_shim64(struct intel_sst_drv *ctx,
  335. void __iomem *shim,
  336. struct sst_shim_regs64 *shim_regs)
  337. {
  338. unsigned long irq_flags;
  339. /*
  340. * we only need to restore IMRX for this case, rest will be
  341. * initialize by FW or driver when firmware is loaded
  342. */
  343. spin_lock_irqsave(&ctx->ipc_spin_lock, irq_flags);
  344. sst_shim_write64(shim, SST_IMRX, shim_regs->imrx);
  345. sst_shim_write64(shim, SST_CSR, shim_regs->csr);
  346. spin_unlock_irqrestore(&ctx->ipc_spin_lock, irq_flags);
  347. }
  348. void sst_configure_runtime_pm(struct intel_sst_drv *ctx)
  349. {
  350. pm_runtime_set_autosuspend_delay(ctx->dev, SST_SUSPEND_DELAY);
  351. pm_runtime_use_autosuspend(ctx->dev);
  352. /*
  353. * For acpi devices, the actual physical device state is
  354. * initially active. So change the state to active before
  355. * enabling the pm
  356. */
  357. if (!acpi_disabled)
  358. pm_runtime_set_active(ctx->dev);
  359. pm_runtime_enable(ctx->dev);
  360. if (acpi_disabled)
  361. pm_runtime_set_active(ctx->dev);
  362. else
  363. pm_runtime_put_noidle(ctx->dev);
  364. sst_save_shim64(ctx, ctx->shim, ctx->shim_regs64);
  365. }
  366. EXPORT_SYMBOL_GPL(sst_configure_runtime_pm);
  367. static int intel_sst_runtime_suspend(struct device *dev)
  368. {
  369. int ret = 0;
  370. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  371. if (ctx->sst_state == SST_RESET) {
  372. dev_dbg(dev, "LPE is already in RESET state, No action\n");
  373. return 0;
  374. }
  375. /* save fw context */
  376. if (ctx->ops->save_dsp_context(ctx))
  377. return -EBUSY;
  378. /* Move the SST state to Reset */
  379. sst_set_fw_state_locked(ctx, SST_RESET);
  380. synchronize_irq(ctx->irq_num);
  381. flush_workqueue(ctx->post_msg_wq);
  382. ctx->ops->reset(ctx);
  383. /* save the shim registers because PMC doesn't save state */
  384. sst_save_shim64(ctx, ctx->shim, ctx->shim_regs64);
  385. return ret;
  386. }
  387. static int intel_sst_suspend(struct device *dev)
  388. {
  389. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  390. struct sst_fw_save *fw_save;
  391. int i, ret = 0;
  392. /* check first if we are already in SW reset */
  393. if (ctx->sst_state == SST_RESET)
  394. return 0;
  395. /*
  396. * check if any stream is active and running
  397. * they should already by suspend by soc_suspend
  398. */
  399. for (i = 1; i <= ctx->info.max_streams; i++) {
  400. struct stream_info *stream = &ctx->streams[i];
  401. if (stream->status == STREAM_RUNNING) {
  402. dev_err(dev, "stream %d is running, can't suspend, abort\n", i);
  403. return -EBUSY;
  404. }
  405. }
  406. synchronize_irq(ctx->irq_num);
  407. flush_workqueue(ctx->post_msg_wq);
  408. /* Move the SST state to Reset */
  409. sst_set_fw_state_locked(ctx, SST_RESET);
  410. /* tell DSP we are suspending */
  411. if (ctx->ops->save_dsp_context(ctx))
  412. return -EBUSY;
  413. /* save the memories */
  414. fw_save = kzalloc(sizeof(*fw_save), GFP_KERNEL);
  415. if (!fw_save)
  416. return -ENOMEM;
  417. fw_save->iram = kzalloc(ctx->iram_end - ctx->iram_base, GFP_KERNEL);
  418. if (!fw_save->iram) {
  419. ret = -ENOMEM;
  420. goto iram;
  421. }
  422. fw_save->dram = kzalloc(ctx->dram_end - ctx->dram_base, GFP_KERNEL);
  423. if (!fw_save->dram) {
  424. ret = -ENOMEM;
  425. goto dram;
  426. }
  427. fw_save->sram = kzalloc(SST_MAILBOX_SIZE, GFP_KERNEL);
  428. if (!fw_save->sram) {
  429. ret = -ENOMEM;
  430. goto sram;
  431. }
  432. fw_save->ddr = kzalloc(ctx->ddr_end - ctx->ddr_base, GFP_KERNEL);
  433. if (!fw_save->ddr) {
  434. ret = -ENOMEM;
  435. goto ddr;
  436. }
  437. memcpy32_fromio(fw_save->iram, ctx->iram, ctx->iram_end - ctx->iram_base);
  438. memcpy32_fromio(fw_save->dram, ctx->dram, ctx->dram_end - ctx->dram_base);
  439. memcpy32_fromio(fw_save->sram, ctx->mailbox, SST_MAILBOX_SIZE);
  440. memcpy32_fromio(fw_save->ddr, ctx->ddr, ctx->ddr_end - ctx->ddr_base);
  441. ctx->fw_save = fw_save;
  442. ctx->ops->reset(ctx);
  443. return 0;
  444. ddr:
  445. kfree(fw_save->sram);
  446. sram:
  447. kfree(fw_save->dram);
  448. dram:
  449. kfree(fw_save->iram);
  450. iram:
  451. kfree(fw_save);
  452. return ret;
  453. }
  454. static int intel_sst_resume(struct device *dev)
  455. {
  456. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  457. struct sst_fw_save *fw_save = ctx->fw_save;
  458. int ret = 0;
  459. struct sst_block *block;
  460. if (!fw_save)
  461. return 0;
  462. sst_set_fw_state_locked(ctx, SST_FW_LOADING);
  463. /* we have to restore the memory saved */
  464. ctx->ops->reset(ctx);
  465. ctx->fw_save = NULL;
  466. memcpy32_toio(ctx->iram, fw_save->iram, ctx->iram_end - ctx->iram_base);
  467. memcpy32_toio(ctx->dram, fw_save->dram, ctx->dram_end - ctx->dram_base);
  468. memcpy32_toio(ctx->mailbox, fw_save->sram, SST_MAILBOX_SIZE);
  469. memcpy32_toio(ctx->ddr, fw_save->ddr, ctx->ddr_end - ctx->ddr_base);
  470. kfree(fw_save->sram);
  471. kfree(fw_save->dram);
  472. kfree(fw_save->iram);
  473. kfree(fw_save->ddr);
  474. kfree(fw_save);
  475. block = sst_create_block(ctx, 0, FW_DWNL_ID);
  476. if (block == NULL)
  477. return -ENOMEM;
  478. /* start and wait for ack */
  479. ctx->ops->start(ctx);
  480. ret = sst_wait_timeout(ctx, block);
  481. if (ret) {
  482. dev_err(ctx->dev, "fw download failed %d\n", ret);
  483. /* FW download failed due to timeout */
  484. ret = -EBUSY;
  485. } else {
  486. sst_set_fw_state_locked(ctx, SST_FW_RUNNING);
  487. }
  488. sst_free_block(ctx, block);
  489. return ret;
  490. }
  491. const struct dev_pm_ops intel_sst_pm = {
  492. .suspend = intel_sst_suspend,
  493. .resume = intel_sst_resume,
  494. .runtime_suspend = intel_sst_runtime_suspend,
  495. };
  496. EXPORT_SYMBOL_GPL(intel_sst_pm);