chip.c 30 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202
  1. /*
  2. * linux/kernel/irq/chip.c
  3. *
  4. * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
  5. * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
  6. *
  7. * This file contains the core interrupt handling code, for irq-chip
  8. * based architectures.
  9. *
  10. * Detailed information is available in Documentation/DocBook/genericirq
  11. */
  12. #include <linux/irq.h>
  13. #include <linux/msi.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel_stat.h>
  17. #include <linux/irqdomain.h>
  18. #include <trace/events/irq.h>
  19. #include "internals.h"
  20. static irqreturn_t bad_chained_irq(int irq, void *dev_id)
  21. {
  22. WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
  23. return IRQ_NONE;
  24. }
  25. /*
  26. * Chained handlers should never call action on their IRQ. This default
  27. * action will emit warning if such thing happens.
  28. */
  29. struct irqaction chained_action = {
  30. .handler = bad_chained_irq,
  31. };
  32. /**
  33. * irq_set_chip - set the irq chip for an irq
  34. * @irq: irq number
  35. * @chip: pointer to irq chip description structure
  36. */
  37. int irq_set_chip(unsigned int irq, struct irq_chip *chip)
  38. {
  39. unsigned long flags;
  40. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  41. if (!desc)
  42. return -EINVAL;
  43. if (!chip)
  44. chip = &no_irq_chip;
  45. desc->irq_data.chip = chip;
  46. irq_put_desc_unlock(desc, flags);
  47. /*
  48. * For !CONFIG_SPARSE_IRQ make the irq show up in
  49. * allocated_irqs.
  50. */
  51. irq_mark_irq(irq);
  52. return 0;
  53. }
  54. EXPORT_SYMBOL(irq_set_chip);
  55. /**
  56. * irq_set_type - set the irq trigger type for an irq
  57. * @irq: irq number
  58. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  59. */
  60. int irq_set_irq_type(unsigned int irq, unsigned int type)
  61. {
  62. unsigned long flags;
  63. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  64. int ret = 0;
  65. if (!desc)
  66. return -EINVAL;
  67. ret = __irq_set_trigger(desc, type);
  68. irq_put_desc_busunlock(desc, flags);
  69. return ret;
  70. }
  71. EXPORT_SYMBOL(irq_set_irq_type);
  72. /**
  73. * irq_set_handler_data - set irq handler data for an irq
  74. * @irq: Interrupt number
  75. * @data: Pointer to interrupt specific data
  76. *
  77. * Set the hardware irq controller data for an irq
  78. */
  79. int irq_set_handler_data(unsigned int irq, void *data)
  80. {
  81. unsigned long flags;
  82. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  83. if (!desc)
  84. return -EINVAL;
  85. desc->irq_common_data.handler_data = data;
  86. irq_put_desc_unlock(desc, flags);
  87. return 0;
  88. }
  89. EXPORT_SYMBOL(irq_set_handler_data);
  90. /**
  91. * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
  92. * @irq_base: Interrupt number base
  93. * @irq_offset: Interrupt number offset
  94. * @entry: Pointer to MSI descriptor data
  95. *
  96. * Set the MSI descriptor entry for an irq at offset
  97. */
  98. int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
  99. struct msi_desc *entry)
  100. {
  101. unsigned long flags;
  102. struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
  103. if (!desc)
  104. return -EINVAL;
  105. desc->irq_common_data.msi_desc = entry;
  106. if (entry && !irq_offset)
  107. entry->irq = irq_base;
  108. irq_put_desc_unlock(desc, flags);
  109. return 0;
  110. }
  111. /**
  112. * irq_set_msi_desc - set MSI descriptor data for an irq
  113. * @irq: Interrupt number
  114. * @entry: Pointer to MSI descriptor data
  115. *
  116. * Set the MSI descriptor entry for an irq
  117. */
  118. int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
  119. {
  120. return irq_set_msi_desc_off(irq, 0, entry);
  121. }
  122. /**
  123. * irq_set_chip_data - set irq chip data for an irq
  124. * @irq: Interrupt number
  125. * @data: Pointer to chip specific data
  126. *
  127. * Set the hardware irq chip data for an irq
  128. */
  129. int irq_set_chip_data(unsigned int irq, void *data)
  130. {
  131. unsigned long flags;
  132. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  133. if (!desc)
  134. return -EINVAL;
  135. desc->irq_data.chip_data = data;
  136. irq_put_desc_unlock(desc, flags);
  137. return 0;
  138. }
  139. EXPORT_SYMBOL(irq_set_chip_data);
  140. struct irq_data *irq_get_irq_data(unsigned int irq)
  141. {
  142. struct irq_desc *desc = irq_to_desc(irq);
  143. return desc ? &desc->irq_data : NULL;
  144. }
  145. EXPORT_SYMBOL_GPL(irq_get_irq_data);
  146. static void irq_state_clr_disabled(struct irq_desc *desc)
  147. {
  148. irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
  149. }
  150. static void irq_state_set_disabled(struct irq_desc *desc)
  151. {
  152. irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
  153. }
  154. static void irq_state_clr_masked(struct irq_desc *desc)
  155. {
  156. irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
  157. }
  158. static void irq_state_set_masked(struct irq_desc *desc)
  159. {
  160. irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
  161. }
  162. int irq_startup(struct irq_desc *desc, bool resend)
  163. {
  164. int ret = 0;
  165. irq_state_clr_disabled(desc);
  166. desc->depth = 0;
  167. irq_domain_activate_irq(&desc->irq_data);
  168. if (desc->irq_data.chip->irq_startup) {
  169. ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
  170. irq_state_clr_masked(desc);
  171. } else {
  172. irq_enable(desc);
  173. }
  174. if (resend)
  175. check_irq_resend(desc);
  176. return ret;
  177. }
  178. void irq_shutdown(struct irq_desc *desc)
  179. {
  180. irq_state_set_disabled(desc);
  181. desc->depth = 1;
  182. if (desc->irq_data.chip->irq_shutdown)
  183. desc->irq_data.chip->irq_shutdown(&desc->irq_data);
  184. else if (desc->irq_data.chip->irq_disable)
  185. desc->irq_data.chip->irq_disable(&desc->irq_data);
  186. else
  187. desc->irq_data.chip->irq_mask(&desc->irq_data);
  188. irq_domain_deactivate_irq(&desc->irq_data);
  189. irq_state_set_masked(desc);
  190. }
  191. void irq_enable(struct irq_desc *desc)
  192. {
  193. irq_state_clr_disabled(desc);
  194. if (desc->irq_data.chip->irq_enable)
  195. desc->irq_data.chip->irq_enable(&desc->irq_data);
  196. else
  197. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  198. irq_state_clr_masked(desc);
  199. }
  200. /**
  201. * irq_disable - Mark interrupt disabled
  202. * @desc: irq descriptor which should be disabled
  203. *
  204. * If the chip does not implement the irq_disable callback, we
  205. * use a lazy disable approach. That means we mark the interrupt
  206. * disabled, but leave the hardware unmasked. That's an
  207. * optimization because we avoid the hardware access for the
  208. * common case where no interrupt happens after we marked it
  209. * disabled. If an interrupt happens, then the interrupt flow
  210. * handler masks the line at the hardware level and marks it
  211. * pending.
  212. *
  213. * If the interrupt chip does not implement the irq_disable callback,
  214. * a driver can disable the lazy approach for a particular irq line by
  215. * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
  216. * be used for devices which cannot disable the interrupt at the
  217. * device level under certain circumstances and have to use
  218. * disable_irq[_nosync] instead.
  219. */
  220. void irq_disable(struct irq_desc *desc)
  221. {
  222. irq_state_set_disabled(desc);
  223. if (desc->irq_data.chip->irq_disable) {
  224. desc->irq_data.chip->irq_disable(&desc->irq_data);
  225. irq_state_set_masked(desc);
  226. } else if (irq_settings_disable_unlazy(desc)) {
  227. mask_irq(desc);
  228. }
  229. }
  230. void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
  231. {
  232. if (desc->irq_data.chip->irq_enable)
  233. desc->irq_data.chip->irq_enable(&desc->irq_data);
  234. else
  235. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  236. cpumask_set_cpu(cpu, desc->percpu_enabled);
  237. }
  238. void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
  239. {
  240. if (desc->irq_data.chip->irq_disable)
  241. desc->irq_data.chip->irq_disable(&desc->irq_data);
  242. else
  243. desc->irq_data.chip->irq_mask(&desc->irq_data);
  244. cpumask_clear_cpu(cpu, desc->percpu_enabled);
  245. }
  246. static inline void mask_ack_irq(struct irq_desc *desc)
  247. {
  248. if (desc->irq_data.chip->irq_mask_ack)
  249. desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
  250. else {
  251. desc->irq_data.chip->irq_mask(&desc->irq_data);
  252. if (desc->irq_data.chip->irq_ack)
  253. desc->irq_data.chip->irq_ack(&desc->irq_data);
  254. }
  255. irq_state_set_masked(desc);
  256. }
  257. void mask_irq(struct irq_desc *desc)
  258. {
  259. if (desc->irq_data.chip->irq_mask) {
  260. desc->irq_data.chip->irq_mask(&desc->irq_data);
  261. irq_state_set_masked(desc);
  262. }
  263. }
  264. void unmask_irq(struct irq_desc *desc)
  265. {
  266. if (desc->irq_data.chip->irq_unmask) {
  267. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  268. irq_state_clr_masked(desc);
  269. }
  270. }
  271. void unmask_threaded_irq(struct irq_desc *desc)
  272. {
  273. struct irq_chip *chip = desc->irq_data.chip;
  274. if (chip->flags & IRQCHIP_EOI_THREADED)
  275. chip->irq_eoi(&desc->irq_data);
  276. if (chip->irq_unmask) {
  277. chip->irq_unmask(&desc->irq_data);
  278. irq_state_clr_masked(desc);
  279. }
  280. }
  281. /*
  282. * handle_nested_irq - Handle a nested irq from a irq thread
  283. * @irq: the interrupt number
  284. *
  285. * Handle interrupts which are nested into a threaded interrupt
  286. * handler. The handler function is called inside the calling
  287. * threads context.
  288. */
  289. void handle_nested_irq(unsigned int irq)
  290. {
  291. struct irq_desc *desc = irq_to_desc(irq);
  292. struct irqaction *action;
  293. irqreturn_t action_ret;
  294. might_sleep();
  295. raw_spin_lock_irq(&desc->lock);
  296. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  297. action = desc->action;
  298. if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
  299. desc->istate |= IRQS_PENDING;
  300. goto out_unlock;
  301. }
  302. kstat_incr_irqs_this_cpu(desc);
  303. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  304. raw_spin_unlock_irq(&desc->lock);
  305. action_ret = action->thread_fn(action->irq, action->dev_id);
  306. if (!noirqdebug)
  307. note_interrupt(desc, action_ret);
  308. raw_spin_lock_irq(&desc->lock);
  309. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  310. out_unlock:
  311. raw_spin_unlock_irq(&desc->lock);
  312. }
  313. EXPORT_SYMBOL_GPL(handle_nested_irq);
  314. static bool irq_check_poll(struct irq_desc *desc)
  315. {
  316. if (!(desc->istate & IRQS_POLL_INPROGRESS))
  317. return false;
  318. return irq_wait_for_poll(desc);
  319. }
  320. static bool irq_may_run(struct irq_desc *desc)
  321. {
  322. unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
  323. /*
  324. * If the interrupt is not in progress and is not an armed
  325. * wakeup interrupt, proceed.
  326. */
  327. if (!irqd_has_set(&desc->irq_data, mask))
  328. return true;
  329. /*
  330. * If the interrupt is an armed wakeup source, mark it pending
  331. * and suspended, disable it and notify the pm core about the
  332. * event.
  333. */
  334. if (irq_pm_check_wakeup(desc))
  335. return false;
  336. /*
  337. * Handle a potential concurrent poll on a different core.
  338. */
  339. return irq_check_poll(desc);
  340. }
  341. /**
  342. * handle_simple_irq - Simple and software-decoded IRQs.
  343. * @desc: the interrupt description structure for this irq
  344. *
  345. * Simple interrupts are either sent from a demultiplexing interrupt
  346. * handler or come from hardware, where no interrupt hardware control
  347. * is necessary.
  348. *
  349. * Note: The caller is expected to handle the ack, clear, mask and
  350. * unmask issues if necessary.
  351. */
  352. void handle_simple_irq(struct irq_desc *desc)
  353. {
  354. raw_spin_lock(&desc->lock);
  355. if (!irq_may_run(desc))
  356. goto out_unlock;
  357. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  358. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  359. desc->istate |= IRQS_PENDING;
  360. goto out_unlock;
  361. }
  362. kstat_incr_irqs_this_cpu(desc);
  363. handle_irq_event(desc);
  364. out_unlock:
  365. raw_spin_unlock(&desc->lock);
  366. }
  367. EXPORT_SYMBOL_GPL(handle_simple_irq);
  368. /**
  369. * handle_untracked_irq - Simple and software-decoded IRQs.
  370. * @desc: the interrupt description structure for this irq
  371. *
  372. * Untracked interrupts are sent from a demultiplexing interrupt
  373. * handler when the demultiplexer does not know which device it its
  374. * multiplexed irq domain generated the interrupt. IRQ's handled
  375. * through here are not subjected to stats tracking, randomness, or
  376. * spurious interrupt detection.
  377. *
  378. * Note: Like handle_simple_irq, the caller is expected to handle
  379. * the ack, clear, mask and unmask issues if necessary.
  380. */
  381. void handle_untracked_irq(struct irq_desc *desc)
  382. {
  383. unsigned int flags = 0;
  384. raw_spin_lock(&desc->lock);
  385. if (!irq_may_run(desc))
  386. goto out_unlock;
  387. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  388. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  389. desc->istate |= IRQS_PENDING;
  390. goto out_unlock;
  391. }
  392. desc->istate &= ~IRQS_PENDING;
  393. irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  394. raw_spin_unlock(&desc->lock);
  395. __handle_irq_event_percpu(desc, &flags);
  396. raw_spin_lock(&desc->lock);
  397. irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
  398. out_unlock:
  399. raw_spin_unlock(&desc->lock);
  400. }
  401. EXPORT_SYMBOL_GPL(handle_untracked_irq);
  402. /*
  403. * Called unconditionally from handle_level_irq() and only for oneshot
  404. * interrupts from handle_fasteoi_irq()
  405. */
  406. static void cond_unmask_irq(struct irq_desc *desc)
  407. {
  408. /*
  409. * We need to unmask in the following cases:
  410. * - Standard level irq (IRQF_ONESHOT is not set)
  411. * - Oneshot irq which did not wake the thread (caused by a
  412. * spurious interrupt or a primary handler handling it
  413. * completely).
  414. */
  415. if (!irqd_irq_disabled(&desc->irq_data) &&
  416. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
  417. unmask_irq(desc);
  418. }
  419. /**
  420. * handle_level_irq - Level type irq handler
  421. * @desc: the interrupt description structure for this irq
  422. *
  423. * Level type interrupts are active as long as the hardware line has
  424. * the active level. This may require to mask the interrupt and unmask
  425. * it after the associated handler has acknowledged the device, so the
  426. * interrupt line is back to inactive.
  427. */
  428. void handle_level_irq(struct irq_desc *desc)
  429. {
  430. raw_spin_lock(&desc->lock);
  431. mask_ack_irq(desc);
  432. if (!irq_may_run(desc))
  433. goto out_unlock;
  434. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  435. /*
  436. * If its disabled or no action available
  437. * keep it masked and get out of here
  438. */
  439. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  440. desc->istate |= IRQS_PENDING;
  441. goto out_unlock;
  442. }
  443. kstat_incr_irqs_this_cpu(desc);
  444. handle_irq_event(desc);
  445. cond_unmask_irq(desc);
  446. out_unlock:
  447. raw_spin_unlock(&desc->lock);
  448. }
  449. EXPORT_SYMBOL_GPL(handle_level_irq);
  450. #ifdef CONFIG_IRQ_PREFLOW_FASTEOI
  451. static inline void preflow_handler(struct irq_desc *desc)
  452. {
  453. if (desc->preflow_handler)
  454. desc->preflow_handler(&desc->irq_data);
  455. }
  456. #else
  457. static inline void preflow_handler(struct irq_desc *desc) { }
  458. #endif
  459. static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
  460. {
  461. if (!(desc->istate & IRQS_ONESHOT)) {
  462. chip->irq_eoi(&desc->irq_data);
  463. return;
  464. }
  465. /*
  466. * We need to unmask in the following cases:
  467. * - Oneshot irq which did not wake the thread (caused by a
  468. * spurious interrupt or a primary handler handling it
  469. * completely).
  470. */
  471. if (!irqd_irq_disabled(&desc->irq_data) &&
  472. irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
  473. chip->irq_eoi(&desc->irq_data);
  474. unmask_irq(desc);
  475. } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
  476. chip->irq_eoi(&desc->irq_data);
  477. }
  478. }
  479. /**
  480. * handle_fasteoi_irq - irq handler for transparent controllers
  481. * @desc: the interrupt description structure for this irq
  482. *
  483. * Only a single callback will be issued to the chip: an ->eoi()
  484. * call when the interrupt has been serviced. This enables support
  485. * for modern forms of interrupt handlers, which handle the flow
  486. * details in hardware, transparently.
  487. */
  488. void handle_fasteoi_irq(struct irq_desc *desc)
  489. {
  490. struct irq_chip *chip = desc->irq_data.chip;
  491. raw_spin_lock(&desc->lock);
  492. if (!irq_may_run(desc))
  493. goto out;
  494. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  495. /*
  496. * If its disabled or no action available
  497. * then mask it and get out of here:
  498. */
  499. if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
  500. desc->istate |= IRQS_PENDING;
  501. mask_irq(desc);
  502. goto out;
  503. }
  504. kstat_incr_irqs_this_cpu(desc);
  505. if (desc->istate & IRQS_ONESHOT)
  506. mask_irq(desc);
  507. preflow_handler(desc);
  508. handle_irq_event(desc);
  509. cond_unmask_eoi_irq(desc, chip);
  510. raw_spin_unlock(&desc->lock);
  511. return;
  512. out:
  513. if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
  514. chip->irq_eoi(&desc->irq_data);
  515. raw_spin_unlock(&desc->lock);
  516. }
  517. EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
  518. /**
  519. * handle_edge_irq - edge type IRQ handler
  520. * @desc: the interrupt description structure for this irq
  521. *
  522. * Interrupt occures on the falling and/or rising edge of a hardware
  523. * signal. The occurrence is latched into the irq controller hardware
  524. * and must be acked in order to be reenabled. After the ack another
  525. * interrupt can happen on the same source even before the first one
  526. * is handled by the associated event handler. If this happens it
  527. * might be necessary to disable (mask) the interrupt depending on the
  528. * controller hardware. This requires to reenable the interrupt inside
  529. * of the loop which handles the interrupts which have arrived while
  530. * the handler was running. If all pending interrupts are handled, the
  531. * loop is left.
  532. */
  533. void handle_edge_irq(struct irq_desc *desc)
  534. {
  535. raw_spin_lock(&desc->lock);
  536. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  537. if (!irq_may_run(desc)) {
  538. desc->istate |= IRQS_PENDING;
  539. mask_ack_irq(desc);
  540. goto out_unlock;
  541. }
  542. /*
  543. * If its disabled or no action available then mask it and get
  544. * out of here.
  545. */
  546. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  547. desc->istate |= IRQS_PENDING;
  548. mask_ack_irq(desc);
  549. goto out_unlock;
  550. }
  551. kstat_incr_irqs_this_cpu(desc);
  552. /* Start handling the irq */
  553. desc->irq_data.chip->irq_ack(&desc->irq_data);
  554. do {
  555. if (unlikely(!desc->action)) {
  556. mask_irq(desc);
  557. goto out_unlock;
  558. }
  559. /*
  560. * When another irq arrived while we were handling
  561. * one, we could have masked the irq.
  562. * Renable it, if it was not disabled in meantime.
  563. */
  564. if (unlikely(desc->istate & IRQS_PENDING)) {
  565. if (!irqd_irq_disabled(&desc->irq_data) &&
  566. irqd_irq_masked(&desc->irq_data))
  567. unmask_irq(desc);
  568. }
  569. handle_irq_event(desc);
  570. } while ((desc->istate & IRQS_PENDING) &&
  571. !irqd_irq_disabled(&desc->irq_data));
  572. out_unlock:
  573. raw_spin_unlock(&desc->lock);
  574. }
  575. EXPORT_SYMBOL(handle_edge_irq);
  576. #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
  577. /**
  578. * handle_edge_eoi_irq - edge eoi type IRQ handler
  579. * @desc: the interrupt description structure for this irq
  580. *
  581. * Similar as the above handle_edge_irq, but using eoi and w/o the
  582. * mask/unmask logic.
  583. */
  584. void handle_edge_eoi_irq(struct irq_desc *desc)
  585. {
  586. struct irq_chip *chip = irq_desc_get_chip(desc);
  587. raw_spin_lock(&desc->lock);
  588. desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
  589. if (!irq_may_run(desc)) {
  590. desc->istate |= IRQS_PENDING;
  591. goto out_eoi;
  592. }
  593. /*
  594. * If its disabled or no action available then mask it and get
  595. * out of here.
  596. */
  597. if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
  598. desc->istate |= IRQS_PENDING;
  599. goto out_eoi;
  600. }
  601. kstat_incr_irqs_this_cpu(desc);
  602. do {
  603. if (unlikely(!desc->action))
  604. goto out_eoi;
  605. handle_irq_event(desc);
  606. } while ((desc->istate & IRQS_PENDING) &&
  607. !irqd_irq_disabled(&desc->irq_data));
  608. out_eoi:
  609. chip->irq_eoi(&desc->irq_data);
  610. raw_spin_unlock(&desc->lock);
  611. }
  612. #endif
  613. /**
  614. * handle_percpu_irq - Per CPU local irq handler
  615. * @desc: the interrupt description structure for this irq
  616. *
  617. * Per CPU interrupts on SMP machines without locking requirements
  618. */
  619. void handle_percpu_irq(struct irq_desc *desc)
  620. {
  621. struct irq_chip *chip = irq_desc_get_chip(desc);
  622. kstat_incr_irqs_this_cpu(desc);
  623. if (chip->irq_ack)
  624. chip->irq_ack(&desc->irq_data);
  625. handle_irq_event_percpu(desc);
  626. if (chip->irq_eoi)
  627. chip->irq_eoi(&desc->irq_data);
  628. }
  629. /**
  630. * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
  631. * @desc: the interrupt description structure for this irq
  632. *
  633. * Per CPU interrupts on SMP machines without locking requirements. Same as
  634. * handle_percpu_irq() above but with the following extras:
  635. *
  636. * action->percpu_dev_id is a pointer to percpu variables which
  637. * contain the real device id for the cpu on which this handler is
  638. * called
  639. */
  640. void handle_percpu_devid_irq(struct irq_desc *desc)
  641. {
  642. struct irq_chip *chip = irq_desc_get_chip(desc);
  643. struct irqaction *action = desc->action;
  644. unsigned int irq = irq_desc_get_irq(desc);
  645. irqreturn_t res;
  646. kstat_incr_irqs_this_cpu(desc);
  647. if (chip->irq_ack)
  648. chip->irq_ack(&desc->irq_data);
  649. if (likely(action)) {
  650. trace_irq_handler_entry(irq, action);
  651. res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
  652. trace_irq_handler_exit(irq, action, res);
  653. } else {
  654. unsigned int cpu = smp_processor_id();
  655. bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
  656. if (enabled)
  657. irq_percpu_disable(desc, cpu);
  658. pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
  659. enabled ? " and unmasked" : "", irq, cpu);
  660. }
  661. if (chip->irq_eoi)
  662. chip->irq_eoi(&desc->irq_data);
  663. }
  664. static void
  665. __irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
  666. int is_chained, const char *name)
  667. {
  668. if (!handle) {
  669. handle = handle_bad_irq;
  670. } else {
  671. struct irq_data *irq_data = &desc->irq_data;
  672. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  673. /*
  674. * With hierarchical domains we might run into a
  675. * situation where the outermost chip is not yet set
  676. * up, but the inner chips are there. Instead of
  677. * bailing we install the handler, but obviously we
  678. * cannot enable/startup the interrupt at this point.
  679. */
  680. while (irq_data) {
  681. if (irq_data->chip != &no_irq_chip)
  682. break;
  683. /*
  684. * Bail out if the outer chip is not set up
  685. * and the interrrupt supposed to be started
  686. * right away.
  687. */
  688. if (WARN_ON(is_chained))
  689. return;
  690. /* Try the parent */
  691. irq_data = irq_data->parent_data;
  692. }
  693. #endif
  694. if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
  695. return;
  696. }
  697. /* Uninstall? */
  698. if (handle == handle_bad_irq) {
  699. if (desc->irq_data.chip != &no_irq_chip)
  700. mask_ack_irq(desc);
  701. irq_state_set_disabled(desc);
  702. if (is_chained)
  703. desc->action = NULL;
  704. desc->depth = 1;
  705. }
  706. desc->handle_irq = handle;
  707. desc->name = name;
  708. if (handle != handle_bad_irq && is_chained) {
  709. unsigned int type = irqd_get_trigger_type(&desc->irq_data);
  710. /*
  711. * We're about to start this interrupt immediately,
  712. * hence the need to set the trigger configuration.
  713. * But the .set_type callback may have overridden the
  714. * flow handler, ignoring that we're dealing with a
  715. * chained interrupt. Reset it immediately because we
  716. * do know better.
  717. */
  718. if (type != IRQ_TYPE_NONE) {
  719. __irq_set_trigger(desc, type);
  720. desc->handle_irq = handle;
  721. }
  722. irq_settings_set_noprobe(desc);
  723. irq_settings_set_norequest(desc);
  724. irq_settings_set_nothread(desc);
  725. desc->action = &chained_action;
  726. irq_startup(desc, true);
  727. }
  728. }
  729. void
  730. __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
  731. const char *name)
  732. {
  733. unsigned long flags;
  734. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  735. if (!desc)
  736. return;
  737. __irq_do_set_handler(desc, handle, is_chained, name);
  738. irq_put_desc_busunlock(desc, flags);
  739. }
  740. EXPORT_SYMBOL_GPL(__irq_set_handler);
  741. void
  742. irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
  743. void *data)
  744. {
  745. unsigned long flags;
  746. struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
  747. if (!desc)
  748. return;
  749. __irq_do_set_handler(desc, handle, 1, NULL);
  750. desc->irq_common_data.handler_data = data;
  751. irq_put_desc_busunlock(desc, flags);
  752. }
  753. EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
  754. void
  755. irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
  756. irq_flow_handler_t handle, const char *name)
  757. {
  758. irq_set_chip(irq, chip);
  759. __irq_set_handler(irq, handle, 0, name);
  760. }
  761. EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
  762. void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
  763. {
  764. unsigned long flags;
  765. struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
  766. if (!desc)
  767. return;
  768. irq_settings_clr_and_set(desc, clr, set);
  769. irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
  770. IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
  771. if (irq_settings_has_no_balance_set(desc))
  772. irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
  773. if (irq_settings_is_per_cpu(desc))
  774. irqd_set(&desc->irq_data, IRQD_PER_CPU);
  775. if (irq_settings_can_move_pcntxt(desc))
  776. irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
  777. if (irq_settings_is_level(desc))
  778. irqd_set(&desc->irq_data, IRQD_LEVEL);
  779. irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
  780. irq_put_desc_unlock(desc, flags);
  781. }
  782. EXPORT_SYMBOL_GPL(irq_modify_status);
  783. /**
  784. * irq_cpu_online - Invoke all irq_cpu_online functions.
  785. *
  786. * Iterate through all irqs and invoke the chip.irq_cpu_online()
  787. * for each.
  788. */
  789. void irq_cpu_online(void)
  790. {
  791. struct irq_desc *desc;
  792. struct irq_chip *chip;
  793. unsigned long flags;
  794. unsigned int irq;
  795. for_each_active_irq(irq) {
  796. desc = irq_to_desc(irq);
  797. if (!desc)
  798. continue;
  799. raw_spin_lock_irqsave(&desc->lock, flags);
  800. chip = irq_data_get_irq_chip(&desc->irq_data);
  801. if (chip && chip->irq_cpu_online &&
  802. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  803. !irqd_irq_disabled(&desc->irq_data)))
  804. chip->irq_cpu_online(&desc->irq_data);
  805. raw_spin_unlock_irqrestore(&desc->lock, flags);
  806. }
  807. }
  808. /**
  809. * irq_cpu_offline - Invoke all irq_cpu_offline functions.
  810. *
  811. * Iterate through all irqs and invoke the chip.irq_cpu_offline()
  812. * for each.
  813. */
  814. void irq_cpu_offline(void)
  815. {
  816. struct irq_desc *desc;
  817. struct irq_chip *chip;
  818. unsigned long flags;
  819. unsigned int irq;
  820. for_each_active_irq(irq) {
  821. desc = irq_to_desc(irq);
  822. if (!desc)
  823. continue;
  824. raw_spin_lock_irqsave(&desc->lock, flags);
  825. chip = irq_data_get_irq_chip(&desc->irq_data);
  826. if (chip && chip->irq_cpu_offline &&
  827. (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
  828. !irqd_irq_disabled(&desc->irq_data)))
  829. chip->irq_cpu_offline(&desc->irq_data);
  830. raw_spin_unlock_irqrestore(&desc->lock, flags);
  831. }
  832. }
  833. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  834. /**
  835. * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
  836. * NULL)
  837. * @data: Pointer to interrupt specific data
  838. */
  839. void irq_chip_enable_parent(struct irq_data *data)
  840. {
  841. data = data->parent_data;
  842. if (data->chip->irq_enable)
  843. data->chip->irq_enable(data);
  844. else
  845. data->chip->irq_unmask(data);
  846. }
  847. /**
  848. * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
  849. * NULL)
  850. * @data: Pointer to interrupt specific data
  851. */
  852. void irq_chip_disable_parent(struct irq_data *data)
  853. {
  854. data = data->parent_data;
  855. if (data->chip->irq_disable)
  856. data->chip->irq_disable(data);
  857. else
  858. data->chip->irq_mask(data);
  859. }
  860. /**
  861. * irq_chip_ack_parent - Acknowledge the parent interrupt
  862. * @data: Pointer to interrupt specific data
  863. */
  864. void irq_chip_ack_parent(struct irq_data *data)
  865. {
  866. data = data->parent_data;
  867. data->chip->irq_ack(data);
  868. }
  869. EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
  870. /**
  871. * irq_chip_mask_parent - Mask the parent interrupt
  872. * @data: Pointer to interrupt specific data
  873. */
  874. void irq_chip_mask_parent(struct irq_data *data)
  875. {
  876. data = data->parent_data;
  877. data->chip->irq_mask(data);
  878. }
  879. EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
  880. /**
  881. * irq_chip_unmask_parent - Unmask the parent interrupt
  882. * @data: Pointer to interrupt specific data
  883. */
  884. void irq_chip_unmask_parent(struct irq_data *data)
  885. {
  886. data = data->parent_data;
  887. data->chip->irq_unmask(data);
  888. }
  889. EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
  890. /**
  891. * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
  892. * @data: Pointer to interrupt specific data
  893. */
  894. void irq_chip_eoi_parent(struct irq_data *data)
  895. {
  896. data = data->parent_data;
  897. data->chip->irq_eoi(data);
  898. }
  899. EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
  900. /**
  901. * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
  902. * @data: Pointer to interrupt specific data
  903. * @dest: The affinity mask to set
  904. * @force: Flag to enforce setting (disable online checks)
  905. *
  906. * Conditinal, as the underlying parent chip might not implement it.
  907. */
  908. int irq_chip_set_affinity_parent(struct irq_data *data,
  909. const struct cpumask *dest, bool force)
  910. {
  911. data = data->parent_data;
  912. if (data->chip->irq_set_affinity)
  913. return data->chip->irq_set_affinity(data, dest, force);
  914. return -ENOSYS;
  915. }
  916. /**
  917. * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
  918. * @data: Pointer to interrupt specific data
  919. * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
  920. *
  921. * Conditional, as the underlying parent chip might not implement it.
  922. */
  923. int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
  924. {
  925. data = data->parent_data;
  926. if (data->chip->irq_set_type)
  927. return data->chip->irq_set_type(data, type);
  928. return -ENOSYS;
  929. }
  930. EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
  931. /**
  932. * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
  933. * @data: Pointer to interrupt specific data
  934. *
  935. * Iterate through the domain hierarchy of the interrupt and check
  936. * whether a hw retrigger function exists. If yes, invoke it.
  937. */
  938. int irq_chip_retrigger_hierarchy(struct irq_data *data)
  939. {
  940. for (data = data->parent_data; data; data = data->parent_data)
  941. if (data->chip && data->chip->irq_retrigger)
  942. return data->chip->irq_retrigger(data);
  943. return 0;
  944. }
  945. /**
  946. * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
  947. * @data: Pointer to interrupt specific data
  948. * @vcpu_info: The vcpu affinity information
  949. */
  950. int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
  951. {
  952. data = data->parent_data;
  953. if (data->chip->irq_set_vcpu_affinity)
  954. return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
  955. return -ENOSYS;
  956. }
  957. /**
  958. * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
  959. * @data: Pointer to interrupt specific data
  960. * @on: Whether to set or reset the wake-up capability of this irq
  961. *
  962. * Conditional, as the underlying parent chip might not implement it.
  963. */
  964. int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
  965. {
  966. data = data->parent_data;
  967. if (data->chip->irq_set_wake)
  968. return data->chip->irq_set_wake(data, on);
  969. return -ENOSYS;
  970. }
  971. #endif
  972. /**
  973. * irq_chip_compose_msi_msg - Componse msi message for a irq chip
  974. * @data: Pointer to interrupt specific data
  975. * @msg: Pointer to the MSI message
  976. *
  977. * For hierarchical domains we find the first chip in the hierarchy
  978. * which implements the irq_compose_msi_msg callback. For non
  979. * hierarchical we use the top level chip.
  980. */
  981. int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  982. {
  983. struct irq_data *pos = NULL;
  984. #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
  985. for (; data; data = data->parent_data)
  986. #endif
  987. if (data->chip && data->chip->irq_compose_msi_msg)
  988. pos = data;
  989. if (!pos)
  990. return -ENOSYS;
  991. pos->chip->irq_compose_msi_msg(pos, msg);
  992. return 0;
  993. }
  994. /**
  995. * irq_chip_pm_get - Enable power for an IRQ chip
  996. * @data: Pointer to interrupt specific data
  997. *
  998. * Enable the power to the IRQ chip referenced by the interrupt data
  999. * structure.
  1000. */
  1001. int irq_chip_pm_get(struct irq_data *data)
  1002. {
  1003. int retval;
  1004. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
  1005. retval = pm_runtime_get_sync(data->chip->parent_device);
  1006. if (retval < 0) {
  1007. pm_runtime_put_noidle(data->chip->parent_device);
  1008. return retval;
  1009. }
  1010. }
  1011. return 0;
  1012. }
  1013. /**
  1014. * irq_chip_pm_put - Disable power for an IRQ chip
  1015. * @data: Pointer to interrupt specific data
  1016. *
  1017. * Disable the power to the IRQ chip referenced by the interrupt data
  1018. * structure, belongs. Note that power will only be disabled, once this
  1019. * function has been called for all IRQs that have called irq_chip_pm_get().
  1020. */
  1021. int irq_chip_pm_put(struct irq_data *data)
  1022. {
  1023. int retval = 0;
  1024. if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
  1025. retval = pm_runtime_put(data->chip->parent_device);
  1026. return (retval < 0) ? retval : 0;
  1027. }